SerialICE July 2010

serialice@serialice.com

7 participants
13 discussions

Various patches that I found useful
by Myles Watson 09 Jul '10

09 Jul '10

I put a copy of serialice.lua in the qemu directory and ran it from there. These patches refer to that file. size8.diff: The factory BIOS wanted to do 8-byte writes, so I split it into two 4-byte writes to minimize the changes necessary in SerialICE. serial.diff: When using a Coreboot image, serial output gets to be too verbose. Send it to Qemu's serial port, and make it much less verbose in the log. pci.diff: Add some helper functions so that PCI is easier to use in serialice.lua Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Some of the other patches I had for serialice.lua were specific to my boards. I wonder what the best way of keeping track of board-specific changes is. For example, the PCIe bar code conflicted with my chipset's initialization. Maybe we should have the SerialICE script query the board and then check which board it is? Another option would be to keep useful pieces that users should cobble together. Yet another option would be to keep multiple scripts for boards. Thanks, Myles

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Bricking (and unbricking) your board.
by Myles Watson 06 Jul '10

06 Jul '10

I was surprised how easy it was to brick my board. These ideas might be useful to somebody: Before you start messing with PCI & I/O values that might keep their state: - have a lspci -vvvxxx from the factory BIOS - record as much of the boot process from the factory BIOS as possible I wanted to collect the bit masks from my factory BIOS, so I modified the filter to return 0x0 and then 0xffffffff for the PCI registers. That way I could see which bits were being changed. After some of the registers were changed, I couldn't boot the board with Coreboot or the factory BIOS. I used SerialICE to set the PCI values to what they were in a saved run of the factory BIOS, and it booted again. Thanks, Myles

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[PATCH] Add HP DL165 G6
by Arne Georg Gleditsch 06 Jul '10

06 Jul '10

Support for the HP DL165 G6 mainboard. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> -- Arne.

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Readback error
by Myles Watson 06 Jul '10

06 Jul '10

All right. With the patches that I sent for Serengeti Cheetah support and Jordan's snserial tool http://www.coreboot.org/index.php?title=AMD_SimNow&redirect=no#Using_the_sn… + a simple patch for making it compile on my compiler (attached)... It works! I can run SimNOW with a SerialICE, snserial to make it go to /dev/pts/13, and qemu with the serialice patches. It looks like I need to update the lua script so that I don't kill the serial port, since this is the last thing I get: MEM: writel fee00380 <= 00000033 * IO: outb 002e <= 87 IO: outb 002e <= 87 IO: outb 002e <= 07 IO: outb 002f <= 02 IO: outb 002e <= 30 IO: outb 002f <= 00 IO: outb 002e <= 60 I thought I'd use gdb to skip over those, but when I use gdb to connect (adding -s -S to the qemu command line), I get a lot of these messages: MEM: readl 000c9900 => ffffffff * Readback error! 38/39 Readback error! 63/34 Any ideas of why connecting gdb would cause readback errors on the port? Thanks, Myles

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[commit] r104 - trunk/SerialICE/mainboard
by repository service 02 Jul '10

02 Jul '10

Author: stepan Date: Fri Jul 2 21:06:05 2010 New Revision: 104 URL: http://www.serialice.com/trac/serialice/changeset/104 Log: Fix the two Tyan boards from Myles latest patch which was Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/SerialICE/mainboard/tyan_s2892.c trunk/SerialICE/mainboard/tyan_s2895.c Modified: trunk/SerialICE/mainboard/tyan_s2892.c ============================================================================== --- trunk/SerialICE/mainboard/tyan_s2892.c Fri Jul 2 16:49:53 2010 (r103) +++ trunk/SerialICE/mainboard/tyan_s2892.c Fri Jul 2 21:06:05 2010 (r104) @@ -18,64 +18,44 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -const char boardname[33]="Tyan S2895 "; +const char boardname[33]="Tyan S2892 "; #define SUPERIO_CONFIG_PORT 0x2e -#define SUPERIO_GPIO_IO_BASE 0x400 +#define W83627HF_SP1 2 -#define LPC47B397_SP1 4 /* Com1 */ -#define LPC47B397_RT 10 /* Runtime reg */ - -static void lpc47b397_gpio_offset_out(unsigned iobase, unsigned offset, unsigned value) -{ - outb(value,iobase+offset); -} - -static unsigned lpc47b397_gpio_offset_in(unsigned iobase, unsigned offset) -{ - return inb(iobase+offset); -} - - -/* Functions for the SMSC LPC47B272 & B397 */ -static void smsc_enable_serial(u16 port, u8 dev, unsigned iobase) -{ - pnp_enter_ext_func_mode_alt(port); - pnp_set_logical_device(port, dev); - pnp_set_enable(port, 0); - pnp_set_iobase0(port, iobase); - pnp_set_enable(port, 1); - pnp_exit_ext_func_mode(port); -} - -static void superio_init(void) +static void sio_setup(void) { unsigned value; u32 dword; u8 byte; - pci_write_config32(PCI_ADDR(0, 1, 0, 0xac), 0x047f0400); - byte = pci_read_config8(PCI_ADDR(0, 1 , 0, 0x7b)); byte |= 0x20; pci_write_config8(PCI_ADDR(0, 1 , 0, 0x7b), byte); dword = pci_read_config32(PCI_ADDR(0, 1 , 0, 0xa0)); - dword |= (1<<29)|(1<<0); + dword |= (1<<0); pci_write_config32(PCI_ADDR(0, 1 , 0, 0xa0), dword); +} + +static void superio_init(void) +{ + int i; + pnp_enter_ext_func_mode(SUPERIO_CONFIG_PORT); + + /* Enable the serial port. */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, W83627HF_SP1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT, CONFIG_SERIAL_PORT); + pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT, 1); - dword = pci_read_config32(PCI_ADDR(0, 1, 0, 0xa4)); - dword |= (1<<16); - pci_write_config32(PCI_ADDR(0, 1, 0, 0xa4), dword); - - smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_RT, SUPERIO_GPIO_IO_BASE); - value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); - value &= 0xbf; - lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); } static void chipset_init(void) { + sio_setup(); superio_init(); __asm__ __volatile__("\ Modified: trunk/SerialICE/mainboard/tyan_s2895.c ============================================================================== --- trunk/SerialICE/mainboard/tyan_s2895.c Fri Jul 2 16:49:53 2010 (r103) +++ trunk/SerialICE/mainboard/tyan_s2895.c Fri Jul 2 21:06:05 2010 (r104) @@ -77,7 +77,7 @@ static void chipset_init(void) { superio_init(); - + smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_SP1, CONFIG_SERIAL_PORT); __asm__ __volatile__("\ jmp skip\n\ .align 128\n\

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Porting to new boards
by Myles Watson 02 Jul '10

02 Jul '10

I'd like to have SerialICE working on my Tyan boards, but I don't see any output from the serial port after my porting attempt. I took a step back and tried Qemu and SimNOW. I see the SerialICE prompt, but I don't know how to test that interface. SerialICE v1.5 (Jun 21 2010) > I was expecting to be able to enter some commands at the prompt, to read/write memory locations and registers. I'm attaching the patches I am working with: emulators.diff: Add trivial support for qemu and copy support for SimNOW from Tyan s2912 since they use the same SuperIO chip. pci_read.diff: Add pci_read functions, since my Tyan s2895 Serial init code uses them (copied from Coreboot) tyan.diff: Add code for s2895 (s2892 is just a copy of s2895 right now) debug_romstrap.diff: Make the romstrap end up looking like Coreboot's romstrap. Status: Qemu & SimNOW give me a prompt, but I don't know how to interact with it. Tyan s2895 - No output. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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[commit] r103 - trunk/qemu-0.11.0
by repository service 02 Jul '10

02 Jul '10

Author: stepan Date: Fri Jul 2 16:49:53 2010 New Revision: 103 URL: http://www.serialice.com/trac/serialice/changeset/103 Log: serialice_io_read_filter was being passed the wrong size for words and longs. It was harder to find because serialice_io_read_log was being passed the correct size, and when the filter returns true, the log isn't called. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/qemu-0.11.0/serialice.c Modified: trunk/qemu-0.11.0/serialice.c ============================================================================== --- trunk/qemu-0.11.0/serialice.c Fri Jul 2 16:49:13 2010 (r102) +++ trunk/qemu-0.11.0/serialice.c Fri Jul 2 16:49:53 2010 (r103) @@ -720,7 +720,7 @@ uint16_t ret; uint32_t data; - if (serialice_io_read_filter(&data, port, 1)) { + if (serialice_io_read_filter(&data, port, 2)) { return data & 0xffff; } @@ -739,7 +739,7 @@ uint32_t ret; uint32_t data; - if (serialice_io_read_filter(&data, port, 1)) { + if (serialice_io_read_filter(&data, port, 4)) { return data; }

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[commit] r102 - trunk/qemu-0.11.0
by repository service 02 Jul '10

02 Jul '10

Author: stepan Date: Fri Jul 2 16:49:13 2010 New Revision: 102 URL: http://www.serialice.com/trac/serialice/changeset/102 Log: Fix a minor spelling error. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/qemu-0.11.0/serialice.c Modified: trunk/qemu-0.11.0/serialice.c ============================================================================== --- trunk/qemu-0.11.0/serialice.c Fri Jul 2 16:43:27 2010 (r101) +++ trunk/qemu-0.11.0/serialice.c Fri Jul 2 16:49:13 2010 (r102) @@ -1171,7 +1171,7 @@ /* ... and wait for it to appear */ if (serialice_wait_prompt() == 0) { - printf("target alife!\n"); + printf("target alive!\n"); } else { printf("target not ok!\n"); exit(1); @@ -1191,7 +1191,7 @@ printf("SerialICE: LUA init...\n"); serialice_lua_init(); - /* Let the rest of Qemu know we're alife */ + /* Let the rest of Qemu know we're alive */ serialice_active = 1; }

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[commit] r101 - in trunk/SerialICE: . mainboard
by repository service 02 Jul '10

02 Jul '10

Author: stepan Date: Fri Jul 2 16:43:27 2010 New Revision: 101 URL: http://www.serialice.com/trac/serialice/changeset/101 Log: Add code for s2895 (s2892 is just a copy of s2895 right now) Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/SerialICE/mainboard/tyan_s2892.c trunk/SerialICE/mainboard/tyan_s2895.c Modified: trunk/SerialICE/Kconfig trunk/SerialICE/start.S Modified: trunk/SerialICE/Kconfig ============================================================================== --- trunk/SerialICE/Kconfig Fri Jul 2 16:42:04 2010 (r100) +++ trunk/SerialICE/Kconfig Fri Jul 2 16:43:27 2010 (r101) @@ -69,6 +69,14 @@ config BOARD_TELEVIDEO_TC7010 bool "Televideo TC7010" +config BOARD_TYAN_S2892 + bool "Tyan S2892" + select CK804_ROMSTRAP + +config BOARD_TYAN_S2895 + bool "Tyan S2895" + select CK804_ROMSTRAP + config BOARD_TYAN_S2912 bool "Tyan S2912" select MCP55_ROMSTRAP @@ -93,6 +101,8 @@ default "asus_p2b.c" if BOARD_ASUS_P2B default "asrock_939a785gmh.c" if BOARD_ASROCK_939A785GMH default "televideo_tc7010.c" if BOARD_TELEVIDEO_TC7010 + default "tyan_s2892.c" if BOARD_TYAN_S2892 + default "tyan_s2895.c" if BOARD_TYAN_S2895 default "tyan_s2912.c" if BOARD_TYAN_S2912 default "hp_dl165_g6.c" if BOARD_HP_DL165_G6 choice @@ -229,6 +239,11 @@ depends on EXPERT default n +config CK804_ROMSTRAP + bool "NVIDIA CK804 Southbridge ROMSTRAP" + depends on EXPERT + default n + config MCP55_ROMSTRAP bool "NVIDIA MCP55 Southbridge ROMSTRAP" depends on EXPERT Added: trunk/SerialICE/mainboard/tyan_s2892.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/SerialICE/mainboard/tyan_s2892.c Fri Jul 2 16:43:27 2010 (r101) @@ -0,0 +1,104 @@ +/* + * SerialICE + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2010 Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="Tyan S2895 "; + +#define SUPERIO_CONFIG_PORT 0x2e +#define SUPERIO_GPIO_IO_BASE 0x400 + +#define LPC47B397_SP1 4 /* Com1 */ +#define LPC47B397_RT 10 /* Runtime reg */ + +static void lpc47b397_gpio_offset_out(unsigned iobase, unsigned offset, unsigned value) +{ + outb(value,iobase+offset); +} + +static unsigned lpc47b397_gpio_offset_in(unsigned iobase, unsigned offset) +{ + return inb(iobase+offset); +} + + +/* Functions for the SMSC LPC47B272 & B397 */ +static void smsc_enable_serial(u16 port, u8 dev, unsigned iobase) +{ + pnp_enter_ext_func_mode_alt(port); + pnp_set_logical_device(port, dev); + pnp_set_enable(port, 0); + pnp_set_iobase0(port, iobase); + pnp_set_enable(port, 1); + pnp_exit_ext_func_mode(port); +} + +static void superio_init(void) +{ + unsigned value; + u32 dword; + u8 byte; + + pci_write_config32(PCI_ADDR(0, 1, 0, 0xac), 0x047f0400); + + byte = pci_read_config8(PCI_ADDR(0, 1 , 0, 0x7b)); + byte |= 0x20; + pci_write_config8(PCI_ADDR(0, 1 , 0, 0x7b), byte); + + dword = pci_read_config32(PCI_ADDR(0, 1 , 0, 0xa0)); + dword |= (1<<29)|(1<<0); + pci_write_config32(PCI_ADDR(0, 1 , 0, 0xa0), dword); + + dword = pci_read_config32(PCI_ADDR(0, 1, 0, 0xa4)); + dword |= (1<<16); + pci_write_config32(PCI_ADDR(0, 1, 0, 0xa4), dword); + + smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_RT, SUPERIO_GPIO_IO_BASE); + value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); + value &= 0xbf; + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); +} + +static void chipset_init(void) +{ + superio_init(); + + __asm__ __volatile__("\ + jmp skip\n\ + .align 128\n\ + .globl ck804_romstrap\n\ + ck804_romstrap:\n\ + .long 0x2b16d065\n\ + .long 0x0\n\ + .long 0x0\n\ + .long linkedlist\n\ + linkedlist:\n\ + .long 0x0003001C // 10h\n\ + .long 0x08000000 // 14h\n\ + .long 0x00000000 // 18h\n\ + .long 0xFFFFFFFF // 1Ch\n\ + .long 0xFFFFFFFF // 20h\n\ + .long 0xFFFFFFFF // 24h\n\ + .long 0xFFFFFFFF // 28h\n\ + .long 0xFFFFFFFF // 2Ch\n\ + .long 0x81543266 // 30h, MAC address low 4 byte\n\ + .long 0x000000E0 // 34h, MAC address high 4 byte\n\ + .long 0x002309CE // 38h, UUID low 4 byte\n\ + .long 0x00E08100 // 3Ch, UUID high 4 byte\n\ + skip:\n"); +} Added: trunk/SerialICE/mainboard/tyan_s2895.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/SerialICE/mainboard/tyan_s2895.c Fri Jul 2 16:43:27 2010 (r101) @@ -0,0 +1,104 @@ +/* + * SerialICE + * + * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2010 Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="Tyan S2895 "; + +#define SUPERIO_CONFIG_PORT 0x2e +#define SUPERIO_GPIO_IO_BASE 0x400 + +#define LPC47B397_SP1 4 /* Com1 */ +#define LPC47B397_RT 10 /* Runtime reg */ + +static void lpc47b397_gpio_offset_out(unsigned iobase, unsigned offset, unsigned value) +{ + outb(value,iobase+offset); +} + +static unsigned lpc47b397_gpio_offset_in(unsigned iobase, unsigned offset) +{ + return inb(iobase+offset); +} + + +/* Functions for the SMSC LPC47B272 & B397 */ +static void smsc_enable_serial(u16 port, u8 dev, unsigned iobase) +{ + pnp_enter_ext_func_mode_alt(port); + pnp_set_logical_device(port, dev); + pnp_set_enable(port, 0); + pnp_set_iobase0(port, iobase); + pnp_set_enable(port, 1); + pnp_exit_ext_func_mode(port); +} + +static void superio_init(void) +{ + unsigned value; + u32 dword; + u8 byte; + + pci_write_config32(PCI_ADDR(0, 1, 0, 0xac), 0x047f0400); + + byte = pci_read_config8(PCI_ADDR(0, 1 , 0, 0x7b)); + byte |= 0x20; + pci_write_config8(PCI_ADDR(0, 1 , 0, 0x7b), byte); + + dword = pci_read_config32(PCI_ADDR(0, 1 , 0, 0xa0)); + dword |= (1<<29)|(1<<0); + pci_write_config32(PCI_ADDR(0, 1 , 0, 0xa0), dword); + + dword = pci_read_config32(PCI_ADDR(0, 1, 0, 0xa4)); + dword |= (1<<16); + pci_write_config32(PCI_ADDR(0, 1, 0, 0xa4), dword); + + smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_RT, SUPERIO_GPIO_IO_BASE); + value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); + value &= 0xbf; + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); +} + +static void chipset_init(void) +{ + superio_init(); + + __asm__ __volatile__("\ + jmp skip\n\ + .align 128\n\ + .globl ck804_romstrap\n\ + ck804_romstrap:\n\ + .long 0x2b16d065\n\ + .long 0x0\n\ + .long 0x0\n\ + .long linkedlist\n\ + linkedlist:\n\ + .long 0x0003001C // 10h\n\ + .long 0x08000000 // 14h\n\ + .long 0x00000000 // 18h\n\ + .long 0xFFFFFFFF // 1Ch\n\ + .long 0xFFFFFFFF // 20h\n\ + .long 0xFFFFFFFF // 24h\n\ + .long 0xFFFFFFFF // 28h\n\ + .long 0xFFFFFFFF // 2Ch\n\ + .long 0x81543266 // 30h, MAC address low 4 byte\n\ + .long 0x000000E0 // 34h, MAC address high 4 byte\n\ + .long 0x002309CE // 38h, UUID low 4 byte\n\ + .long 0x00E08100 // 3Ch, UUID high 4 byte\n\ + skip:\n"); +} Modified: trunk/SerialICE/start.S ============================================================================== --- trunk/SerialICE/start.S Fri Jul 2 16:42:04 2010 (r100) +++ trunk/SerialICE/start.S Fri Jul 2 16:43:27 2010 (r101) @@ -124,6 +124,15 @@ .long via_romstrap #endif +#ifdef CONFIG_CK804_ROMSTRAP +/* Pointers to nvidia tables at 0xffffe0 */ + . = 0x10; + .long ck804_romstrap + .long ck804_romstrap + .long ck804_romstrap + .long ck804_romstrap +#endif + #ifdef CONFIG_MCP55_ROMSTRAP /* Pointers to nvidia tables at 0xffffe0 */ . = 0x10;

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[commit] r100 - trunk/SerialICE
by repository service 02 Jul '10

02 Jul '10

Author: stepan Date: Fri Jul 2 16:42:04 2010 New Revision: 100 URL: http://www.serialice.com/trac/serialice/changeset/100 Log: Add pci_read functions, since Tyan s2895 serial init code uses them. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/SerialICE/chipset.c Modified: trunk/SerialICE/chipset.c ============================================================================== --- trunk/SerialICE/chipset.c Fri Jul 2 16:39:51 2010 (r99) +++ trunk/SerialICE/chipset.c Fri Jul 2 16:42:04 2010 (r100) @@ -40,6 +40,24 @@ outl(value, 0xcfc); } +static u8 pci_read_config8(u32 addr) +{ + outl(addr & ~3, 0xcf8); + inb(0xcfc + (addr & 3)); +} + +static u16 pci_read_config16(u32 addr) +{ + outl(addr & ~3, 0xcf8); + inw(0xcfc + (addr & 2)); +} + +static u32 pci_read_config32(u32 addr) +{ + outl(addr & ~3, 0xcf8); + inl(0xcfc); +} + /* PnP / SuperIO access functions */ static inline void pnp_write_register(u16 port, u8 reg, u8 value)

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SerialICE July 2010