New patch to review for serialice: 60faa90 Add the Asus F2A85-M

[Rudolf Marek]

Rudolf Marek ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1680

-gerrit

commit 60faa90c100d0276a6dab2ff0e1a71919507f537
Author: Rudolf Marek 
Date:   Sun Nov 4 12:26:03 2012 +0100

Add the Asus F2A85-M

Add the Asus F2A85-M, while at it, add also SBxxx specific
    snippets which may be used by future boards. It contains
    handy stuff to enable the LPC decodes and also it
    enables clock output if SB clockchip is used.

Change-Id: Ieb782bdb35831568d61fd57c7c956bf4cc9747c7
    Signed-off-by: Rudolf Marek 
---
 SerialICE/Kconfig                  |  6 +++
 SerialICE/mainboard/asus_f2a85-m.c | 50 +++++++++++++++++++
 SerialICE/southbridge/amd-sbxxx.c  | 99 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 155 insertions(+)

diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig
index 7199453..18826f2 100644
--- a/SerialICE/Kconfig
+++ b/SerialICE/Kconfig
@@ -45,6 +45,10 @@ config BOARD_INTEL_D945GCLF
 config BOARD_DELL_S1850
    bool "Dell PowerEdge S1850"

+config BOARD_ASUS_F2A85_M
+	bool "ASUS F2A85-M"
+	select BUILD_XMMSTACK
+
 config BOARD_ASUS_M2V_MX_SE
    bool "ASUS M2V-MX SE"
    select VIA_ROMSTRAP
@@ -140,10 +144,12 @@ config BOARD_INIT
    default "aopen_dxpl-plus.c" if BOARD_AOPEN_DXPL_PLUS
    default "via_epia_m850.c" if BOARD_VIA_EPIA_M850
    default "intel_d845gbv2.c" if BOARD_INTEL_D845GBV2
+	default "asus_f2a85-m.c" if BOARD_ASUS_F2A85_M

config SOUTHBRIDGE_INIT
    string
    default "southbridge/intel-ich7.c" if BOARD_KONTRON_986LCD_M
+	default "southbridge/amd-sbxxx.c" if BOARD_ASUS_F2A85_M

config SUPERIO_INIT
    string
diff --git a/SerialICE/mainboard/asus_f2a85-m.c b/SerialICE/mainboard/asus_f2a85-m.c
new file mode 100644
index 0000000..532421d
--- /dev/null
+++ b/SerialICE/mainboard/asus_f2a85-m.c
@@ -0,0 +1,50 @@
+/*
+ * SerialICE 
+ *
+ * Copyright (C) 2006 Uwe Hermann 
+ * Copyright (C) 2012 Rudolf Marek 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+const char boardname[33]="Asus F2A85-M                    ";
+
+#define SUPERIO_CONFIG_PORT		0x2e
+
+static void superio_init(void)
+{
+	u8 byte;
+	pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT);
+
+	/* Disable the watchdog. */
+	pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7);
+	pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00);
+
+	/* Enable the serial port. */
+	pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */
+	pnp_set_enable(SUPERIO_CONFIG_PORT, 0);
+	pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8);
+	pnp_set_irq0(SUPERIO_CONFIG_PORT, 4);
+	pnp_set_enable(SUPERIO_CONFIG_PORT, 1);
+
+	pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT);
+}
+
+
+static void chipset_init(void)
+{
+	southbridge_init();
+	sbxxx_enable_48mhzout();
+	superio_init();
+}
diff --git a/SerialICE/southbridge/amd-sbxxx.c b/SerialICE/southbridge/amd-sbxxx.c
new file mode 100644
index 0000000..d921813
--- /dev/null
+++ b/SerialICE/southbridge/amd-sbxxx.c
@@ -0,0 +1,99 @@
+/*
+ * SerialICE
+ *
+ * Copyright (C) 2012 Rudolf Marek 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This initializes AMD SBxx that
+ * o Ports 0x2e/0x2f 0x4e/0x4f and 0x3f8 are routed to superio
+ * o the MMIO regs of SB are accesible
+ * o enables POST card (see #if 0)
+ */
+
+static void sbxxx_enable_48mhzout(void)
+{
+	volatile u32 *p1;
+	u32 dword;
+
+	/* most likely programming to 48MHz out signal */
+	p1 = (u32 *) 0xFED80E28;
+	dword = (*p1) & 0xFFC7FFFF;
+	dword |= 0x00100000;
+	*p1 = dword;
+
+	p1 = (u32 *) 0xFED80E40;
+	*p1 = (*p1) & 0xFFFFFF7F;
+}
+
+static void southbridge_init(void)
+{
+	u16 reg16;
+	u32 reg32;
+
+	/* route FED00000 - FEDFFFFF as non-posted to SB */
+	pci_write_config32(PCI_ADDR(0, 0x18, 1, 0x84), 0x00FEDF00 | (1 << 7));
+	/* lowest NP address is HPET at FED00000 */
+	pci_write_config32(PCI_ADDR(0, 0x18, 1, 0x80), (0xFED00000 >> 8) | 3);
+
+	/* Send all IO (0000-FFFF) to southbridge. */
+	pci_write_config32(PCI_ADDR(0, 0x18, 1, 0xc4),  0x0000F000);
+	pci_write_config32(PCI_ADDR(0, 0x18, 1, 0xc0),  0x00000003);
+
+	/* handy for POST card on PCI */
+#if 0
+	/* Chip Control: Enable subtractive decoding */
+	byte = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x40));
+	byte |= 1 << 5;
+	pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x40), byte);
+
+	/* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */
+	byte = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x4B));
+	byte |= 1 << 7;
+	pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x4B), byte);
+
+	/* The same IO Base and IO Limit here is meaningful because we set the
+	 * bridge to be subtractive. During early setup stage, we have to make
+	 * sure that data can go through port 0x80.
+	 */
+	/* IO Base: 0xf000 */
+	byte = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x1C));
+	byte |= 0xF << 4;
+	pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x1C), byte);
+
+	/* IO Limit: 0xf000 */
+	byte = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x1D));
+	byte |= 0xF << 4;
+	pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x1D), byte);
+
+	/* PCI Command: Enable IO response */
+	byte = pci_read_config8(PCI_ADDR(0, 0x14, 4, 0x4));
+	byte |= 1 << 0;
+	pci_write_config8(PCI_ADDR(0, 0x14, 4, 0x4) , byte);
+
+	/* kill LPC decode of port 80, if you have LPC post card just invert and enable that */
+	byte = pci_read_config8(PCI_ADDR(0, 0x14, 0, 0x4A));
+	byte &= ~(1 << 5);	/* disable lpc port 80 */
+	pci_write_config8(PCI_ADDR(0, 0x14, 0, 0x4A), byte);
+#endif
+
+	/* SB  MMIO range decode enable */
+	outb(0x24, 0xcd6);
+	outb(0x1, 0xcd7);
+
+	/* Enable LPC decoding of 0x2e/0x2f, 0x4e/0x4f 0x3f8  */
+	pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x44), (1<<6));
+	pci_write_config8(PCI_ADDR(0, 0x14, 3, 0x48), (1 << 1) | (1 << 0));
+}