Author: stepan Date: Sun Mar 14 12:18:11 2010 New Revision: 96 URL: http://www.serialice.com/trac/serialice/changeset/96
Log: Add slightly modified version of Peter Bannis' TC7010 port.
Added: trunk/SerialICE/mainboard/televideo_tc7010.c Modified: trunk/SerialICE/Kconfig
Modified: trunk/SerialICE/Kconfig ============================================================================== --- trunk/SerialICE/Kconfig Tue Jan 26 02:49:02 2010 (r95) +++ trunk/SerialICE/Kconfig Sun Mar 14 12:18:11 2010 (r96) @@ -60,6 +60,9 @@ config BOARD_ASUS_P2B bool "ASUS P2B"
+config BOARD_TELEVIDEO_TC7010 + bool "Televideo TC7010" + endchoice
config BOARD_INIT @@ -74,6 +77,7 @@ default "thomson_ip1000.c" if BOARD_THOMSON_IP1000 default "asus_p2b.c" if BOARD_ASUS_P2B default "asrock_939a785gmh.c" if BOARD_ASROCK_939A785GMH + default "televideo_tc7010.c" if BOARD_TELEVIDEO_TC7010 choice prompt "Target communication"
Added: trunk/SerialICE/mainboard/televideo_tc7010.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/SerialICE/mainboard/televideo_tc7010.c Sun Mar 14 12:18:11 2010 (r96) @@ -0,0 +1,60 @@ +/* + * SerialICE + * + * Copyright (C) 2010 Peter Bannis + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33] = "Televideo TC7010 "; + +#define SUPERIO_CONFIG_PORT 0x2e +#define PM_BASE 0xe8 + +static void superio_init(void) +{ + /* Set base address of power management unit */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 8); + pnp_set_enable(SUPERIO_CONFIG_PORT, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT, PM_BASE); + pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + + /* Use on-chip clock multiplier */ + outb(0x03, PM_BASE); + outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1); + + /* Wait for the clock to stabilise */ + while (!(inb(PM_BASE + 1) & 0x80)) ; + + /* Enable the serial ports. */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 6); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + + /* Set LDN 5 UART Mode */ + outb(0x21, SUPERIO_CONFIG_PORT); + outb(inb(SUPERIO_CONFIG_PORT + 1) | (1 << 3), SUPERIO_CONFIG_PORT + 1); + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 5); /* COM2 */ + pnp_set_enable(SUPERIO_CONFIG_PORT, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x2f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT, 3); + pnp_set_enable(SUPERIO_CONFIG_PORT, 1); +} + +static void chipset_init(void) +{ + superio_init(); +}