New patch to review for serialice: d6b9880 Add support for Intel D945GNT

[Stefan Tauner]

Stefan Tauner ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1578

-gerrit

commit d6b9880d709ab5732242cf3fedfdc26853049f9b
Author: Stefan Tauner 
Date:   Sun Oct 14 06:32:33 2012 +0200

Add support for Intel D945GNT

This is based on the patch from Beata dalHagen, see
    http://serialice.com/pipermail/serialice/2012-May/000372.html
    This version has only been compile tested.
    It seems like we should use kconfig more, but i don't know this
    stuff good enough yet. Still better than copying the whole file :)

Change-Id: Ia4058d0f73f8357b97d7c0fe1868d9a289c4e2f7
    Signed-off-by: Stefan Tauner 
---
 SerialICE/Kconfig                    |  5 ++++-
 SerialICE/mainboard/intel_d945gclf.c | 40 ++++++++++++++++++++++--------------
 2 files changed, 29 insertions(+), 16 deletions(-)

diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig
index 7199453..4ca4e98 100644
--- a/SerialICE/Kconfig
+++ b/SerialICE/Kconfig
@@ -42,6 +42,9 @@ config BOARD_RODA_RK886EX
 config BOARD_INTEL_D945GCLF
    bool "Intel D945GCLF"

+config BOARD_INTEL_D945GNT
+	bool "Intel D945GNT"
+
 config BOARD_DELL_S1850
    bool "Dell PowerEdge S1850"

@@ -119,7 +122,7 @@ config BOARD_INIT
    default "amd_serengeti-cheetah.c" if BOARD_AMD_SERENGETI_CHEETAH
    default "kontron_986lcd-m.c" if BOARD_KONTRON_986LCD_M
    default "roda_rk886ex.c" if BOARD_RODA_RK886EX
-	default "intel_d945gclf.c" if BOARD_INTEL_D945GCLF
+	default "intel_d945gclf.c" if BOARD_INTEL_D945GCLF || BOARD_INTEL_D945GNT
    default "dell_s1850.c" if BOARD_DELL_S1850
    default "asus_m2v-mx_se.c" if BOARD_ASUS_M2V_MX_SE
    default "asus_k8v-x.c" if BOARD_ASUS_K8V_X
diff --git a/SerialICE/mainboard/intel_d945gclf.c b/SerialICE/mainboard/intel_d945gclf.c
index c78f3bc..5b9ae13 100644
--- a/SerialICE/mainboard/intel_d945gclf.c
+++ b/SerialICE/mainboard/intel_d945gclf.c
@@ -17,9 +17,15 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

-/* This is a chipset init file for the Intel D945GCLF mainboard */
+/* This is a chipset init file for the Intel D945GCLF/D945GNT mainboards */

+#if defined(CONFIG_BOARD_INTEL_D945GCLF)
 const char boardname[33]="Intel D945GCLF                  ";
+#elif defined(CONFIG_BOARD_INTEL_D945GNT)
+const char boardname[33]="Intel D945GNT                   ";
+#else
+#error "Unsupported board"
+#endif

/* Hardware specific functions */

@@ -64,28 +70,32 @@ static void southbridge_init(void)
    outw(0x0002, TCOBASE + 0x06);
 }

-static void superio_init(void)
+static void superio_init(u8 cfg_port, u8 com_port, u8 pm)
 {
-	pnp_enter_ext_func_mode_alt(0x2e);
+	pnp_enter_ext_func_mode_alt(cfg_port);

-	pnp_set_logical_device(0x2e, 4); // COM-A
-	pnp_set_enable(0x2e, 0);
-	pnp_set_iobase0(0x2e, 0x3f8);
-	pnp_set_irq0(0x2e, 4);
-	pnp_set_enable(0x2e, 1);
+	pnp_set_logical_device(cfg_port, com_port);
+	pnp_set_enable(cfg_port, 0);
+	pnp_set_iobase0(cfg_port, 0x3f8);
+	pnp_set_irq0(cfg_port, 4);
+	pnp_set_enable(cfg_port, 1);

-	pnp_set_logical_device(0x2e, 10); // PM
-	pnp_set_enable(0x2e, 0);
-	pnp_set_iobase0(0x2e, 0x680);
-	pnp_set_irq0(0x2e, 3);
-	pnp_set_enable(0x2e, 1);
+	pnp_set_logical_device(cfg_port, pm);
+	pnp_set_enable(cfg_port, 0);
+	pnp_set_iobase0(cfg_port, 0x680);
+	pnp_set_irq0(cfg_port, 3);
+	pnp_set_enable(cfg_port, 1);

-	pnp_exit_ext_func_mode(0x2e);
+	pnp_exit_ext_func_mode(cfg_port);
 }

static void chipset_init(void)
 {
    southbridge_init();
-	superio_init();
+#if defined(CONFIG_BOARD_INTEL_D945GCLF)
+	superio_init(0x2e, 4, 10);
+#elif defined(CONFIG_BOARD_INTEL_D945GNT)
+	superio_init(0x2e, 3, 4); // LPC47M182
+#endif
 }