Author: stepan Date: Fri Jul 2 16:43:27 2010 New Revision: 101 URL: http://www.serialice.com/trac/serialice/changeset/101
Log: Add code for s2895 (s2892 is just a copy of s2895 right now) Signed-off-by: Myles Watson mylesgw@gmail.com Acked-by: Stefan Reinauer stepan@coresystems.de
Added: trunk/SerialICE/mainboard/tyan_s2892.c trunk/SerialICE/mainboard/tyan_s2895.c Modified: trunk/SerialICE/Kconfig trunk/SerialICE/start.S
Modified: trunk/SerialICE/Kconfig ============================================================================== --- trunk/SerialICE/Kconfig Fri Jul 2 16:42:04 2010 (r100) +++ trunk/SerialICE/Kconfig Fri Jul 2 16:43:27 2010 (r101) @@ -69,6 +69,14 @@ config BOARD_TELEVIDEO_TC7010 bool "Televideo TC7010"
+config BOARD_TYAN_S2892 + bool "Tyan S2892" + select CK804_ROMSTRAP + +config BOARD_TYAN_S2895 + bool "Tyan S2895" + select CK804_ROMSTRAP + config BOARD_TYAN_S2912 bool "Tyan S2912" select MCP55_ROMSTRAP @@ -93,6 +101,8 @@ default "asus_p2b.c" if BOARD_ASUS_P2B default "asrock_939a785gmh.c" if BOARD_ASROCK_939A785GMH default "televideo_tc7010.c" if BOARD_TELEVIDEO_TC7010 + default "tyan_s2892.c" if BOARD_TYAN_S2892 + default "tyan_s2895.c" if BOARD_TYAN_S2895 default "tyan_s2912.c" if BOARD_TYAN_S2912 default "hp_dl165_g6.c" if BOARD_HP_DL165_G6 choice @@ -229,6 +239,11 @@ depends on EXPERT default n
+config CK804_ROMSTRAP + bool "NVIDIA CK804 Southbridge ROMSTRAP" + depends on EXPERT + default n + config MCP55_ROMSTRAP bool "NVIDIA MCP55 Southbridge ROMSTRAP" depends on EXPERT
Added: trunk/SerialICE/mainboard/tyan_s2892.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/SerialICE/mainboard/tyan_s2892.c Fri Jul 2 16:43:27 2010 (r101) @@ -0,0 +1,104 @@ +/* + * SerialICE + * + * Copyright (C) 2009 Uwe Hermann uwe@hermann-uwe.de + * Copyright (C) 2010 Arne Georg Gleditsch arne.gleditsch@numascale.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="Tyan S2895 "; + +#define SUPERIO_CONFIG_PORT 0x2e +#define SUPERIO_GPIO_IO_BASE 0x400 + +#define LPC47B397_SP1 4 /* Com1 */ +#define LPC47B397_RT 10 /* Runtime reg */ + +static void lpc47b397_gpio_offset_out(unsigned iobase, unsigned offset, unsigned value) +{ + outb(value,iobase+offset); +} + +static unsigned lpc47b397_gpio_offset_in(unsigned iobase, unsigned offset) +{ + return inb(iobase+offset); +} + + +/* Functions for the SMSC LPC47B272 & B397 */ +static void smsc_enable_serial(u16 port, u8 dev, unsigned iobase) +{ + pnp_enter_ext_func_mode_alt(port); + pnp_set_logical_device(port, dev); + pnp_set_enable(port, 0); + pnp_set_iobase0(port, iobase); + pnp_set_enable(port, 1); + pnp_exit_ext_func_mode(port); +} + +static void superio_init(void) +{ + unsigned value; + u32 dword; + u8 byte; + + pci_write_config32(PCI_ADDR(0, 1, 0, 0xac), 0x047f0400); + + byte = pci_read_config8(PCI_ADDR(0, 1 , 0, 0x7b)); + byte |= 0x20; + pci_write_config8(PCI_ADDR(0, 1 , 0, 0x7b), byte); + + dword = pci_read_config32(PCI_ADDR(0, 1 , 0, 0xa0)); + dword |= (1<<29)|(1<<0); + pci_write_config32(PCI_ADDR(0, 1 , 0, 0xa0), dword); + + dword = pci_read_config32(PCI_ADDR(0, 1, 0, 0xa4)); + dword |= (1<<16); + pci_write_config32(PCI_ADDR(0, 1, 0, 0xa4), dword); + + smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_RT, SUPERIO_GPIO_IO_BASE); + value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); + value &= 0xbf; + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); +} + +static void chipset_init(void) +{ + superio_init(); + + __asm__ __volatile__("\ + jmp skip\n\ + .align 128\n\ + .globl ck804_romstrap\n\ + ck804_romstrap:\n\ + .long 0x2b16d065\n\ + .long 0x0\n\ + .long 0x0\n\ + .long linkedlist\n\ + linkedlist:\n\ + .long 0x0003001C // 10h\n\ + .long 0x08000000 // 14h\n\ + .long 0x00000000 // 18h\n\ + .long 0xFFFFFFFF // 1Ch\n\ + .long 0xFFFFFFFF // 20h\n\ + .long 0xFFFFFFFF // 24h\n\ + .long 0xFFFFFFFF // 28h\n\ + .long 0xFFFFFFFF // 2Ch\n\ + .long 0x81543266 // 30h, MAC address low 4 byte\n\ + .long 0x000000E0 // 34h, MAC address high 4 byte\n\ + .long 0x002309CE // 38h, UUID low 4 byte\n\ + .long 0x00E08100 // 3Ch, UUID high 4 byte\n\ + skip:\n"); +}
Added: trunk/SerialICE/mainboard/tyan_s2895.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/SerialICE/mainboard/tyan_s2895.c Fri Jul 2 16:43:27 2010 (r101) @@ -0,0 +1,104 @@ +/* + * SerialICE + * + * Copyright (C) 2009 Uwe Hermann uwe@hermann-uwe.de + * Copyright (C) 2010 Arne Georg Gleditsch arne.gleditsch@numascale.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="Tyan S2895 "; + +#define SUPERIO_CONFIG_PORT 0x2e +#define SUPERIO_GPIO_IO_BASE 0x400 + +#define LPC47B397_SP1 4 /* Com1 */ +#define LPC47B397_RT 10 /* Runtime reg */ + +static void lpc47b397_gpio_offset_out(unsigned iobase, unsigned offset, unsigned value) +{ + outb(value,iobase+offset); +} + +static unsigned lpc47b397_gpio_offset_in(unsigned iobase, unsigned offset) +{ + return inb(iobase+offset); +} + + +/* Functions for the SMSC LPC47B272 & B397 */ +static void smsc_enable_serial(u16 port, u8 dev, unsigned iobase) +{ + pnp_enter_ext_func_mode_alt(port); + pnp_set_logical_device(port, dev); + pnp_set_enable(port, 0); + pnp_set_iobase0(port, iobase); + pnp_set_enable(port, 1); + pnp_exit_ext_func_mode(port); +} + +static void superio_init(void) +{ + unsigned value; + u32 dword; + u8 byte; + + pci_write_config32(PCI_ADDR(0, 1, 0, 0xac), 0x047f0400); + + byte = pci_read_config8(PCI_ADDR(0, 1 , 0, 0x7b)); + byte |= 0x20; + pci_write_config8(PCI_ADDR(0, 1 , 0, 0x7b), byte); + + dword = pci_read_config32(PCI_ADDR(0, 1 , 0, 0xa0)); + dword |= (1<<29)|(1<<0); + pci_write_config32(PCI_ADDR(0, 1 , 0, 0xa0), dword); + + dword = pci_read_config32(PCI_ADDR(0, 1, 0, 0xa4)); + dword |= (1<<16); + pci_write_config32(PCI_ADDR(0, 1, 0, 0xa4), dword); + + smsc_enable_serial(SUPERIO_CONFIG_PORT, LPC47B397_RT, SUPERIO_GPIO_IO_BASE); + value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); + value &= 0xbf; + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); +} + +static void chipset_init(void) +{ + superio_init(); + + __asm__ __volatile__("\ + jmp skip\n\ + .align 128\n\ + .globl ck804_romstrap\n\ + ck804_romstrap:\n\ + .long 0x2b16d065\n\ + .long 0x0\n\ + .long 0x0\n\ + .long linkedlist\n\ + linkedlist:\n\ + .long 0x0003001C // 10h\n\ + .long 0x08000000 // 14h\n\ + .long 0x00000000 // 18h\n\ + .long 0xFFFFFFFF // 1Ch\n\ + .long 0xFFFFFFFF // 20h\n\ + .long 0xFFFFFFFF // 24h\n\ + .long 0xFFFFFFFF // 28h\n\ + .long 0xFFFFFFFF // 2Ch\n\ + .long 0x81543266 // 30h, MAC address low 4 byte\n\ + .long 0x000000E0 // 34h, MAC address high 4 byte\n\ + .long 0x002309CE // 38h, UUID low 4 byte\n\ + .long 0x00E08100 // 3Ch, UUID high 4 byte\n\ + skip:\n"); +}
Modified: trunk/SerialICE/start.S ============================================================================== --- trunk/SerialICE/start.S Fri Jul 2 16:42:04 2010 (r100) +++ trunk/SerialICE/start.S Fri Jul 2 16:43:27 2010 (r101) @@ -124,6 +124,15 @@ .long via_romstrap #endif
+#ifdef CONFIG_CK804_ROMSTRAP +/* Pointers to nvidia tables at 0xffffe0 */ + . = 0x10; + .long ck804_romstrap + .long ck804_romstrap + .long ck804_romstrap + .long ck804_romstrap +#endif + #ifdef CONFIG_MCP55_ROMSTRAP /* Pointers to nvidia tables at 0xffffe0 */ . = 0x10;
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