Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3795
-gerrit
commit 723c37cc31ab0f81c12f93f44183ae2d2ae66f17 Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Mon Jul 22 02:27:53 2013 -0500
EPIA-M850: Add hook for PCI MMIO accesses
Add a hook that enables decoding of PCI MMIO base on the VIA VX900.
Change-Id: I5a66366fc4dbaf4e2f60f58febad90f7bb7cd2ff Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- SerialICE/simba/chipset/via_bars.lua | 22 ++++++++++++++++++++++ SerialICE/simba/mainboard/via_epia_m_850.lua | 1 + 2 files changed, 23 insertions(+)
diff --git a/SerialICE/simba/chipset/via_bars.lua b/SerialICE/simba/chipset/via_bars.lua index 7868535..1dca148 100644 --- a/SerialICE/simba/chipset/via_bars.lua +++ b/SerialICE/simba/chipset/via_bars.lua @@ -28,3 +28,25 @@ function northbridge_vx900() pci_cfg16_hook(dev_sb, 0xbd, "SB_PCI", sb_pcie_bar) pci_cfg32_hook(dev_nb, 0x0, "NB_PCI", nb_pcie_bar) end + +dev_nb_traf_ctl = { + pci_dev = pci_bdf(0,0,5,0), + name = "trf", + bar = {}, +} + +function vx900_pcie_bar(f, action) + local baseaddr = bit32.lshift(action.data, 28) + local size = 256*1024*1024 + + -- enable is 0:00.5 [060] .10 + if baseaddr then + pcie_mm_enable(f.dev, f.reg, baseaddr, size) + else + pcie_mm_disable(f.dev, f.reg, baseaddr, size) + end +end + +function northbridge_vx900_traf() + pci_cfg8_hook(dev_nb_traf_ctl, 0x61, "PCI", vx900_pcie_bar) +end diff --git a/SerialICE/simba/mainboard/via_epia_m_850.lua b/SerialICE/simba/mainboard/via_epia_m_850.lua index 44f0fde..f791e54 100644 --- a/SerialICE/simba/mainboard/via_epia_m_850.lua +++ b/SerialICE/simba/mainboard/via_epia_m_850.lua @@ -156,6 +156,7 @@ function do_mainboard_setup() enable_hook_superio(0x4e, 0x07)
northbridge_vx900() + northbridge_vx900_traf() pci_cfg16_hook(dev_power, 0x88, "PM", pm_io_bar) pci_cfg16_hook(dev_power, 0xd0, "SMBus", smbus_bar_hook)