rdmsr

[Nils]

Hi,
I am trying to port SerialICE to my Geode GX2 board and wanted to use rdmsr / 
wrmsr for serial init but they seem a little different to the Coreboot 
versions.
Am i right that the extra "key" value always has to be: 9c5a203a and acts as a 
extra safety measure ?

Thanks , Nils.

[Marc Jones]

Hi Nils,

On Sat, Apr 16, 2011 at 3:47 PM, Nils  wrote:
> Hi,
> I am trying to port SerialICE to my Geode GX2 board and wanted to use rdmsr /
> wrmsr for serial init but they seem a little different to the Coreboot
> versions.
> Am i right that the extra "key" value always has to be: 9c5a203a and acts as a
> extra safety measure ?

Sorry a month late on this, but from the datasheet, which is on the
AMD site somewhere...

4.5.2.83 MSR Lock Register
4.5.2.84 Real Time Stamp Counter Register
MSR Address 00001908

"Lock MSRs. The CPU CoreMSRs above 0xFFF (with the exception of the MSR_LOCK
register itself) are locked when this bit reads back as 1. To unlock
these MSRs, write the
value 45524F434C494156h to this register (the byte string “VAILCORE”).
Writing any
other value locks the MSRs.
The lock only affects software access via the WRMSR and RDMSR
instructions when the
processor is NOT in SMM or DMM mode. MSRs are always writable and readable from
the GLBus and when the processor is in SMM or DMM mode regardless of
the state of
the LOCK bit.
Note that a write or read to a locked MSR register causes  a
protection exception in the
pipeline.
When MSRs are locked, no GLBus MSR transactions are generated (GLBus MSR
addresses are above 0x3FFF)."

Marc

[nils]

You wrote:
> 4.5.2.83 MSR Lock Register
> 4.5.2.84 Real Time Stamp Counter Register
> MSR Address 00001908
>
> "Lock MSRs. The CPU CoreMSRs above 0xFFF (with the exception of the MSR_LOCK
> register itself) are locked when this bit reads back as 1. To unlock
> these MSRs, write the
> value 45524F434C494156h to this register (the byte string “VAILCORE”).
> Writing any

....

Thanks for the excellent explanation!

Nils.