[SerialICE] New patch to review for serialice: 9536981 Add hooking mechanism to provide for special parsers

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/462

-gerrit

commit 953698142a9a0ac17af089b89d82b03cac409262
Author: Patrick Georgi 
Date:   Thu Dec 1 13:03:30 2011 +0100

Add hooking mechanism to provide for special parsers

Right now the code hardcodes a lot of special handling.
    The idea is to move these into functions that are run until
    one is successful, or use a standard routine if none claimed
    responsibility.

Later-on, these handlers could be chipset specific and enabled
    automatically to provide a better view of what's going on.

Change-Id: I10cf9debd718cf5f60a652d071dcb9356ac79a03
    Signed-off-by: Patrick Georgi 
---
 SerialICE/scripts/serialice.lua |   60 +++++++++++++++++++++++++++++++++++++-
 1 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/SerialICE/scripts/serialice.lua b/SerialICE/scripts/serialice.lua
index ef77488..535cb0b 100644
--- a/SerialICE/scripts/serialice.lua
+++ b/SerialICE/scripts/serialice.lua
@@ -50,6 +50,58 @@ function size_data(size, data)
    end
 end

+function new_list()
+	return { list = nil }
+end
+
+function prepend_to_list(list, value)
+	list.list = { next = list.list, value = value }
+end
+
+function walk_list(list, ...)
+	if list == nil or list.list == nil then
+		return false
+	end
+	local l = list.list
+	while l do
+		if l.value(...) then
+			return true
+		end
+		l = l.next
+	end
+	return false
+end
+
+msr_write_hooks = new_list()
+msr_read_hooks = new_list()
+
+-- handle MTRRs
+prepend_to_list(msr_write_hooks,
+function(addr, hi, lo, filtered)
+	if addr >= 0x200 and addr < 0x210 then
+		if addr % 2 == 0 then
+			mt = lo % 0x100
+			if     mt == 0 then memtype = "Uncacheable"
+			elseif mt == 1 then memtype = "Write-Combine"
+			elseif mt == 4 then memtype = "Write-Through"
+			elseif mt == 5 then memtype = "Write-Protect"
+			elseif mt == 6 then memtype = "Write-Back"
+			else memtype = "Unknown"
+			end
+			printf("CPU: Set MTRR %x base to %08x.%08x (%s)\n", (addr - 0x200) / 2, hi, bit.band(lo, 0xffffff00), memtype)
+		else
+			if bit.band(lo, 0x800) == 0x800 then
+				valid = "valid"
+			else
+				valid = "disabled"
+			end
+			printf("CPU: Set MTRR %x mask to %08x.%08x (%s)\n", (addr - 0x200) / 2, hi, bit.band(lo, 0xfffff000), valid)
+		end
+		return true
+	end
+	return false
+end)
+
 -- In the beginning, during RAM initialization, it is essential that 
 -- all DRAM accesses are handled by the target, or RAM will not work
 -- correctly. After RAM initialization, RAM access has no "special"
@@ -606,12 +658,16 @@ end

function SerialICE_msr_write_log(addr, hi, lo, filtered)
    log_cs_ip()
-	printf("CPU: wrmsr %08x <= %08x.%08x\n", addr, hi, lo)
+	if not walk_list(msr_write_hooks, addr, hi, lo, filtered) then
+		printf("CPU: wrmsr %08x <= %08x.%08x\n", addr, hi, lo)
+	end
 end

function SerialICE_msr_read_log(addr, hi, lo, filtered)
    log_cs_ip()
-	printf("CPU: rdmsr %08x => %08x.%08x\n", addr, hi, lo)
+	if not walk_list(msr_write_hooks, addr, hi, lo, filtered) then
+		printf("CPU: rdmsr %08x => %08x.%08x\n", addr, hi, lo)
+	end
 end

function SerialICE_cpuid_log(in_eax, in_ecx, out_eax, out_ebx, out_ecx, out_edx, filtered)