On Tue, Mar 29, 2011 at 7:52 AM, Joseph Smith joe@settoplinux.org wrote:
On Tue, 29 Mar 2011 12:38:49 +0200, Idwer Vollering vidwer@gmail.com wrote:
2011/3/29 Joseph Smith joe@settoplinux.org:
On Tue, 29 Mar 2011 05:03:21 -0400, Corey Osgood
wrote:
On Tue, Mar 29, 2011 at 4:34 AM, Joseph Smith joe@settoplinux.org
wrote:
On Mon, 28 Mar 2011 22:51:23 -0600, Myles Watson mylesgw@gmail.com
wrote:
> Any other suggestions?
Have you tried different host frequencies until you don't see
garbage?
If you know the default value, you could try it first.
Sorry for the ignorance but what do you mean by host frequencies?
Baudrate?
-- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org
Maybe this will help. Attached is my patch for the Zotac NM10, the NM10 is virtually identical to ICH7, and NCT5571D is very similar to Winbond ICs (Nuvoton is a branch of Winbond, the datasheet's title is actually "W83627DHG Data Sheet", someone apparently forgot to change it).
Thanks Corey, I noticed you setup SIO PM Events on the southbridge and ACPI on
SuperIO.
Did you have to do that to get serial working? Besides that yours looks pretty much the same as mine.
Yes, and no. The ICH7 has a watchdog timer that will reboot the system after a short time without the timer being constantly reset, the PMBASE is set up so that can be disabled by the IO calls to (TCOBASE + n). Looking at the datasheet, it also looks like ICH4 has the same thing, but you're not seeing the system go into a reboot loop? Section 9.9.7 is the register. As for why ACPI was set up in the Super I/O, I have no clue, it's been a few months since I wrote that, and I can't see any glaring reason in the datasheet to have done it.
You aren't setting up SERIRQ_CNTL (and CNF[1,2]_LPC_EN, COM[A,B]_LPC_EN). Is that on purpose ?
Just to clarify my setup does Coreys does not. It is not always needed, my other ICH4 boards supported by serialice do not need any southbridge registers setup (except to disable the watchdog timer). Works out of the box so to speak.
No, those are registers 0x64 (SERIRQ_CNTL), 0x80 (LPC_I/O_DEC, controls COMA/COMB_LPC_EN), and 0x82 (LPC_EN, controls CNF1/2_LPC_EN) on ICH7/NM10, my code does set those up. Yours doesn't set up SERIRQ_CNTL (0x64), but does the other two. IMO, also use 0x1003 for 0xE6, anything else should be enabled by the BIOS later.
Hope this helps! -Corey