SerialICE February 2014

serialice@serialice.com

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New patch to review for serialice: 9a6c106 mainboard/jetway_nf81_t56n_lf: Add initial support.
by Edward O'Callaghan 13 Feb '14

13 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5214 -gerrit commit 9a6c1062f0dd5bc3d42cce5ed6f81121125f171a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Feb 14 01:03:34 2014 +1100 mainboard/jetway_nf81_t56n_lf: Add initial support. Add support for Jetway NF81-T56N-LF mainboard and its Super I/O. Change-Id: Idef372f1f2654a93dbd1023101fd0bb15fef32f8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- SerialICE/Kconfig | 7 ++++++ SerialICE/mainboard/jetway_nf81_t56n_lf.c | 27 ++++++++++++++++++++ SerialICE/superio/fintek-f71869ad.c | 41 +++++++++++++++++++++++++++++++ 3 files changed, 75 insertions(+) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 00933b2..61b6c50 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -130,6 +130,10 @@ config BOARD_ASROCK_775I65G config BOARD_COMMELL_LV_672 bool "Commell LV-672" +config BOARD_JETWAY_NF81_T56N_LF + bool "Jetway NF81-T56N-LF" + select BUILD_XMMSTACK + endchoice config BOARD_INIT @@ -163,15 +167,18 @@ config BOARD_INIT default "intel_d845gbv2.c" if BOARD_INTEL_D845GBV2 default "asrock_775i65g.c" if BOARD_ASROCK_775I65G default "commell_lv_672.c" if BOARD_COMMELL_LV_672 + default "jetway_nf81_t56n_lf.c" if BOARD_JETWAY_NF81_T56N_LF config SOUTHBRIDGE_INIT string default "southbridge/intel-ich7.c" if BOARD_KONTRON_986LCD_M default "southbridge/amd-sbxxx.c" if BOARD_ASUS_F2A85_M + default "southbridge/amd-sbxxx.c" if BOARD_JETWAY_NF81_T56N_LF config SUPERIO_INIT string default "superio/winbond-w83627thg.c" if BOARD_KONTRON_986LCD_M + default "superio/fintek-f71869ad.c" if BOARD_JETWAY_NF81_T56N_LF choice prompt "ROM size" diff --git a/SerialICE/mainboard/jetway_nf81_t56n_lf.c b/SerialICE/mainboard/jetway_nf81_t56n_lf.c new file mode 100644 index 0000000..590df8f --- /dev/null +++ b/SerialICE/mainboard/jetway_nf81_t56n_lf.c @@ -0,0 +1,27 @@ +/* + * SerialICE + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="Jetway NF81-T56N-LF "; + +static void chipset_init(void) +{ + southbridge_init(); + sbxxx_enable_48mhzout(); + superio_init(); +} diff --git a/SerialICE/superio/fintek-f71869ad.c b/SerialICE/superio/fintek-f71869ad.c new file mode 100644 index 0000000..77d5023 --- /dev/null +++ b/SerialICE/superio/fintek-f71869ad.c @@ -0,0 +1,41 @@ +/* + * SerialICE + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define SUPERIO_CONFIG_PORT 0x2e +#define SUPERIO_IO_PORT 0x3F8 +#define SUPERIO_IRQ_ADDR 4 + +static void superio_init(void) +{ + u8 byte; + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + + /* Disable the watchdog. */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); + pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + + /* Enable the serial port. */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT, SUPERIO_IO_PORT); + pnp_set_irq0(SUPERIO_CONFIG_PORT, SUPERIO_IRQ_ADDR); + pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + + pnp_exit_ext_func_mode_ite(SUPERIO_CONFIG_PORT); +}

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New patch to review for serialice: 7079bf3 southbridge/amd-sbxxx.c: Init clock to 48 MHz on AMD SB800
by Paul Menzel 13 Feb '14

13 Feb '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5213 -gerrit commit 7079bf382ee6e63a1adee9f8d038be21bfbcd904 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Jul 15 13:31:51 2013 +0200 southbridge/amd-sbxxx.c: Init clock to 48 MHz on AMD SB800 Copy the init from coreboot’s `src/southbridge/amd/cimx/sb800/bootblock.c`. Daniel Gröber showed my error in forgetting to actually enable the clock of 48 MHz so it did not work for me with 14 MHz. The Super I/O SMSC SCH311x needs 14 MHz so the Kconfig option is ported over. Change-Id: I9146d2c0620c2bb338130f55ead0704fa82075c7 Signed-off-by: Daniel Gröber <dxld(a)darkboxed.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- SerialICE/southbridge/amd-sbxxx.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/SerialICE/southbridge/amd-sbxxx.c b/SerialICE/southbridge/amd-sbxxx.c index 37dca92..99a7240 100644 --- a/SerialICE/southbridge/amd-sbxxx.c +++ b/SerialICE/southbridge/amd-sbxxx.c @@ -30,24 +30,28 @@ #define SB_MMIO 0xFED80000 #define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) + static void sbxxx_enable_48mhzout(void) { - /* most likely programming to 48MHz out signal */ u32 reg32; - reg32 = SB_MMIO_MISC32(0x28); - reg32 &= 0xffc7ffff; - reg32 |= 0x00100000; - SB_MMIO_MISC32(0x28) = reg32; + // Program SB800 MiscClkCntrl register to configure clock output on the + // 14M_25M_48M_OSC ball usually used for the Super-I/O. + // Almost all SIOs need 48 MHz, only the SMSC SCH311x wants 14 MHz, + // which is the SB800's power up default. We could switch back to 14 + // in the mainboard's romstage.c, but then the clock frequency would + // change twice. reg32 = SB_MMIO_MISC32(0x40); - reg32 &= ~0x80u; + reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default) +#if !CONFIG_SUPERIO_WANTS_14MHZ_CLOCK + reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz +#endif SB_MMIO_MISC32(0x40) = reg32; } static void southbridge_init(void) { u8 reg8; - u32 reg32; /* route FED00000 - FEDFFFFF as non-posted to SB */ pci_write_config32(PCI_ADDR(0, 0x18, 1, 0x84), @@ -60,6 +64,13 @@ static void southbridge_init(void) pci_write_config32(PCI_ADDR(0, 0x18, 1, 0xc4), 0x0000f000); pci_write_config32(PCI_ADDR(0, 0x18, 1, 0xc0), 0x00000003); + // Program AcpiMmioEn to enable MMIO access to MiscCntrl register + outb(0x24, 0xcd6); + reg8 = inb(0xcd7); + reg8 |= 1; + reg8 &= ~(1 << 1); + outb(reg8, 0xcd7); + /* SB MMIO range decode enable */ outb(0x24, 0xcd6); outb(0x1, 0xcd7);

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Patch set updated for serialice: 2ea1c5b Add support for ASRock E350M1
by Paul Menzel 13 Feb '14

13 Feb '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3510 -gerrit commit 2ea1c5b433eb09b0264605d486bbd18aadc56916 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Jun 21 10:17:46 2013 +0200 Add support for ASRock E350M1 The ASRock E350M1 uses the southbridge AMD SB800 and the Super I/O Nuvoton NCT5572D similar to the Winbond W83627HF so use that one as done in coreboot too. Change-Id: I0a1eea0cf01d36682b737e0161eb2dfbc05f8d21 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- SerialICE/Kconfig | 7 +++++++ SerialICE/mainboard/asrock_e350m1.c | 28 ++++++++++++++++++++++++++++ SerialICE/southbridge/amd-sbxxx.c | 5 +++++ 3 files changed, 40 insertions(+) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 00933b2..a8313fb 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -69,6 +69,10 @@ config BOARD_ASUS_M4A77TD_PRO bool "ASUS M4A77TD-PRO" select BUILD_XMMSTACK +config BOARD_ASROCK_E350M1 + bool "ASRock E350M1" + select BUILD_XMMSTACK + config BOARD_ASROCK_939A785GMH bool "ASRock 939A785GMH" select BUILD_XMMSTACK @@ -163,14 +167,17 @@ config BOARD_INIT default "intel_d845gbv2.c" if BOARD_INTEL_D845GBV2 default "asrock_775i65g.c" if BOARD_ASROCK_775I65G default "commell_lv_672.c" if BOARD_COMMELL_LV_672 + default "asrock_e350m1.c" if BOARD_ASROCK_E350M1 config SOUTHBRIDGE_INIT string default "southbridge/intel-ich7.c" if BOARD_KONTRON_986LCD_M + default "southbridge/amd-sbxxx.c" if BOARD_ASROCK_E350M1 default "southbridge/amd-sbxxx.c" if BOARD_ASUS_F2A85_M config SUPERIO_INIT string + default "superio/winbond-w83627thg.c" if BOARD_ASROCK_E350M1 default "superio/winbond-w83627thg.c" if BOARD_KONTRON_986LCD_M choice diff --git a/SerialICE/mainboard/asrock_e350m1.c b/SerialICE/mainboard/asrock_e350m1.c new file mode 100644 index 0000000..07f82af --- /dev/null +++ b/SerialICE/mainboard/asrock_e350m1.c @@ -0,0 +1,28 @@ +/* + * SerialICE + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2013 Paul Menzel <paulepanter(a)users.sourceforge.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="ASRock E350M1 "; + +static void chipset_init(void) +{ + southbridge_init(); + sbxxx_enable_48mhzout(); + superio_init(); +} diff --git a/SerialICE/southbridge/amd-sbxxx.c b/SerialICE/southbridge/amd-sbxxx.c index 99a7240..bec202c 100644 --- a/SerialICE/southbridge/amd-sbxxx.c +++ b/SerialICE/southbridge/amd-sbxxx.c @@ -35,6 +35,11 @@ static void sbxxx_enable_48mhzout(void) { u32 reg32; + reg32 = SB_MMIO_MISC32(0x24); + reg32 &= 0xffc7ffff; + reg32 |= 0x00100000; + SB_MMIO_MISC32(0x24) = reg32; + // Program SB800 MiscClkCntrl register to configure clock output on the // 14M_25M_48M_OSC ball usually used for the Super-I/O. // Almost all SIOs need 48 MHz, only the SMSC SCH311x wants 14 MHz,

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SerialICE February 2014