SerialICE July 2013

serialice@serialice.com

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23 discussions

New patch to review for serialice: a182ef2 EPIA-M850: Add hook for PCI MMIO accesses
by Alexandru Gagniuc 22 Jul '13

22 Jul '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3795 -gerrit commit a182ef21985547a8865cc28b1661b207443c15c1 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Jul 22 02:27:53 2013 -0500 EPIA-M850: Add hook for PCI MMIO accesses Add a hook that enables decoding of PCI MMIO base on the VIA VX900. Change-Id: I5a66366fc4dbaf4e2f60f58febad90f7bb7cd2ff Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- SerialICE/simba/chipset/via_bars.lua | 22 ++++++++++++++++++++++ SerialICE/simba/mainboard/via_epia_m_850.lua | 2 ++ 2 files changed, 24 insertions(+) diff --git a/SerialICE/simba/chipset/via_bars.lua b/SerialICE/simba/chipset/via_bars.lua index 7868535..f9916d7 100644 --- a/SerialICE/simba/chipset/via_bars.lua +++ b/SerialICE/simba/chipset/via_bars.lua @@ -28,3 +28,25 @@ function northbridge_vx900() pci_cfg16_hook(dev_sb, 0xbd, "SB_PCI", sb_pcie_bar) pci_cfg32_hook(dev_nb, 0x0, "NB_PCI", nb_pcie_bar) end + +dev_nb_traf_ctl = { + pci_dev = pci_bdf(0,0,5,0), + name = "trf", + bar = {}, +} + +function vx900_pcie_bar(f, action) + local baseaddr = bit32.lshift(action.data, 28) + local size = 256*1024*1024 + + -- enable is 0:00.0 [054] .31 + if baseaddr then + pcie_mm_enable(f.dev, f.reg, baseaddr, size) + else + pcie_mm_disable(f.dev, f.reg, baseaddr, size) + end +end + +function northbridge_vx900_traf() + pci_cfg8_hook(dev_nb_traf_ctl, 0x61, "PCI", vx900_pcie_bar) +end diff --git a/SerialICE/simba/mainboard/via_epia_m_850.lua b/SerialICE/simba/mainboard/via_epia_m_850.lua index 44f0fde..c18d870 100644 --- a/SerialICE/simba/mainboard/via_epia_m_850.lua +++ b/SerialICE/simba/mainboard/via_epia_m_850.lua @@ -141,6 +141,7 @@ end -- **************** function do_mainboard_setup() + print("Muhuhuhahahahaaa") enable_hook(io_hooks, filter_pci_io_cfg) enable_hook(mem_hooks, filter_lapic) enable_hook(mem_hooks, filter_ioapic) @@ -156,6 +157,7 @@ function do_mainboard_setup() enable_hook_superio(0x4e, 0x07) northbridge_vx900() + northbridge_vx900_traf() pci_cfg16_hook(dev_power, 0x88, "PM", pm_io_bar) pci_cfg16_hook(dev_power, 0xd0, "SMBus", smbus_bar_hook)

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New patch to review for serialice: af90943 Add support for ASRock E350M1
by Paul Menzel 13 Jul '13

13 Jul '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3510 -gerrit commit af90943213d8219bbd8cf0d649d573844ce974d1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Jun 21 10:17:46 2013 +0200 Add support for ASRock E350M1 Change-Id: I0a1eea0cf01d36682b737e0161eb2dfbc05f8d21 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- SerialICE/Kconfig | 6 +++++ SerialICE/mainboard/asrock_e350m1.c | 50 +++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 00933b2..16b5c6b 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -69,6 +69,10 @@ config BOARD_ASUS_M4A77TD_PRO bool "ASUS M4A77TD-PRO" select BUILD_XMMSTACK +config BOARD_ASROCK_E350M1 + bool "ASRock E350M1" + select BUILD_XMMSTACK + config BOARD_ASROCK_939A785GMH bool "ASRock 939A785GMH" select BUILD_XMMSTACK @@ -163,10 +167,12 @@ config BOARD_INIT default "intel_d845gbv2.c" if BOARD_INTEL_D845GBV2 default "asrock_775i65g.c" if BOARD_ASROCK_775I65G default "commell_lv_672.c" if BOARD_COMMELL_LV_672 + default "asrock_e350m1.c" if BOARD_ASROCK_E350M1 config SOUTHBRIDGE_INIT string default "southbridge/intel-ich7.c" if BOARD_KONTRON_986LCD_M + default "southbridge/amd-sbxxx.c" if BOARD_ASROCK_E350M1 default "southbridge/amd-sbxxx.c" if BOARD_ASUS_F2A85_M config SUPERIO_INIT diff --git a/SerialICE/mainboard/asrock_e350m1.c b/SerialICE/mainboard/asrock_e350m1.c new file mode 100644 index 0000000..d3b9087 --- /dev/null +++ b/SerialICE/mainboard/asrock_e350m1.c @@ -0,0 +1,50 @@ +/* + * SerialICE + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2013 Paul Menzel <paulepanter(a)users.sourceforge.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="ASRock E350M1 "; + +#define SUPERIO_CONFIG_PORT 0x2e + +static void superio_init(void) +{ + u8 byte; + pnp_enter_ext_func_mode_ite(SUPERIO_CONFIG_PORT); + + /* Disable the watchdog. */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 7); + pnp_write_register(SUPERIO_CONFIG_PORT, 0x72, 0x00); + + /* Enable the serial port. */ + pnp_set_logical_device(SUPERIO_CONFIG_PORT, 1); /* COM1 */ + pnp_set_enable(SUPERIO_CONFIG_PORT, 0); + pnp_set_iobase0(SUPERIO_CONFIG_PORT, 0x3f8); + pnp_set_irq0(SUPERIO_CONFIG_PORT, 4); + pnp_set_enable(SUPERIO_CONFIG_PORT, 1); + + pnp_exit_ext_func_mode(SUPERIO_CONFIG_PORT); +} + + +static void chipset_init(void) +{ + southbridge_init(); + sbxxx_enable_48mhzout(); + superio_init(); +}

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Patch set updated for serialice: ceaeb7b Add support for ASRock E350M1
by Paul Menzel 13 Jul '13

13 Jul '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3510 -gerrit commit ceaeb7b92fbe4046fb54c537631bebb174c380e6 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Jun 21 10:17:46 2013 +0200 Add support for ASRock E350M1 The ASRock E350M1 uses the southbridge AMD SB800 and therefore uses the function `southbridge_init()` from `southbridge/amd-sbxxx.c`. This also features the function to set the clock output to 48 MHz. Unfortunately it looks like that the port(?) differs from the SB900/Hudson(?) chipset. 0x24 seems to be used on the SB800 where it is 0x28 for the SB900/Hudson. Change-Id: I0a1eea0cf01d36682b737e0161eb2dfbc05f8d21 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- SerialICE/Kconfig | 7 +++++++ SerialICE/mainboard/asrock_e350m1.c | 28 ++++++++++++++++++++++++++++ SerialICE/southbridge/amd-sbxxx.c | 4 ++-- 3 files changed, 37 insertions(+), 2 deletions(-) diff --git a/SerialICE/Kconfig b/SerialICE/Kconfig index 00933b2..a8313fb 100644 --- a/SerialICE/Kconfig +++ b/SerialICE/Kconfig @@ -69,6 +69,10 @@ config BOARD_ASUS_M4A77TD_PRO bool "ASUS M4A77TD-PRO" select BUILD_XMMSTACK +config BOARD_ASROCK_E350M1 + bool "ASRock E350M1" + select BUILD_XMMSTACK + config BOARD_ASROCK_939A785GMH bool "ASRock 939A785GMH" select BUILD_XMMSTACK @@ -163,14 +167,17 @@ config BOARD_INIT default "intel_d845gbv2.c" if BOARD_INTEL_D845GBV2 default "asrock_775i65g.c" if BOARD_ASROCK_775I65G default "commell_lv_672.c" if BOARD_COMMELL_LV_672 + default "asrock_e350m1.c" if BOARD_ASROCK_E350M1 config SOUTHBRIDGE_INIT string default "southbridge/intel-ich7.c" if BOARD_KONTRON_986LCD_M + default "southbridge/amd-sbxxx.c" if BOARD_ASROCK_E350M1 default "southbridge/amd-sbxxx.c" if BOARD_ASUS_F2A85_M config SUPERIO_INIT string + default "superio/winbond-w83627thg.c" if BOARD_ASROCK_E350M1 default "superio/winbond-w83627thg.c" if BOARD_KONTRON_986LCD_M choice diff --git a/SerialICE/mainboard/asrock_e350m1.c b/SerialICE/mainboard/asrock_e350m1.c new file mode 100644 index 0000000..07f82af --- /dev/null +++ b/SerialICE/mainboard/asrock_e350m1.c @@ -0,0 +1,28 @@ +/* + * SerialICE + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2013 Paul Menzel <paulepanter(a)users.sourceforge.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +const char boardname[33]="ASRock E350M1 "; + +static void chipset_init(void) +{ + southbridge_init(); + sbxxx_enable_48mhzout(); + superio_init(); +} diff --git a/SerialICE/southbridge/amd-sbxxx.c b/SerialICE/southbridge/amd-sbxxx.c index 37dca92..36664ba 100644 --- a/SerialICE/southbridge/amd-sbxxx.c +++ b/SerialICE/southbridge/amd-sbxxx.c @@ -34,10 +34,10 @@ static void sbxxx_enable_48mhzout(void) { /* most likely programming to 48MHz out signal */ u32 reg32; - reg32 = SB_MMIO_MISC32(0x28); + reg32 = SB_MMIO_MISC32(0x24); reg32 &= 0xffc7ffff; reg32 |= 0x00100000; - SB_MMIO_MISC32(0x28) = reg32; + SB_MMIO_MISC32(0x24) = reg32; reg32 = SB_MMIO_MISC32(0x40); reg32 &= ~0x80u;

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SerialICE July 2013