Author: pgf
Date: Tue Aug 14 20:48:26 2012
New Revision: 3167
URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3167
Log:
bsl: add TODO list
just some reminders of what could/should be done here.
Modified:
cpu/arm/olpc/bsl.fth
Modified: cpu/arm/olpc/bsl.fth
==============================================================================
--- cpu/arm/olpc/bsl.fth Tue Aug 14 01:19:12 2012 (r3166)
+++ cpu/arm/olpc/bsl.fth Tue Aug 14 20:48:26 2012 (r3167)
@@ -1,6 +1,15 @@
\ See license at end of file
purpose: Downloader for TI MSP430 BootStrap Loader (BSL) protocol
+
+\ TODO:
+\ friendlier programming interface ( "ok flash-bsl u:\file.hex")
+\ progress indicator during programming
+\ print, perhaps in red, the msp430 password after programming,
+\ iff the password doesn't match all-ff or the known neonode password.
+\ save calibration data in mfg tag, in case it's lost.
+\ create msp430 recalibrator programmer
+
\ devalias bsl /uart@NNNN:9600,8,e,1//bsl-protocol
\ the MSP430 BSL has the annoying trait that it will self-erase if
Author: rsmith
Date: Tue Aug 14 01:19:12 2012
New Revision: 3166
URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3166
Log:
OLPC 1.75 - Fix EC programming breakage
The changes to support the io3790 on the CL4 broke programming on the
1.75. This fixes up the breakage.
It also factors out the dummy read into its own word called edi-start.
Not necessary for the fix but was handy during debugging.
Modified:
cpu/arm/olpc/edi.fth
Modified: cpu/arm/olpc/edi.fth
==============================================================================
--- cpu/arm/olpc/edi.fth Mon Aug 13 23:21:51 2012 (r3165)
+++ cpu/arm/olpc/edi.fth Tue Aug 14 01:19:12 2012 (r3166)
@@ -18,10 +18,10 @@
: efcfg ( -- reg# ) kb9010? if h# fead else h# fea0 then ;
: efcmd ( -- reg# ) kb9010? if h# feac else h# fea7 then ;
-: efdat ( -- reg# ) kb9010? if h# feab else h# feaa then ;
+: efdat ( -- reg# ) kb9010? if h# feab else h# feaa then ; \ io3731 has different read and write regs
+h# feab constant efdat-in
: rst8051 ( -- reg# ) kb9010? if h# ff14 else h# f010 then ;
: ecreboot ( -- reg# ) kb9010? if h# ff01 else h# f018 then ;
-
\ Issues with .py code
\ A14:A8 should be A15:A8 several places
\ inconsistent use of handle vs gd.handle in edi_erase_chip
@@ -140,7 +140,7 @@
;
: finished? ( b -- flag )
- kb9010? if 2 and 0= else h# 80 = then
+ kb9010? if 2 and 0= else h# 80 and h# 80 = then
;
: wait-flash-busy ( -- ) \ Wait for an erase/programming operation to complete
get-msecs h# 1000 + ( limit )
@@ -220,8 +220,9 @@
set-offset
h# 90 flash-cmd
wait-flash-busy
- efdat edi-b@ \ reg: efdat
+ efdat-in edi-b@ \ reg: efdat
;
+
: trim-tune ( -- )
\ firmware-id 0= if
\ Read trim data and write to register (for ENE macros)
@@ -334,13 +335,19 @@
ecsts edi-b! ( )
then
;
+
+\ Does a dummy ready and throws away the result.
+\ required to get the EDI interface enabled
+: edi-start ( -- )
+ h# ff22 ['] edi-b@ catch if noop else drop then
+;
+
: edi-open ( -- )
\ slow-edi-clock \ Target speed between 1 and 2 MHz
spi-start
- \ dummy read, to activate EDI and can fail so ignore the fail
- h# ff22 ['] edi-b@ catch if noop else drop then
-
+ edi-start
+
set-chip-id
\ The first operation often fails so retry it
Author: rsmith
Date: Mon Aug 13 21:42:03 2012
New Revision: 3157
URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3157
Log:
OLPC CL4 - Fix EC flash fail after cold boot
After a cold boot the first attempt to flash the EC would fail with a
"EC byte in confused" then all attempts after that would fail with a
"Bad SPI FLASH ID 0" until you did a warm boot then they would
succeed.
The EDI interface requires a EDI transaction with a clock between 1
and 8 Mhz for it to enable. Empirically we see that the data you get
back from this 1st transaction are zeros and so the 1st read will
abort because zero is not a valid response an EDI transaction. The
previous did a catch and retry when it ran the select-flash operation
but with the introduction of the io3790 a chip ID check has to be run
first.
The ID command does not be sufficient to enable the EDI interface
(also found empirically) it appears to have to be a read.
So now when we do the dummy read we ignore it if it fails rather than
abort out.
This also fixed the "Bat SPI FLASH ID 0" problem so it would seem that
if edi-open takes an abort that things are not properly cleaned up or
correctly re-initialized on the next attempt. I didn't debug the problem any
further.
Modified:
cpu/arm/olpc/edi.fth
Modified: cpu/arm/olpc/edi.fth
==============================================================================
--- cpu/arm/olpc/edi.fth Mon Aug 13 09:10:50 2012 (r3156)
+++ cpu/arm/olpc/edi.fth Mon Aug 13 21:42:03 2012 (r3157)
@@ -72,7 +72,9 @@
unloop exit
then ( d )
spi-cs-off ( d )
- h# ff = abort" EDI byte in inactive"
+ \ The setup in the CL4 has can also report zeros when inactive.
+ 2dup h# ff = 00 = or abort" EDI byte in inactive"
+ ." Unknown EDI byte in response: " .h cr
true abort" EDI byte in confused"
then ( d )
drop
@@ -336,8 +338,8 @@
\ slow-edi-clock \ Target speed between 1 and 2 MHz
spi-start
- \ dummy read, to activate EDI
- h# ff22 edi-b@ drop
+ \ dummy read, to activate EDI and can fail so ignore the fail
+ h# ff22 ['] edi-b@ catch if noop else drop then
set-chip-id