Author: rsmith Date: Mon Aug 13 21:42:03 2012 New Revision: 3157 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3157
Log: OLPC CL4 - Fix EC flash fail after cold boot
After a cold boot the first attempt to flash the EC would fail with a "EC byte in confused" then all attempts after that would fail with a "Bad SPI FLASH ID 0" until you did a warm boot then they would succeed.
The EDI interface requires a EDI transaction with a clock between 1 and 8 Mhz for it to enable. Empirically we see that the data you get back from this 1st transaction are zeros and so the 1st read will abort because zero is not a valid response an EDI transaction. The previous did a catch and retry when it ran the select-flash operation but with the introduction of the io3790 a chip ID check has to be run first. The ID command does not be sufficient to enable the EDI interface (also found empirically) it appears to have to be a read.
So now when we do the dummy read we ignore it if it fails rather than abort out.
This also fixed the "Bat SPI FLASH ID 0" problem so it would seem that if edi-open takes an abort that things are not properly cleaned up or correctly re-initialized on the next attempt. I didn't debug the problem any further.
Modified: cpu/arm/olpc/edi.fth ============================================================================== --- cpu/arm/olpc/edi.fth Mon Aug 13 09:10:50 2012 (r3156) +++ cpu/arm/olpc/edi.fth Mon Aug 13 21:42:03 2012 (r3157) @@ -72,7 +72,9 @@ unloop exit then ( d ) spi-cs-off ( d ) - h# ff = abort" EDI byte in inactive" + \ The setup in the CL4 has can also report zeros when inactive. + 2dup h# ff = 00 = or abort" EDI byte in inactive" + ." Unknown EDI byte in response: " .h cr true abort" EDI byte in confused" then ( d ) drop @@ -336,8 +338,8 @@ \ slow-edi-clock \ Target speed between 1 and 2 MHz spi-start
- \ dummy read, to activate EDI - h# ff22 edi-b@ drop + \ dummy read, to activate EDI and can fail so ignore the fail + h# ff22 ['] edi-b@ catch if noop else drop then