June 2009 - openfirmware - mail.coreboot.org

r1230 - cpu/x86/pc/olpc/via dev/olpc/dcon

by svn＠openfirmware.info

Author: wmb Date: 2009-06-30 21:53:14 +0200 (Tue, 30 Jun 2009) New Revision: 1230 Modified: cpu/x86/pc/olpc/via/acpi.fth cpu/x86/pc/olpc/via/addrs.fth cpu/x86/pc/olpc/via/dsdt.dsl cpu/x86/pc/olpc/via/fw.bth cpu/x86/pc/olpc/via/ioinit.fth cpu/x86/pc/olpc/via/rmstart.fth cpu/x86/pc/olpc/via/romreset.bth dev/olpc/dcon/viadcon.fth Log: Via - ACPI wakeup support. Modified: cpu/x86/pc/olpc/via/acpi.fth =================================================================== --- cpu/x86/pc/olpc/via/acpi.fth 2009-06-29 19:30:06 UTC (rev 1229) +++ cpu/x86/pc/olpc/via/acpi.fth 2009-06-30 19:53:14 UTC (rev 1230) @@ -232,6 +232,44 @@ dup >acpi-table-len 9 fix-checksum ; +h# 28 constant rm-ds \ Must agree with GDT in rmstart.fth + +label do-acpi-wake + \ This code must be copied to low memory + \ Jump to this code (in low memory) with the linear target address in EAX + \ Interrupts must be off. We don't have a stack. + \ We got here via a far jmp to a 16-bit code segment, so we are + \ using the 16-bit instruction set, but we're not yet in real mode + + 16-bit + + ahead + 0 w, 0 w, \ Room for the segment:offset pointer + then + + op: ax bx mov + h# 0f # ax and + op: 4 # bx shr + + cs: ax wake-adr la1+ #) mov \ Offset + cs: bx wake-adr wa1+ #) mov \ Segment + + \ The following might be unnecessary + ax ax xor rm-ds # al mov \ 16-bit data segment + ax ds mov ax es mov ax ss mov + + cr0 ax mov h# fe # al and ax cr0 mov \ Enter real mode + + here 5 + do-acpi-wake - wake-adr + >seg:off #) far jmp \ Jump to set cs + + \ The following might be unnecessary + \ Now we are running in real mode; fix segments again + cs ax mov ax ds mov ax es mov + + cs: wake-adr wa1+ s#) far jmp +end-code +here do-acpi-wake - constant /do-acpi-wake + : setup-acpi ( -- ) [ifdef] notdef \ This has to agree with the _SB's _INI method, which gets the memory size @@ -254,6 +292,8 @@ " dsdt" find-drop-in 0= abort" No DSDT " ( adr len ) 2dup dsdt-adr swap move free-mem + do-acpi-wake wake-adr 4 + /do-acpi-wake move + [ifdef] notdef \ Copy in the SSDT \ I suppose we could point to it in FLASH - if so don't compress it, Modified: cpu/x86/pc/olpc/via/addrs.fth =================================================================== --- cpu/x86/pc/olpc/via/addrs.fth 2009-06-29 19:30:06 UTC (rev 1229) +++ cpu/x86/pc/olpc/via/addrs.fth 2009-06-30 19:53:14 UTC (rev 1230) @@ -69,12 +69,13 @@ h# e0080 constant fadt-adr h# e0180 constant facs-adr h# e01c0 constant dbgp-adr -h# e0200 constant madt-adr \ MADT is 5a byts long +h# e0200 constant madt-adr \ MADT is 5a bytes long h# e0280 constant hpet-adr h# fc000 constant dsdt-adr h# fd000 constant ssdt-adr h# ffc00 constant smbios-adr +h# fff00 constant wake-adr h# 3e.0000 constant inflate-base h# 30.0000 constant workspace Modified: cpu/x86/pc/olpc/via/dsdt.dsl =================================================================== --- cpu/x86/pc/olpc/via/dsdt.dsl 2009-06-29 19:30:06 UTC (rev 1229) +++ cpu/x86/pc/olpc/via/dsdt.dsl 2009-06-30 19:53:14 UTC (rev 1230) @@ -22,6 +22,14 @@ { Processor(\_PR.CPU0,0x00,0x00000410,0x06) { + Name(_CST, Package() + { + 4, + Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x414)}, 2, 2, 750}, + Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x415)}, 3, 65, 500}, + Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x416)}, 4, 100, 300}, + Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x417)}, 5, 200, 200} + }) } } // System Sleep States Modified: cpu/x86/pc/olpc/via/fw.bth =================================================================== --- cpu/x86/pc/olpc/via/fw.bth 2009-06-29 19:30:06 UTC (rev 1229) +++ cpu/x86/pc/olpc/via/fw.bth 2009-06-30 19:53:14 UTC (rev 1230) @@ -344,12 +344,12 @@ boot-getline to boot-file " rom:emacs" $boot ; +fload ${BP}/cpu/x86/pc/rmtools.fth fload ${BP}/cpu/x86/pc/olpc/via/acpi.fth fload ${BP}/cpu/x86/pc/olpc/via/smbios.fth [ifdef] Later -fload ${BP}/cpu/x86/pc/rmtools.fth fload ${BP}/dev/geode/smi.fth \ fload ${BP}/cpu/x86/pc/biosload/rmenter.fth fload ${BP}/cpu/x86/pc/biosints.fth Modified: cpu/x86/pc/olpc/via/ioinit.fth =================================================================== --- cpu/x86/pc/olpc/via/ioinit.fth 2009-06-29 19:30:06 UTC (rev 1229) +++ cpu/x86/pc/olpc/via/ioinit.fth 2009-06-30 19:53:14 UTC (rev 1230) @@ -199,7 +199,8 @@ 82 0f 0a mreg \ Direct SCI to IRQ 10 (0xa) 84 ff da mreg \ IRQs 7,6,4,3,1 are primary wakeups 85 ff 40 mreg \ IRQ 14 is primary wakeup - 8a 9f 1f mreg \ C-state auto switching with normal latencies +\ 8a 9f 1f mreg \ C-state auto switching with normal latencies + 8a 9f 9f mreg \ C-state auto switching with slow C4 recovery mode - for C4 support [ifdef] demo-board 8d 18 18 mreg \ fast clock as throttle timer tick, hold SMI# low until event status cleared (FIXME for OLPC) [then] Modified: cpu/x86/pc/olpc/via/rmstart.fth =================================================================== --- cpu/x86/pc/olpc/via/rmstart.fth 2009-06-29 19:30:06 UTC (rev 1229) +++ cpu/x86/pc/olpc/via/rmstart.fth 2009-06-30 19:53:14 UTC (rev 1230) @@ -39,9 +39,8 @@ \ Addresses where the following items will be located in the processor's \ physical address space: -\ ffff.fc00: GDT ( 3 entries ) + padding -\ ffff.fc20: GDT address + size ( 6 bytes ) plus padding -\ ffff.fc28: Startup code plus padding +\ ffff.fc00: GDT ( 4 active entries ) + padding +\ ffff.fc30: Startup code plus padding \ ffff.fff0: Reset entry point - jump to startup code plus padding to end \ Assembler macros for startup diagnostics @@ -88,10 +87,12 @@ 0 w, 0 l, 0 w, \ * Null descriptor ffff w, 9b.000000 l, 00.c.f w, \ 10 Code, linear=physical, full 4Gbytes ffff w, 93.000000 l, 00.c.f w, \ 18 Data, linear=physical, full 4Gbytes + ffff w, 9b.0f0000 l, 00.0.0 w, \ 20 Code16, base f.0000, 64K + ffff w, 93.0f0000 l, 00.0.0 w, \ 28 Data16, base f.0000, 64K \ ------->>>>> Startup code, reached by branch from main entry point below \ - \ ffff.fc20 + \ ffff.fc30 here \ Mark the beginning of this code so its size may be determined \ and so that a jump to it may be assembled later. @@ -170,8 +171,8 @@ here over - ( adr , size-of-preceding-code ) - \ ffff.fc20 is the location of the code that follows the GDT - ffff.fff0 ffff.fc20 - swap - ( address #bytes-to-pad ) + \ ffff.fc30 is the location of the code that follows the GDT + ffff.fff0 ffff.fc30 - swap - ( address #bytes-to-pad ) \ The code mustn't extend past ffff.ffc0, because that is where PC \ manufacturers put the 0x10-byte BIOS version string. @@ -187,7 +188,7 @@ 16-bit cli cld \ Turn off interrupts (does not affect NMI) - #) jmp \ Relative jump back to ffff.fc20 + #) jmp \ Relative jump back to ffff.fc30 0 w, 0 c, \ align "pad" to end of ROM loader-version# l, \ version# loader-format# w, \ "format" (>1 when crc present) Modified: cpu/x86/pc/olpc/via/romreset.bth =================================================================== --- cpu/x86/pc/olpc/via/romreset.bth 2009-06-29 19:30:06 UTC (rev 1229) +++ cpu/x86/pc/olpc/via/romreset.bth 2009-06-30 19:53:14 UTC (rev 1230) @@ -11,7 +11,10 @@ \needs start-assembling fload ${BP}/cpu/x86/asmtools.fth \needs write-dropin fload ${BP}/forth/lib/mkdropin.fth +\needs >seg:off fload ${BP}/cpu/x86/pc/rmtools.fth +h# 20 constant rm-cs \ Must agree with GDT in rmstart.fth + fload ${BP}/cpu/x86/mmuparam.fth \ startmacros.fth defines some assembler macros that make MSR and I/O port @@ -170,12 +173,21 @@ bx ax mov h# 1c00 invert # ax and acpi-io-base 4 + # dx mov op: ax dx out char r report - resume-data # sp mov - resume-entry # ax mov ax call \ This might return if checksumming fails + cli + + facs-adr h# c + #) ax mov ax ax or 0<> if + \ Resume in real mode for ACPI operating systems + \ Linear wakeup address is in EAX + sp sp xor \ Possibly unnecessary + wake-adr >seg:off drop rm-cs #) far jmp + else + \ Resume in 32-bit protected mode for OFW + resume-data # sp mov + resume-entry # ax mov ax call \ This might return if checksumming fails + then char x report then \ Not a wakeup from S3 - \ Cache is now setup normally, backed by memory h# 20.0000 # esp mov Modified: dev/olpc/dcon/viadcon.fth =================================================================== --- dev/olpc/dcon/viadcon.fth 2009-06-29 19:30:06 UTC (rev 1229) +++ dev/olpc/dcon/viadcon.fth 2009-06-30 19:53:14 UTC (rev 1230) @@ -83,7 +83,7 @@ d# 50 ms wait-output dcon-load \ Put the DCON in VGA-refreshed mode - d# 25 us + d# 25 ms \ Ensure that that DCON sees the DCONLOAD high \ display-on else dcon-unload \ Put the DCON in self-refresh mode

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r1229 - cpu/x86/pc/olpc

by svn＠openfirmware.info

Author: wmb Date: 2009-06-29 21:30:06 +0200 (Mon, 29 Jun 2009) New Revision: 1229 Modified: cpu/x86/pc/olpc/dsdt.bth Log: dsdt.bth - added -p option to force the output filename in the face of a change to the way that some newer versions of iasl construct the output filename. Modified: cpu/x86/pc/olpc/dsdt.bth =================================================================== --- cpu/x86/pc/olpc/dsdt.bth 2009-06-29 12:17:35 UTC (rev 1228) +++ cpu/x86/pc/olpc/dsdt.bth 2009-06-29 19:30:06 UTC (rev 1229) @@ -3,7 +3,7 @@ command: &builder &this build-now -" iasl -vi -vr -vs ../dsdt.dsl" expand$ $sh +" iasl -p dsdt -vi -vr -vs ../dsdt.dsl" expand$ $sh \ " iasl -vi -vr -vs ../fadt.dsl" expand$ $sh \ " iasl -vi -vr -vs ../ssdt.dsl" expand$ $sh

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r1228 - cpu/x86/pc/olpc/via

by svn＠openfirmware.info

Author: wmb Date: 2009-06-29 14:17:35 +0200 (Mon, 29 Jun 2009) New Revision: 1228 Modified: cpu/x86/pc/olpc/via/fw.bth cpu/x86/pc/olpc/via/smbios.fth Log: OLPC Via - moved setup-smbios to an effective place in the startup sequence. Modified: cpu/x86/pc/olpc/via/fw.bth =================================================================== --- cpu/x86/pc/olpc/via/fw.bth 2009-06-28 01:14:50 UTC (rev 1227) +++ cpu/x86/pc/olpc/via/fw.bth 2009-06-29 12:17:35 UTC (rev 1228) @@ -675,6 +675,7 @@ ['] false to interrupt-auto-boot? probe-usb " probe+" do-drop-in + setup-smbios \ Must be done after build-date is defined via do-drop-in interpreter-init [ifdef] Later Modified: cpu/x86/pc/olpc/via/smbios.fth =================================================================== --- cpu/x86/pc/olpc/via/smbios.fth 2009-06-28 01:14:50 UTC (rev 1227) +++ cpu/x86/pc/olpc/via/smbios.fth 2009-06-29 12:17:35 UTC (rev 1228) @@ -479,7 +479,3 @@ smbios-adr h# 1f 4 fix-checksum \ Overall checksum smbios-adr h# 10 + h# 0f 5 fix-checksum \ Intermediate checksum ; - -stand-init: SMBIOS tables - setup-smbios -;

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r1227 - cpu/x86/pc/olpc cpu/x86/pc/olpc/via dev/olpc/kb3700

by svn＠openfirmware.info

Author: rsmith Date: 2009-06-28 03:14:50 +0200 (Sun, 28 Jun 2009) New Revision: 1227 Modified: cpu/x86/pc/olpc/rtcwake.fth cpu/x86/pc/olpc/via/versions.fth dev/olpc/kb3700/battery.fth dev/olpc/kb3700/ecio.fth Log: - Add support for general purpose ec timer driven wakeups - Add some test code for testing ec timer driven wakeups - words for flipping of a LiFePO4 debug dump bit - autowack support code update - Make OFW pull EC version 1.9.4 Modified: cpu/x86/pc/olpc/rtcwake.fth =================================================================== --- cpu/x86/pc/olpc/rtcwake.fth 2009-06-26 18:19:51 UTC (rev 1226) +++ cpu/x86/pc/olpc/rtcwake.fth 2009-06-28 01:14:50 UTC (rev 1227) @@ -69,6 +69,21 @@ key drop ; +\ for testing wakeups from the EC +: wackup-test-ec ( ms -- ) + d# 3000 autowack-delay \ At small ms delays the host can miss the SCI so this + \ is the back up. + 0 begin ( ms count ) + autowack-on swap dup ( count ms ms ) + ec-wackup ( count ms ) + s + swap dup ( ms count count ) + space .d (cr 1+ key? ( ms count+1 ) + until + key drop 2drop + autowack-off +; + stand-init: Century h# 20 cmos-century cmos! \ The century is in BCD, hence h# ; Modified: cpu/x86/pc/olpc/via/versions.fth =================================================================== --- cpu/x86/pc/olpc/via/versions.fth 2009-06-26 18:19:51 UTC (rev 1226) +++ cpu/x86/pc/olpc/via/versions.fth 2009-06-28 01:14:50 UTC (rev 1227) @@ -2,10 +2,10 @@ \ The overall firmware revision macro: FW_MAJOR A -macro: FW_MINOR 04a +macro: FW_MINOR 04b \ The EC microcode -macro: EC_VERSION 1_9_1 +macro: EC_VERSION 1_9_4 \ Alternate command for getting EC microcode, for testing new versions. \ Temporarily uncomment the line and modify the path as necessary Modified: dev/olpc/kb3700/battery.fth =================================================================== --- dev/olpc/kb3700/battery.fth 2009-06-26 18:19:51 UTC (rev 1226) +++ dev/olpc/kb3700/battery.fth 2009-06-28 01:14:50 UTC (rev 1227) @@ -134,10 +134,11 @@ : see-bstate 0 begin - next-bstate dup . - dup 4 = if + next-bstate + dup 0 = if cr - then key? + then + dup . key? until ; @@ -166,6 +167,13 @@ \ Turn off the trickle charger : bat-disable-trickle ( -- ) fc23 ec@ 1 invert and fc23 ec! ; +\ Turn on the EC lifepo4 dump +: bat-enable-ec-life-dump ( -- ) f915 ec@ 8 or f915 ec! ; + +\ Turn on the EC lifepo4 dump +: bat-disable-ec-life-dump ( -- ) f915 ec@ 8 invert and f915 ec! ; + + \ Access the 1-wire data line via the EC GPIO ports h# 383 constant dataport Modified: dev/olpc/kb3700/ecio.fth =================================================================== --- dev/olpc/kb3700/ecio.fth 2009-06-26 18:19:51 UTC (rev 1226) +++ dev/olpc/kb3700/ecio.fth 2009-06-28 01:14:50 UTC (rev 1227) @@ -20,10 +20,6 @@ iobase 3 + pc! ; -: autowak! ( value -- ) f64f ec! ; -: autowak-on ( -- ) 1 autowak! ; -: autowak-off ( -- ) 0 autowak! ; -: autowak-delay ( delay -- ) wbsplit f650 ec! f651 ec! ; : kbc-debug-on ( -- ) 1 fbfe ec! ; : kbc-debug-off ( -- ) 0 fbfe ec! ; @@ -66,8 +62,10 @@ : ec-rw ( -- w ) ec-rb ec-rb swap bwjoin ; : ec-ww ( -- w ) wbsplit ec-wb ec-wb ; +: ec-wl ( -- l ) lbsplit ec-wb ec-wb ec-wb ec-wb ; : (ec-cmd-b!) ( b cmd -- ) ec-cmd-out ec-wb ; +: (ec-cmd-l!) ( l cmd -- ) ec-cmd-out ec-wl ; : (ec-cmd-b@) ( cmd -- b ) ec-cmd-out ec-rb ; : (ec-cmd-w@) ( cmd -- w ) ec-cmd-out ec-rw ; @@ -94,6 +92,17 @@ loop ( b cmd ) too-many-retries ; + +: ec-cmd-l! ( l cmd -- ) + #ec-retries 0 do ( b cmd ) + 2dup ['] (ec-cmd-l!) catch 0= if ( b cmd ) + 2drop unloop exit + then ( b cmd x x ) + 2drop ( b cmd ) + loop ( b cmd ) + too-many-retries +; + : ec-cmd-b@ ( cmd -- b ) #ec-retries 0 do ( cmd ) dup ['] (ec-cmd-b@) catch 0= if ( cmd b ) @@ -157,7 +166,7 @@ too-many-retries ; -: ec-wakeup! ( wakeup -- ) lbsplit h# 36 ec-cmd-out ec-wb ec-wb ec-wb ec-wb ; +: ec-wackup ( ms -- ) lbsplit h# 36 ec-cmd-out ec-wb ec-wb ec-wb ec-wb ; : ec-abnormal@ ( -- b ) h# 1f ec-cmd-b@ ; @@ -181,7 +190,10 @@ : sci-inhibit ( -- ) h# 32 ec-cmd ; : sci-uninhibit ( -- ) h# 34 ec-cmd ; -: sci-inhibit-delay ( delay -- ) wbsplit f64d ec! f64e ec! ; +: autowack-on ( -- ) 1 33 ec-cmd-b! ; +: autowack-off ( -- ) 0 33 ec-cmd-b! ; +: autowack-delay ( delay -- ) wbsplit f650 ec! f651 ec! ; + : ec-indexed-io-off ( -- ) h# fe95 ec@ h# 40 invert and h# fe95 ec! ; 0 [if]

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r1226 - cpu/x86/pc/olpc/via

by svn＠openfirmware.info

Author: wmb Date: 2009-06-26 20:19:51 +0200 (Fri, 26 Jun 2009) New Revision: 1226 Modified: cpu/x86/pc/olpc/via/suspend.fth cpu/x86/pc/olpc/via/versions.fth Log: Via - Added sci-wakeup, lid-wakeup, ebook-wakeup, batlow-wakeup. Modified: cpu/x86/pc/olpc/via/suspend.fth =================================================================== --- cpu/x86/pc/olpc/via/suspend.fth 2009-06-26 16:10:47 UTC (rev 1225) +++ cpu/x86/pc/olpc/via/suspend.fth 2009-06-26 18:19:51 UTC (rev 1226) @@ -12,14 +12,11 @@ code ax-call ( ax-value dst -- ) bx pop ax pop bx call c; -.( XXX Implement lid-wakeup) cr -: lid-wakeup -; +: batlow-wakeup ( -- ) h# 22 acpi-w@ h# 1000 or h# 22 acpi-w! ; +: ebook-wakeup ( -- ) h# 22 acpi-w@ h# 0100 or h# 22 acpi-w! ; +: lid-wakeup ( -- ) h# 22 acpi-w@ h# 0800 or h# 22 acpi-w! ; +: sci-wakeup ( -- ) h# 22 acpi-w@ h# 0002 or h# 22 acpi-w! ; -.( XXX Implement sci-wakeup) cr -: sci-wakeup -; - : s3 \ Enable wakeup from power button, also clearing \ any status bits in the low half of the register. Modified: cpu/x86/pc/olpc/via/versions.fth =================================================================== --- cpu/x86/pc/olpc/via/versions.fth 2009-06-26 16:10:47 UTC (rev 1225) +++ cpu/x86/pc/olpc/via/versions.fth 2009-06-26 18:19:51 UTC (rev 1226) @@ -2,7 +2,7 @@ \ The overall firmware revision macro: FW_MAJOR A -macro: FW_MINOR 04 +macro: FW_MINOR 04a \ The EC microcode macro: EC_VERSION 1_9_1

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r1225 - cpu/x86 cpu/x86/pc cpu/x86/pc/olpc/via ofw/inet

by svn＠openfirmware.info

Author: wmb Date: 2009-06-26 18:10:47 +0200 (Fri, 26 Jun 2009) New Revision: 1225 Added: cpu/x86/pc/olpc/via/smbios.fth Modified: cpu/x86/apic.fth cpu/x86/pc/apic.fth cpu/x86/pc/olpc/via/acpi.fth cpu/x86/pc/olpc/via/addrs.fth cpu/x86/pc/olpc/via/config.fth cpu/x86/pc/olpc/via/dsdt.dsl cpu/x86/pc/olpc/via/fw.bth cpu/x86/pc/olpc/via/ioinit.fth cpu/x86/pc/olpc/via/versions.fth ofw/inet/ip.fth Log: OLPC q3a04 - ACPI and SMBIOS enabled, suspend/resume works from OFW. Modified: cpu/x86/apic.fth =================================================================== --- cpu/x86/apic.fth 2009-06-25 21:23:17 UTC (rev 1224) +++ cpu/x86/apic.fth 2009-06-26 16:10:47 UTC (rev 1225) @@ -44,9 +44,9 @@ : id! ( id -- ) d# 24 lshift d# 20 apic! ; : id@ ( -- id ) d# 20 apic@ d# 24 rshift ; : lvt0@ ( -- n ) h# 350 apic@ ; -: lvt0! ( n -- ) h# 350 apic@ ; +: lvt0! ( n -- ) h# 350 apic! ; : lvt1@ ( -- n ) h# 360 apic@ ; -: lvt1! ( n -- ) h# 360 apic@ ; +: lvt1! ( n -- ) h# 360 apic! ; : lvt0-disable-irq ( -- ) h# 10000 h# 350 apic-set ; \ Disable LINT0 : lvt0-enable-irq ( -- ) h# 10000 h# 350 apic-clr ; \ Enable LINT0 @@ -148,6 +148,8 @@ : open ( -- okay? ) io-apic-base 0= if io-apic-mmio-base h# 80 " map-in" $call-parent to io-apic-base + 1 d# 24 lshift 0 io-apic! \ I/O APIC ID + 1 3 io-apic! \ Front side bus message delivery then true ; Modified: cpu/x86/pc/apic.fth =================================================================== --- cpu/x86/pc/apic.fth 2009-06-25 21:23:17 UTC (rev 1224) +++ cpu/x86/pc/apic.fth 2009-06-26 16:10:47 UTC (rev 1225) @@ -123,10 +123,10 @@ 20 0 30 50014 -80 f0 +80 f0 (00) d0 0 e0 ffffffff -f0 10f +f0 10f (1ff) Spurious vector number 320 10000 Timer Masked off 340 10000 PCINT Masked off 350 700 LINT0 vector 0 mode ExtINT (111) Edge Trigger Active High @@ -164,7 +164,7 @@ indirect io apic regs 00 1000000 IOAPIC ID is 1 01 178003 (RO) version -02 1000000 Arb ID is 1 +02 1000000 (RO) Arb ID is 1 03 1 Front side bus message delivery 10,11 0100.0000 . 0001.0000 DD00 . 0000 . 000 ooom . tips MVV .. Modified: cpu/x86/pc/olpc/via/acpi.fth =================================================================== --- cpu/x86/pc/olpc/via/acpi.fth 2009-06-25 21:23:17 UTC (rev 1224) +++ cpu/x86/pc/olpc/via/acpi.fth 2009-06-26 16:10:47 UTC (rev 1225) @@ -2,9 +2,13 @@ h# 0. 2constant xsdt-adr +: set-acpi-table-length ( table-adr -- ) + here over - swap la1+ l! +; + create fadt ( 000 4 ) " FACP" $, \ Signature -( 004 4 ) h# 84 l, \ Table Length +( 004 4 ) h# 84 l, \ Length ( 008 1 ) h# 02 c, \ Revision (supports reset adr) ( 009 1 ) h# 00 c, \ Checksum ( 00A 6 ) " OLPC " $, \ Oem ID @@ -27,24 +31,22 @@ ( 037 1 ) h# 00 c, \ P-State Control ( 038 4 ) h# 400 l, \ PM1A Event Block Address ( 03C 4 ) h# 0 l, \ PM1B Event Block Address -\ ( 040 4 ) h# 9c28 l, \ PM1A Control Block Address ( 040 4 ) h# 404 l, \ PM1A Control Block Address ( 044 4 ) h# 0 l, \ PM1B Control Block Address -( 048 4 ) h# 0 l, \ PM2 Control Block Address (don't support) -\ ( 04C 4 ) h# 9c10 l, \ PM Timer Block Address +( 048 4 ) h# 22 l, \ PM2 Control Block Address ( 04C 4 ) h# 408 l, \ PM Timer Block Address ( 050 4 ) h# 420 l, \ GPE0 Block Address ( 054 4 ) h# 0 l, \ GPE1 Block Address ( 058 1 ) h# 4 c, \ PM1 Event Block Length ( 059 1 ) h# 2 c, \ PM1 Control Block Length -( 05A 1 ) h# 0 c, \ PM2 Control Block Length +( 05A 1 ) h# 1 c, \ PM2 Control Block Length ( 05B 1 ) h# 4 c, \ PM Timer Block Length ( 05C 1 ) h# 4 c, \ GPE0 Block Length ( 05D 1 ) h# 0 c, \ GPE1 Block Length ( 05E 1 ) h# 10 c, \ GPE1 Base Offset ( 05F 1 ) h# 85 c, \ _CST Support -( 060 2 ) h# 1 w, \ C2 Latency -( 062 2 ) h# 1 w, \ C3 Latency +( 060 2 ) d# 10 w, \ C2 Latency (guess) +( 062 2 ) d# 100 w, \ C3 Latency (guess) ( 064 2 ) h# 0 w, \ CPU Cache Size ( 066 2 ) h# 0 w, \ Cache Flush Stride ( 068 1 ) h# 0 c, \ Duty Cycle Offset @@ -59,37 +61,24 @@ ( 080 1 ) h# 1 c, \ Reset value ( 081 3 ) 0 c, 0 c, 0 c, \ Reserved -here fadt - constant /fadt +fadt set-acpi-table-length \ FADT Flags: \ WBINVD is operational : 1 \ WBINVD does not invalidate : 0 \ All CPUs support C1 : 1 \ C2 works on MP system : 0 -\ Power button is generic : 0 -\ Sleep button is generic : 1 +\ Power button is generic : 0 ?? +\ Sleep button is generic : 1 ?? \ RTC wakeup not fixed : 0 \ RTC wakeup/S4 not possible : 1 \ 32-bit PM Timer : 1 \ Docking Supported : 0 \ Reset Register Supported: 1 -create rsdp -( 00 8 ) " RSD PTR " $, \ Signature -( 08 1 ) 00 c, \ Checksum -( 09 6 ) " OLPC " $, \ Oem Id -( 0f 1 ) 2 c, \ ACPI revision (3.0b) -( 10 4 ) rsdt-adr l, \ RSDT Address - -( 14 4 ) d# 36 l, \ Length for extended version -( 18 8 ) xsdt-adr d, \ XSDT Address -( 20 1 ) 0 c, \ extended checksum -( 21 3 ) 0 c, 0 c, 0 c, \ reserved -here rsdp - constant /rsdp - create madt \ Multiple APIC Descriptor Table ( 000 4 ) " APIC" $, \ Signature -( 004 4 ) h# 5a l, \ Table Length +( 004 4 ) h# 5a l, \ Length ( 008 1 ) h# 01 c, \ Revision ( 009 1 ) h# 00 c, \ Checksum ( 00A 6 ) " OLPC " $, \ Oem ID @@ -106,7 +95,6 @@ ( 02f 1 ) 0 c, \ ACPI ID ( 030 4 ) 1 l, \ Flags - 1 means this processor is usable - ( 034 1 ) 1 c, \ I/O APIC ( 035 1 ) d# 12 c, \ length ( 036 1 ) 1 c, \ I/O APIC ID @@ -133,11 +121,11 @@ ( 053 1 ) 9 c, \ Bus-relative IRQ ( 054 4 ) 9 l, \ Interrupt # that this source will trigger ( 058 2 ) h# f w, \ Flags - active low, level triggered -here madt - constant /madt +madt set-acpi-table-length create hpet \ High Precision Event Timer table ( 000 4 ) " HPET" $, \ Signature -( 004 4 ) h# 38 l, \ Table Length +( 004 4 ) h# 38 l, \ Length ( 008 1 ) h# 01 c, \ Revision ( 009 1 ) h# 00 c, \ Checksum ( 00A 6 ) " OLPC " $, \ Oem ID @@ -155,13 +143,11 @@ ( 034 1 ) 0 c, \ Sequence ( 035 2 ) 0 w, \ Min tick ( 037 1 ) 0 c, \ flags -here hpet - constant /hpet +hpet set-acpi-table-length create rsdt ( 00 4 ) " RSDT" $, \ Signature ( 04 4 ) h# 34 l, \ Length -\ ( 04 4 ) h# 30 l, \ Length -\ ( 04 4 ) h# 2c l, \ Length ( 08 1 ) 1 c, \ Revision ( 09 1 ) 00 c, \ Checksum ( 0a 6 ) " OLPC " $, \ Oem Id @@ -176,7 +162,7 @@ \ ( 2c 4 ) dbgp-adr l, \ DBGP Address \ ( 30 4 ) ssdt-adr l, \ SSDT Address \ ( 30 4 ) prtn-adr l, \ PRTN Address -here rsdt - constant /rsdt +rsdt set-acpi-table-length 0 [if] create dbgp @@ -192,7 +178,7 @@ ( 24 1 ) 0 c, \ Full 16550 interface ( 25 3 ) 0 c, 0 c, 0 c, \ reserved ( 28 c ) 1 c, 8 c, 0 c, 1 c, h# 3f8 l, 0 l, \ Port base address (generic register descriptor) -here dbgp - constant /dbgp +dbgp set-acpi-table-length [then] create facs @@ -205,8 +191,21 @@ ( 18 8 ) 0. d, \ 64-bit waking vector ( 20 1 ) 1 c, \ Version ( 21 1f ) here d# 31 dup allot erase -here facs - constant /facs +facs set-acpi-table-length +create rsdp +( 00 8 ) " RSD PTR " $, \ Signature +( 08 1 ) 00 c, \ Checksum +( 09 6 ) " OLPC " $, \ Oem Id +( 0f 1 ) 2 c, \ ACPI revision (3.0b) +( 10 4 ) rsdt-adr l, \ RSDT Address + +( 14 4 ) d# 36 l, \ Length for extended version +( 18 8 ) xsdt-adr d, \ XSDT Address +( 20 1 ) 0 c, \ extended checksum +( 21 3 ) 0 c, 0 c, 0 c, \ reserved +here rsdp - constant /rsdp + : fix-checksum ( table /table checksum-offset -- ) >r over >r ( table /table r: cksum-offset table ) 0 -rot bounds ?do i c@ + loop ( sum ) @@ -227,6 +226,12 @@ h# 1000 - \ Safety page ; +: >acpi-table-len ( adr -- len ) la1+ l@ ; +: copy-acpi-table ( src dst -- ) + tuck over >acpi-table-len move ( dst ) + dup >acpi-table-len 9 fix-checksum +; + : setup-acpi ( -- ) [ifdef] notdef \ This has to agree with the _SB's _INI method, which gets the memory size @@ -234,14 +239,14 @@ memory-limit d# 10 rshift 'ebda h# 180 + l! [then] - \ Copy rsdt and fadt to low memory + \ Copy tables to low memory + fadt fadt-adr copy-acpi-table + madt madt-adr copy-acpi-table + hpet hpet-adr copy-acpi-table +\ dbgp dbgp-adr copy-acpi-table + facs facs-adr facs >acpi-table-len move + rsdt rsdt-adr copy-acpi-table rsdp rsdp-adr /rsdp move rsdp-adr h# 14 8 fix-checksum rsdp-adr /rsdp h# 20 fix-checksum - rsdt rsdt-adr /rsdt move rsdt-adr /rsdt 9 fix-checksum - fadt fadt-adr /fadt move fadt-adr /fadt 9 fix-checksum - madt madt-adr /madt move madt-adr /madt 9 fix-checksum - hpet hpet-adr /hpet move hpet-adr /hpet 9 fix-checksum -\ dbgp dbgp-adr /dbgp move dbgp-adr /dbgp 9 fix-checksum - facs facs-adr /facs move \ Copy in the DSDT \ I suppose we could point to it in FLASH - if so don't compress it, @@ -261,10 +266,8 @@ h# ffffffff h# 20 acpi-l! \ Ack all leftover events ; -.( Not setting up ACPI automatically) cr stand-init: ACPI tables -." Not setting up ACPI automatically" cr -\ setup-acpi + setup-acpi ; \ Geode h# 6000 constant xp-smbus-base Modified: cpu/x86/pc/olpc/via/addrs.fth =================================================================== --- cpu/x86/pc/olpc/via/addrs.fth 2009-06-25 21:23:17 UTC (rev 1224) +++ cpu/x86/pc/olpc/via/addrs.fth 2009-06-26 16:10:47 UTC (rev 1225) @@ -74,6 +74,8 @@ h# fc000 constant dsdt-adr h# fd000 constant ssdt-adr +h# ffc00 constant smbios-adr + h# 3e.0000 constant inflate-base h# 30.0000 constant workspace Modified: cpu/x86/pc/olpc/via/config.fth =================================================================== --- cpu/x86/pc/olpc/via/config.fth 2009-06-25 21:23:17 UTC (rev 1224) +++ cpu/x86/pc/olpc/via/config.fth 2009-06-26 16:10:47 UTC (rev 1225) @@ -9,6 +9,7 @@ [ifdef] xo-board create use-ec [then] +create use-apic \ --- The environment that "boots" us --- \ - Image Format - Example Media - previous stage bootloader Modified: cpu/x86/pc/olpc/via/dsdt.dsl =================================================================== --- cpu/x86/pc/olpc/via/dsdt.dsl 2009-06-25 21:23:17 UTC (rev 1224) +++ cpu/x86/pc/olpc/via/dsdt.dsl 2009-06-26 16:10:47 UTC (rev 1225) @@ -18,10 +18,12 @@ Store (Arg1, CMSD) } // Processor Objects - Scope(\_PR) { - Processor(\_PR.CPU0,0x00,0x00000410,0x06){} - } - +Scope(\_PR) +{ + Processor(\_PR.CPU0,0x00,0x00000410,0x06) + { + } +} // System Sleep States Name(\_S0,Package(){0,0,0,0}) Name(\_S1,Package(){4,4,4,4}) @@ -888,13 +890,13 @@ ECDX, 2 //USB3 PM capability status register } - Method(_STA,0) { //Status of the USB3 Device - If(LEqual(\_SB.PCI0.USB3.CMDR, 0x00)) { - Return(0x0D) - } Else { - Return(0x0F) - } + Method(_STA,0) { //Status of the USB3 Device + If(LEqual(\_SB.PCI0.USB3.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) } + } } @@ -904,7 +906,7 @@ Name(_PRW, Package(2){0x0E,3}) Name(_S3D, 3) - + OperationRegion(U2F4,PCI_Config,0x00,0xC2) Field(U2F4,ByteAcc,NoLock,Preserve){ Offset(0x00), Modified: cpu/x86/pc/olpc/via/fw.bth =================================================================== --- cpu/x86/pc/olpc/via/fw.bth 2009-06-25 21:23:17 UTC (rev 1224) +++ cpu/x86/pc/olpc/via/fw.bth 2009-06-26 16:10:47 UTC (rev 1225) @@ -346,10 +346,11 @@ fload ${BP}/cpu/x86/pc/olpc/via/acpi.fth +fload ${BP}/cpu/x86/pc/olpc/via/smbios.fth + [ifdef] Later fload ${BP}/cpu/x86/pc/rmtools.fth fload ${BP}/dev/geode/smi.fth -fload ${BP}/cpu/x86/pc/olpc/smbios.fth \ fload ${BP}/cpu/x86/pc/biosload/rmenter.fth fload ${BP}/cpu/x86/pc/biosints.fth fload ${BP}/cpu/x86/pc/olpc/biosresume.fth Modified: cpu/x86/pc/olpc/via/ioinit.fth =================================================================== --- cpu/x86/pc/olpc/via/ioinit.fth 2009-06-25 21:23:17 UTC (rev 1224) +++ cpu/x86/pc/olpc/via/ioinit.fth 2009-06-26 16:10:47 UTC (rev 1225) @@ -167,7 +167,7 @@ [then] .( Check RTC century byte mapping to cmos 32 - see d17f0 rx58) cr [ifdef] use-apic - 58 40 40 mreg \ Enable Internal APIC + 58 40 40 mreg \ Enable Internal IO-APIC [then] [ifdef] xo-board 59 ff 1c mreg \ Keyboard (ports 60,64) and ports 62,66 on LPC bus (EC) @@ -257,6 +257,9 @@ [ifdef] use-apic e7 80 80 mreg \ Enable APIC Cycle Reflect to ALL Bus Master Activity Effective Signal [then] +[ifdef] xo-board + ec 04 00 mreg \ C3 state setting +[then] fc 06 04 mreg \ DPSLP# to SLP# Latency Adjustment - 22.5 us end-table @@ -278,7 +281,7 @@ \ 74 d8 08 mreg \ Lock Cycle Issued by CPU Blocks P2C Cycles (04 bit is reserved) 74 dc 0c mreg \ Lock Cycle Issued by CPU Blocks P2C Cycles - 04 res be like Phx 75 ff 0f mreg \ Use New grant mechanism for PCI arbitration, PCI Master Bus Timeout is 7x16 PCI clock - 76 fd 50 mreg \ Enable PCI parking, Grant to CPU after 2 PC master grants + 76 fd d0 mreg \ Enable PCI parking, Grant to CPU after 2 PC master grants, support IO address 22 for C3 77 58 48 mreg \ PCI1 FIFO empty blocks CPU to PCI read, Read FIFO times out after 1 ms 80 07 07 mreg \ PCI1 and HDAC upstream read does not pass write, APCI blocks upstream write \ 82 3e 20 mreg \ Monitor CCA and SDIO2 @@ -316,4 +319,6 @@ \ 00 to run - Axxxxx hits VGA in normal mode, hits shadow DRAM in SMM \ 01 to access VGA when in SMM (data cycles only) +\ acpi-io-base h# 26 + port-rb h# 07 bitset al dx out \ Settings to support C4 state +acpi-io-base h# 26 + port-rb h# 06 bitset al dx out \ Settings to support C3 state acpi-io-base h# 4c + port-rl h# 400 bitset ax dx out \ Set USB power high Added: cpu/x86/pc/olpc/via/smbios.fth =================================================================== --- cpu/x86/pc/olpc/via/smbios.fth (rev 0) +++ cpu/x86/pc/olpc/via/smbios.fth 2009-06-26 16:10:47 UTC (rev 1225) @@ -0,0 +1,485 @@ +\ Make SMBIOS tables + + +0 [if] +h# ffbc0 constant 'pciirq +\ http://www.microsoft.com/whdc/archive/pciirq.mspx +\ create pciirq-header +\ h# 52495024 l, \ $PIR +\ h# 0100 w, \ version 1.0 +\ h# 0040 w, \ Total size +\ +\ 0 c, 0 c, \ Bus#, DevFunc# +\ 0 w, \ Exclusive IRQs +\ 0 l, \ Compatible router +\ 0 l, \ miniport data +\ 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, \ res +\ h# b0 c, \ checksum +\ \ Table data goes here + +: make-pciirq-table ( -- ) + 'pciirq h# 40 erase + h# 52495024 'pciirq l! \ $PIR + h# 0100 'pciirq la1+ w! \ version + h# 0040 'pciirq la1+ wa1+ w! \ total size + h# b0 'pciirq h# 1f + c! \ checksum + \ The rest of the table is 0 because the actual routing + \ is now done by ACPI +; +[then] + +: c$, $, 0 c, ; + +0 value #smbios-tables +: copy-smbios-table ( dst-adr table -- dst-adr' ) + #smbios-tables 1+ to #smbios-tables + 2dup 1+ c@ ( dst-adr table dst-adr len ) + dup >r move ( dst-adr r: len ) + r> + ( dst-adr' ) +; + +: smbios-c, ( dst-adr b -- dst-adr' ) over c! 1+ ; +: smbios-w, ( dst-adr w -- dst-adr' ) over le-w! wa1+ ; +: smbios-l, ( dst-adr l -- dst-adr' ) over le-l! la+ ; +: smbios-null ( dst-adr -- dst-adr' ) 0 smbios-c, ; +: end-smbios-table ( dst-adr -- dst-adr' ) smbios-null ; +: +smbios$ ( dst-adr adr len -- dst-adr' ) + 3dup rot swap move ( dst-adr adr len ) + nip + smbios-null +; + +0 value uuid-adr + +create smbios-entry +( 00 ) " _SM_" $, +( 04 ) 0 c, \ Byte checksum - structure must sum to 0 SETME +( 05 ) h# 1f c, \ Entry structure length +( 06 ) h# 02 c, \ Major version +( 07 ) h# 01 c, \ Minor version +( 08 ) h# 100 w, \ Maximum size of a structure +( 0a ) h# 00 c, \ Entry point revision +( 0b ) 0 c, 0 c, 0 c, 0 c, 0 c, \ Formatted area +( 10 ) " _DMI_" $, \ Intermediate anchor string +( 15 ) 0 c, \ Intermediate checksum SETME +( 16 ) 0 w, \ Structure table length SETME +( 18 ) 0 l, \ Structure table address SETME +\ ( 1c ) d# 11 w, \ Number of structures +( 1c ) d# 12 w, \ Number of structures +( 1e ) h# 21 c, \ BCD revision + +create bios-info +( 00 ) 0 c, \ BIOS info type code +( 01 ) h# 13 c, \ Length (one BIOS characteristic extension byte) +( 02 ) h# 0000 w, \ Handle +( 04 ) 1 c, \ Vendor string index +( 05 ) 2 c, \ Version string index +( 06 ) h# f000 w, \ BIOS starting address segment +( 08 ) 3 c, \ Release date index +( 09 ) h# 0f c, \ BIOS ROM size in 64K chunks, minus 1 +( 0a ) h# 99880 l, \ BIOS characteristics - PCI, Reflash, shadowing, CD boot, selectable boot, EDD +( 0e ) 0 l, \ Vendor and system specific BIOS characteristics +( 12 ) 1 c, \ ACPI is supported +\ " OLPC" c$, \ Vendor string +\ " Q2E00" c$, \ Version string +\ " 04/01/2008" c$, \ Release date string +\ 0 c, \ End + +create system-info +( 00 ) 1 c, \ System info type code +( 01 ) h# 19 c, \ Length (for v2.1) +( 02 ) h# 0100 w, \ Handle +( 04 ) 1 c, \ Manufacturer string index +( 05 ) 2 c, \ Product name string index +( 06 ) 3 c, \ Version string index +( 07 ) 4 c, \ Serial number string index +( 08 ) here to uuid-adr h# 10 allot \ SETME +( 18 ) 6 c, \ Wake up type +\ " OLPC" c$, \ 1: Manufacturer +\ " XO" c$, \ 2: Product Name +\ " 1" c$, \ 3: Version +\ " <sn>" c$, \ 4: Serial number +\ 0 c, + +create base-board-info +( 00 ) 2 c, \ System info type code +( 01 ) h# 8 c, \ Length (for v2.1) +( 02 ) h# 0200 w, \ Handle +( 04 ) 1 c, \ Manufacturer string index +( 05 ) 2 c, \ Product string index +( 06 ) 3 c, \ Version string index +( 07 ) 4 c, \ Serial number string index +\ " QUANTA" c$, \ 1: Manufacturer +\ " XO" c$, \ 2: Product Name +\ " 1" c$, \ 3: Version + + +create system-enclosure +( 00 ) 3 c, \ System enclosure type code +( 01 ) h# 0d c, \ Length (for v2.1) +( 02 ) h# 0300 w, \ Handle +( 04 ) 1 c, \ Manufacturer string index +( 05 ) 9 c, \ Type - laptop +( 06 ) 2 c, \ Version number string index +( 07 ) 0 c, \ Serial number string index +( 08 ) 0 c, \ Asset tag string index +( 09 ) 3 c, \ Boot-up state +( 0a ) 3 c, \ Power Supply State +( 0b ) 3 c, \ Thermal State +( 0c ) 5 c, \ Security Status - XXX set to 4 in secure mode +\ " OLPC" c$, \ 2: Manufacturer +\ " 1" c$, \ 3: Version +\ 0 c, + +create processor-info +( 00 ) 4 c, \ Processor info type code +( 01 ) h# 20 c, \ Length (for v2.1) +( 02 ) h# 0400 w, \ Handle +( 04 ) 0 c, \ Reference designator string index +( 05 ) 3 c, \ Type - CPU +( 06 ) 1 c, \ Family - other +( 07 ) 1 c, \ Manufacturer +( 08 ) h# 5a2 l, h# 88a93d l, \ CPUID results - Set dynamically later +( 10 ) 2 c, \ Processor version string index +( 11 ) h# 8c c, \ Processor voltage (h# 80 + 1.2V/10) +( 12 ) d# 33 w, \ External clock (main bus clock) +( 14 ) d# 433 w, \ Max speed +( 16 ) d# 433 w, \ Current speed +( 18 ) h# 41 c, \ CPU present and enabled +( 19 ) 6 c, \ Processor upgrade - None +( 1a ) h# 0701 w, \ L1 Cache Handle +( 1c ) h# 0703 w, \ L2 Cache Handle +( 1e ) h# ffff w, \ L3 Cache Handle +\ " AuthenticAMD" c$, \ 1: Manufacturer +\ 0 c, + +create l1-icache-info +( 00 ) 7 c, \ Cache info type code +( 01 ) h# 13 c, \ Length +( 02 ) h# 0701 w, \ Handle +( 04 ) 0 c, \ Socket string index +( 05 ) h# 180 w, \ Writeback, enabled, internal, not socketed, L1 +( 07 ) h# 8002 w, \ Max size - 128K +( 09 ) h# 8002 w, \ Installed size - 128K +( 0b ) 1 w, \ Supported SRAM type - unknown +( 0d ) 1 w, \ Installed SRAM type - unknown +( 0f ) 0 c, \ Speed (NS) +( 10 ) 1 c, \ ECC - other +( 11 ) 5 c, \ Type - Unified (actually it is split I and D but they are coherent) +( 12 ) 5 c, \ Associativity - 4-way set-associative +\ 0 w, + +0 [if] +create l1-dcache-info +( 00 ) 7 c, \ Cache info type code +( 01 ) h# 13 c, \ Length +( 02 ) h# 0702 w, \ Handle +( 04 ) 0 c, \ Socket string index +( 05 ) h# 180 w, \ Writeback, enabled, internal, not socketed, L1 +( 07 ) h# 8001 w, \ Max size - 64K +( 09 ) h# 8001 w, \ Installed size - 64K +( 0b ) 1 w, \ Supported SRAM type - unknown +( 0d ) 1 w, \ Installed SRAM type - unknown +( 0f ) 0 c, \ Speed (NS) +( 10 ) 3 c, \ ECC - none +( 11 ) 4 c, \ Type - Data +( 12 ) 8 c, \ Associativity - 16-way set-associative +\ 0 w, +[then] + +create l2-cache-info +( 00 ) 7 c, \ Cache info type code +( 01 ) h# 13 c, \ Length +( 02 ) h# 0703 w, \ Handle +( 04 ) 0 c, \ Socket string index +( 05 ) h# 181 w, \ Writeback, enabled, internal, not socketed, L2 +( 07 ) h# 8002 w, \ Max size - 128K +( 09 ) h# 8002 w, \ Installed size - 128K +( 0b ) 1 w, \ Supported SRAM type - unknown +( 0d ) 1 w, \ Installed SRAM type - unknown +( 0f ) 0 c, \ Speed (NS) +\ ( 10 ) 3 c, \ ECC - none +( 10 ) 1 c, \ ECC - other +( 11 ) 5 c, \ Type - Unified +( 12 ) h# a c, \ Associativity - 32-way set-associative +\ 0 w, + +0 value portinfo# +: make-smbios-port ( dst-adr connectortype porttype name$ -- dst-adr' ) + #smbios-tables 1+ to #smbios-tables + 2>r >r >r + 8 smbios-c, 9 smbios-c, + portinfo# h# 800 + smbios-w, portinfo# 1+ to portinfo# + 0 smbios-c, 0 smbios-c, \ Internal Refdes and Internal Connector Type + 1 smbios-c, \ String index + r> smbios-c, \ Connector type + r> smbios-c, \ Port type + 2r> +smbios$ \ Reference designator string + end-smbios-table +; + +create sd-slot-array +( 00 ) d# 9 c, \ physical-memory-array type code +( 01 ) h# 0d c, \ Length +( 02 ) h# d01 w, \ Handle +( 04 ) 1 c, \ Refdes +( 05 ) h# b c, \ Slot type - proprietary +( 06 ) 1 c, \ Bus width - other +( 07 ) 4 c, \ Usage - in use +( 08 ) 3 c, \ Length - short +( 09 ) h# 0000 w, \ ID - meaningless +( 0b ) 4 c, \ Characteristics 1 - 3.3V +( 0c ) 2 c, \ Characteristics 2 - hot plug + +create video-array +( 00 ) d# 10 c, \ onboard device type code +( 01 ) h# 06 c, \ Length +( 02 ) h# a01 w, \ Handle +( 04 ) h# 83 c, \ Enabled, type 3 (video) +( 05 ) 1 c, \ Description string + +create bios-lang-array +( 00 ) d# 13 c, \ BIOS language type code +( 01 ) h# 16 c, \ Length +( 02 ) h# d01 w, \ Handle +( 04 ) 1 c, \ Number of languages +( 05 ) 1 c, \ Flags - abbreviated format +( 06 ) 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, 0 c, \ Res +( 15 ) 1 c, \ Currrent language string + +create main-memory-array +( 00 ) d# 16 c, \ physical-memory-array type code +( 01 ) h# 0f c, \ Length +( 02 ) h# 1001 w, \ Handle +( 04 ) 3 c, \ Location - onboard +( 05 ) 3 c, \ Use - system memory +( 06 ) 3 c, \ ECC - none +( 07 ) h# 100000 l, \ Maximum size - 1024K KiB (1 GiB) +( 0b ) h# fffe w, \ Memory Error Info Handle - not provided +( 0d ) 1 w, \ Number of devices +\ 0 w, + +create memory-device +( 00 ) d# 17 c, \ physical-memory-array type code +( 01 ) h# 15 c, \ Length +( 02 ) h# 1101 w, \ Handle +( 04 ) h# 1001 w, \ Handle of "parent" memory array +( 06 ) h# fffe w, \ Memory Error Info Handle - not provided +( 08 ) d# 64 w, \ Total width +( 0a ) d# 64 w, \ Data width +( 0c ) h# 400 w, \ Size - 1024 MB +( 0e ) h# 0b c, \ Form factor - row of chips +( 0f ) 0 c, \ Set - not part of a set +( 10 ) 1 c, \ Device Locator string index +( 11 ) 0 c, \ Bank Locator string index +( 12 ) h# 13 c, \ Memory type - DDR3 +( 13 ) h# 0080 w, \ Memory type detail - Synchronous +\ " Soldered" c$, +\ 0 w, + +create ma-mapped-address +( 00 ) d# 19 c, \ memory-array-mapped-address type code +( 01 ) h# 0f c, \ Length +( 02 ) h# 1301 w, \ Handle +( 04 ) 0 l, \ Starting address - first KiB +( 08 ) h# fffff l, \ Ending address - last KiB +( 0c ) h# 31 w, \ Handle of "parent" memory array +( 0e ) h# 1 c, \ Partition width +\ 0 w, + +create pointing-device +( 00 ) d# 21 c, \ system boot info type code +( 01 ) h# 07 c, \ Length +( 02 ) h# 1501 w, \ Handle +( 04 ) 7 c, \ Type - touchpad +( 05 ) 4 c, \ Interface - PS/2 +( 06 ) 2 c, \ #buttons - 2 + + +create system-boot-info +( 00 ) d# 32 c, \ system boot info type code +( 01 ) h# 0b c, \ Length +( 02 ) h# 2000 w, \ Handle +( 04 ) 0 l, 0 w, \ 6 reseved bytes +( 0a ) 0 c, \ Boot status - no errors +\ 0 w, + +create end-array +( 00 ) h# 7f c, \ End type code +( 01 ) h# 04 c, \ Length +( 02 ) h# 7f01 w, \ Handle + + +: test-name$ ( -- $ ) " IE8y2D ScD%g4r2bAIFA." ; +: test-version$ ( -- $ ) " OLPC Ver 1.50.01" ; +: fw-version$ ( -- $ ) + " /openprom" find-package if + " model" rot get-package-property 0= if + get-encoded-string ( adr len ) + dup d# 16 = if + \ We just want the "Q2E00" part + drop 6 + 5 exit + then + 2drop + then + then + " Unknown" +; +d# 10 buffer: fw-date-buf + +\ Convert build-date format "2008-04-14" to SMBIOS format "04/14/2008" +: fw-date$ ( -- $ ) + " xx/xx/xxxx" fw-date-buf swap move + " build-date" evaluate drop ( adr ) + dup fw-date-buf 6 + 4 move ( adr ) \ Year + dup 5 + fw-date-buf 2 move ( adr ) \ Month + 8 + fw-date-buf 3 + 2 move ( ) \ Day + fw-date-buf d# 10 +; +: get-tag$ ( tag$ -- value$ ) find-tag 0= if " Not Available" then ?-null ; + +: too-long? ( dst-adr -- dst-adr flag ) dup pad - h# 10 >= ; +: (uuid) ( -- true | adr len false ) + " U#" find-tag if ( adr len ) + ?-null ( adr len' ) + pad -rot ( dst-adr adr len ) + bounds ?do ( dst-adr ) + too-long? if drop true unloop exit then + i c@ h# 10 digit if ( dst-adr digith ) + i 1+ c@ h# 10 digit if ( dst-adr digith digitl ) + swap 4 lshift or ( dst-adr byte ) + over c! 1+ ( dst-adr' ) + 2 ( dst-adr advance ) + else ( dst-adr digith char ) + 3drop true unloop exit + then ( dst-adr ) + else ( dst-adr char ) + [char] - <> if drop true unloop exit then + 1 ( dst-adr advance ) + then ( dst-adr advance ) + +loop ( dst-adr ) + pad tuck - ( adr len ) + dup h# 10 = if ( adr len ) + false \ Good UUID ( adr len false ) + else ( adr len ) + 2drop true ( true ) + then ( true | adr len false ) + else ( ) + true ( true ) + then ( true | adr len false ) +; +: get-uuid ( -- uuid$ ) + (uuid) if " "(00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff)" then +; + +code get-cpuid ( code -- eax ebx ecx edx ) + ax pop cpuid ax push bx push cx push dx push +c; +0 value ptr +: 0pad ( -- ) pad to ptr ; +: pad, ( n -- ) ptr ! ptr na1+ to ptr ; + +: cpu-family$ ( -- adr len ) + 0 get-cpuid 0pad rot pad, pad, pad, drop + pad d# 12 +; + +: 4scramble ( a b c d -- d c b a ) swap 2swap swap ; +: cpu-name, ( cpuid# -- ) get-cpuid 4scramble pad, pad, pad, pad, ; + +: cpu-name$ ( -- adr len ) + 0pad + h# 8000.0002 cpu-name, + h# 8000.0003 cpu-name, + h# 8000.0004 cpu-name, + pad h# 30 -leading -trailing +; + +: +OLPC ( adr -- adr' ) " OLPC" +smbios$ ; +: setup-smbios ( -- ) + 0 to #smbios-tables + 0 to portinfo# + + smbios-entry smbios-adr h# 1f move + smbios-adr h# 1f + ( adr ) + + bios-info copy-smbios-table ( adr ) + test-name$ +smbios$ + test-version$ +smbios$ +\ +OLPC +\ fw-version$ +smbios$ + fw-date$ +smbios$ + end-smbios-table + + dup >r ( adr r: adr ) + system-info copy-smbios-table ( adr r: adr ) + get-uuid r> 8 + swap move ( adr ) + +OLPC + " XO" +smbios$ + " 1" +smbios$ \ Version + " SN" get-tag$ +smbios$ + end-smbios-table + + base-board-info copy-smbios-table ( adr ) + " QUANTA" +smbios$ + " XO" +smbios$ + " 1.5" +smbios$ \ Version + " SN" get-tag$ +smbios$ + end-smbios-table + + \ XXX might need to amend the security status field + system-enclosure copy-smbios-table ( adr ) + +OLPC + " 1.5" +smbios$ \ Version + end-smbios-table + + dup >r ( adr r: adr ) + processor-info copy-smbios-table ( adr' r: adr ) + 1 get-cpuid nip nip ( adr' eax edx r: adr ) + r@ h# c + l! r> 8 + l! ( adr' ) + cpu-family$ +smbios$ + cpu-name$ +smbios$ + end-smbios-table + + l1-icache-info copy-smbios-table smbios-null end-smbios-table +\ l1-dcache-info copy-smbios-table smbios-null end-smbios-table + l2-cache-info copy-smbios-table smbios-null end-smbios-table + +[ifdef] notdef \ Why bother - XP doesn't collect these + h# 1f h# 1d " Microphone" make-smbios-port + h# 1f h# 1d " Headphone" make-smbios-port + h# 12 h# 10 " USB1" make-smbios-port + h# 12 h# 10 " USB2" make-smbios-port + h# 12 h# 10 " USB3" make-smbios-port + + sd-slot-array copy-smbios-table " SD Slot" +smbios$ end-smbios-table + bios-lang-array copy-smbios-table " enUS" +smbios$ end-smbios-table +[then] + video-array copy-smbios-table " CON" +smbios$ end-smbios-table + + main-memory-array copy-smbios-table smbios-null end-smbios-table + memory-device copy-smbios-table " Soldered" +smbios$ end-smbios-table + ma-mapped-address copy-smbios-table smbios-null end-smbios-table + +\ XP ignores it +\ pointing-device copy-smbios-table smbios-null end-smbios-table + + \ PORTABLE BATTERY (TYPE 22) + +\ XP ignores it +\ system-boot-info copy-smbios-table smbios-null end-smbios-table + + end-array copy-smbios-table smbios-null end-smbios-table ( adr' ) + + \ Fixup the entry structure + smbios-adr h# 1f + tuck - ( tables-adr tables-len ) + smbios-adr h# 16 + w! ( tables-adr ) + smbios-adr h# 18 + l! ( ) + #smbios-tables smbios-adr h# 1c + w! + + smbios-adr h# 1f 4 fix-checksum \ Overall checksum + smbios-adr h# 10 + h# 0f 5 fix-checksum \ Intermediate checksum +; + +stand-init: SMBIOS tables + setup-smbios +; Modified: cpu/x86/pc/olpc/via/versions.fth =================================================================== --- cpu/x86/pc/olpc/via/versions.fth 2009-06-25 21:23:17 UTC (rev 1224) +++ cpu/x86/pc/olpc/via/versions.fth 2009-06-26 16:10:47 UTC (rev 1225) @@ -2,7 +2,7 @@ \ The overall firmware revision macro: FW_MAJOR A -macro: FW_MINOR 03t +macro: FW_MINOR 04 \ The EC microcode macro: EC_VERSION 1_9_1 Modified: ofw/inet/ip.fth =================================================================== --- ofw/inet/ip.fth 2009-06-25 21:23:17 UTC (rev 1224) +++ ofw/inet/ip.fth 2009-06-26 16:10:47 UTC (rev 1225) @@ -76,9 +76,11 @@ then ( 'netmask-c ) ; -\ either h# ffffffff or h# 0 is broadcast ip addr +\ Matches either h# ffffffff or h# 0 or subnet-specific broadcast addr : broadcast-ip-addr? ( adr-buf -- flag ) - dup broadcast-ip-addr ip= swap unknown-ip-addr? or + dup broadcast-ip-addr ip= + swap def-broadcast-ip ip= or + over unknown-ip-addr? or ; : netmask ( -- 'ip )

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r1224 - cpu/x86/pc/olpc/via

by svn＠openfirmware.info

Author: wmb Date: 2009-06-25 23:23:17 +0200 (Thu, 25 Jun 2009) New Revision: 1224 Modified: cpu/x86/pc/olpc/via/dsdt.dsl Log: Typo in dsdt.dsl Modified: cpu/x86/pc/olpc/via/dsdt.dsl =================================================================== --- cpu/x86/pc/olpc/via/dsdt.dsl 2009-06-25 21:15:53 UTC (rev 1223) +++ cpu/x86/pc/olpc/via/dsdt.dsl 2009-06-25 21:23:17 UTC (rev 1224) @@ -383,7 +383,7 @@ CreateDWordField(BUF0,MEM3._MIN, PMRN) CreateDWordField(BUF0,MEM3._MAX, PMRM) CreateDWordField(BUF0,MEM3._LEN, PMRL) - \\ XXX top of PCI memory space + // XXX top of PCI memory space Store(0xFFE80000, PMRM) Store(\_SB.PCI0.MEMC.LTMA, Local0) ShiftLeft(Local0, 16, PMRN)

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r1223 - cpu/x86/pc cpu/x86/pc/olpc/via dev/olpc/dcon dev/via/unichrome

by svn＠openfirmware.info

Author: wmb Date: 2009-06-25 23:15:53 +0200 (Thu, 25 Jun 2009) New Revision: 1223 Modified: cpu/x86/pc/linux.fth cpu/x86/pc/olpc/via/addrs.fth cpu/x86/pc/olpc/via/config.fth cpu/x86/pc/olpc/via/fw.bth cpu/x86/pc/olpc/via/ioinit.fth cpu/x86/pc/olpc/via/olpc.bth cpu/x86/pc/olpc/via/resume.bth cpu/x86/pc/olpc/via/romreset.bth cpu/x86/pc/olpc/via/suspend.fth cpu/x86/pc/olpc/via/versions.fth dev/olpc/dcon/viadcon.fth dev/via/unichrome/unichrome.fth Log: Via checkpoint - suspend/resume works, ACPI starting to get there Modified: cpu/x86/pc/linux.fth =================================================================== --- cpu/x86/pc/linux.fth 2009-06-25 21:13:27 UTC (rev 1222) +++ cpu/x86/pc/linux.fth 2009-06-25 21:15:53 UTC (rev 1223) @@ -146,7 +146,7 @@ ; \ If we are running in physical address mode, make a page directory -\ that will map up when the kernel turns on paging. +\ that will map us when the kernel turns on paging. [ifdef] fw-map-limit : v=p-pde ( adr -- ) dup h# 83 or cr3@ rot d# 22 rshift la+ l! Modified: cpu/x86/pc/olpc/via/addrs.fth =================================================================== --- cpu/x86/pc/olpc/via/addrs.fth 2009-06-25 21:13:27 UTC (rev 1222) +++ cpu/x86/pc/olpc/via/addrs.fth 2009-06-25 21:15:53 UTC (rev 1223) @@ -50,24 +50,27 @@ h# d000.0000 constant fb-pci-base h# f000.0000 constant gfx-pci-base -h# fe01.a000 constant ohci-pci-base -h# fe01.b000 constant ehci-pci-base -h# fe02.4000 constant sd-pci-base -h# fe02.8000 constant camera-pci-base -h# fec0.0000 constant io-apic-mmio-base +\ h# fe01.a000 constant ohci-pci-base +\ h# fe01.b000 constant ehci-pci-base +\ h# fe02.4000 constant sd-pci-base +\ h# fe02.8000 constant camera-pci-base h# fed0.0000 constant hpet-mmio-base h# fed3.0000 constant spi-mmio-base -h# fed4.0000 constant wdt-mmio-base +\ h# fed4.0000 constant wdt-mmio-base +h# fec0.0000 constant io-apic-mmio-base h# fee0.0000 constant apic-mmio-base h# 400 constant acpi-io-base h# 500 constant smbus-io-base +h# 4080 constant uart-dma-io-base h# e0000 constant rsdp-adr h# e0040 constant rsdt-adr h# e0080 constant fadt-adr h# e0180 constant facs-adr h# e01c0 constant dbgp-adr +h# e0200 constant madt-adr \ MADT is 5a byts long +h# e0280 constant hpet-adr h# fc000 constant dsdt-adr h# fd000 constant ssdt-adr Modified: cpu/x86/pc/olpc/via/config.fth =================================================================== --- cpu/x86/pc/olpc/via/config.fth 2009-06-25 21:13:27 UTC (rev 1222) +++ cpu/x86/pc/olpc/via/config.fth 2009-06-25 21:15:53 UTC (rev 1223) @@ -18,7 +18,7 @@ \ create coreboot-loaded -\ create virtual-mode +create virtual-mode create addresses-assigned \ Define if base addresses are already assigned \ create serial-console \ Define to default to serial port for console create pc Modified: cpu/x86/pc/olpc/via/fw.bth =================================================================== --- cpu/x86/pc/olpc/via/fw.bth 2009-06-25 21:13:27 UTC (rev 1222) +++ cpu/x86/pc/olpc/via/fw.bth 2009-06-25 21:15:53 UTC (rev 1223) @@ -255,11 +255,9 @@ false ; -[ifdef] Later false value secure? : protect-fw ( -- ) secure? if ec-indexed-io-off then ; -[then] \ stand-init-debug? [if] warning @ warning off @@ -271,9 +269,7 @@ disable-interrupts d# 1000 i-key-wait if - [ifdef] Later protect-fw - [then] ." Interacting" cr hex interact then @@ -313,20 +309,21 @@ fload ${BP}/ofw/gui/loadmenu.fth fload ${BP}/ofw/gui/insticon.fth -[ifdef] Later -fload ${BP}/cpu/x86/pc/olpc/disptest.fth -: setup-for-linux ( -- ) - [ ' linux-hook behavior compile, ] \ Chain to old behavior - vpci-devices-on \ Do this after quieting USB -; -' setup-for-linux to linux-hook : screen-#lines ( -- n ) screen-ih 0= if default-#lines exit then screen-ih package( #lines )package ; ' screen-#lines to lines/page +[ifdef] Later +fload ${BP}/cpu/x86/pc/olpc/disptest.fth +: setup-for-linux ( -- ) + [ ' linux-hook behavior compile, ] \ Chain to old behavior + \ whatever +; +' setup-for-linux to linux-hook + fload ${BP}/cpu/x86/pc/olpc/help.fth fload ${BP}/cpu/x86/pc/olpc/gui.fth [then] @@ -347,10 +344,11 @@ boot-getline to boot-file " rom:emacs" $boot ; +fload ${BP}/cpu/x86/pc/olpc/via/acpi.fth + [ifdef] Later fload ${BP}/cpu/x86/pc/rmtools.fth fload ${BP}/dev/geode/smi.fth -fload ${BP}/cpu/x86/pc/olpc/acpi.fth fload ${BP}/cpu/x86/pc/olpc/smbios.fth \ fload ${BP}/cpu/x86/pc/biosload/rmenter.fth fload ${BP}/cpu/x86/pc/biosints.fth @@ -364,11 +362,12 @@ [ifdef] wlan-wackup fload ${BP}/cpu/x86/pc/olpc/wlantest.fth -fload ${BP}/cpu/x86/pc/olpc/rtcwake.fth ' gx-power-off to power-off [then] [then] +fload ${BP}/cpu/x86/pc/olpc/rtcwake.fth + [ifdef] Later [ifdef] use-ega : ega-output ( -- ) @@ -407,10 +406,8 @@ " u:\vmlinuz" to boot-device ; -[ifdef] Later : dimmer ( -- ) screen-ih if " dimmer" screen-ih $call-method then ; : brighter ( -- ) screen-ih if " brighter" screen-ih $call-method then ; -[then] [ifdef] Later dev /8042/keyboard @@ -457,6 +454,9 @@ ec-reboot \ Tell the EC to reboot us, so the EC can reset too [then] + \ Prevent "resume from S3" on restart + 4 acpi-w@ h# 1c00 invert and 4 acpi-w! + 6 h# cf9 pc! \ In case the EC doesn't do it begin halt again ; @@ -577,9 +577,9 @@ ; [then] -[ifdef] Later : console-start ( -- ) " screen" open-dev ?dup if + dup to screen-ih set-stdout \ logo-banner drop \ close-dev @@ -592,7 +592,6 @@ \ ." nvramrc" cr \ use-nvramrc? if nvramrc safe-evaluate then ; -[then] : debug-interact ( -- ) early-interact? if @@ -646,6 +645,7 @@ ?factory-mode ?factory-boot-sequence +[then] console-start @@ -656,8 +656,10 @@ then read-game-keys -[then] + +[ifdef] Later stdout off \ +[then] " probe-" do-drop-in @@ -683,8 +685,8 @@ [then] ['] (interrupt-auto-boot?) to interrupt-auto-boot? ?usb-keyboard - install-console - install-dual-console +\ install-console +\ install-dual-console banner auto-boot @@ -705,13 +707,8 @@ \ " wifi media lab 802.11" eval \ " flash http:\\18.85.46.172\new.rom" eval ; +: urom " flash! u:\new.rom" eval ; -: sci-wakeup ( -- ) ; -\ : acpi-l@ ( index -- l ) drop 0 ; -\ : acpi-l! ( l index -- ) 2drop ; -: s3 ( -- ) ; - - [ifdef] use-ec-Later \ Fancy battery charge logger. fload ${BP}/cpu/x86/pc/olpc/charge.fth Modified: cpu/x86/pc/olpc/via/ioinit.fth =================================================================== --- cpu/x86/pc/olpc/via/ioinit.fth 2009-06-25 21:13:27 UTC (rev 1222) +++ cpu/x86/pc/olpc/via/ioinit.fth 2009-06-25 21:15:53 UTC (rev 1223) @@ -182,9 +182,12 @@ 5b 53 53 mreg \ Enable APIC Clock Gating - 43 res be like Phx [then] 68 80 80 mreg \ Enable HPETs - 69 ff 00 mreg \ HPET base low - 6a ff d0 mreg \ HPET base mid - 6b ff fe mreg \ HPET base high + +hpet-mmio-base lbsplit swap 2swap swap drop ( bits31:24 bits23:16 bits15:8 ) + 69 ff rot mreg \ HPET base low + 6a ff rot mreg \ HPET base mid + 6b ff rot mreg \ HPET base high + 6e ff 18 mreg \ COMB not pos decoded but otherwise set to 2f8, COMA pos decoded at 3f8 70 ff 06 mreg \ SVID backdoor 71 ff 11 mreg \ SVID backdoor @@ -193,6 +196,7 @@ 80 20 20 mreg \ Debounce power button 81 08 08 mreg \ 32-bit ACPI timer \ 81 08 00 mreg \ 24-bit ACPI timer - why? + 82 0f 0a mreg \ Direct SCI to IRQ 10 (0xa) 84 ff da mreg \ IRQs 7,6,4,3,1 are primary wakeups 85 ff 40 mreg \ IRQ 14 is primary wakeup 8a 9f 1f mreg \ C-state auto switching with normal latencies @@ -226,14 +230,19 @@ b4 80 00 mreg \ No positive decoding for UART1 ??? b7 40 40 mreg \ 40 res be like Phx - b8 fc 80 mreg \ UART DMA Control Registers Base low (port is 4080) - b9 ff 40 mreg \ UART DMA Control Registers Base high +uart-dma-io-base wbsplit swap ( bits15:8 bits7:0 ) + b8 fc rot mreg \ UART DMA Control Registers Base low (port is 4080) + b9 ff rot mreg \ UART DMA Control Registers Base high ba 77 44 mreg \ COM1 DMA Channel Selects - DMA0 for both Transmit and Receive - bc ff 00 mreg \ SPI MMIO Base Address 15:8 (address is fed30000) - bd ff d3 mreg \ SPI MMIO Base Address 23:16 - be ff fe mreg \ SPI MMIO Base Address 31:24 - d0 f0 00 mreg \ SMBUS IO Base Address low (port is 0500) - d1 ff 05 mreg \ SMBUS IO Base Address high + +spi-mmio-base lbsplit swap 2swap swap drop ( bits31:24 bits23:16 bits15:8 ) + bc ff rot mreg \ SPI MMIO Base Address 15:8 (address is fed30000) + bd ff rot mreg \ SPI MMIO Base Address 23:16 + be ff rot mreg \ SPI MMIO Base Address 31:24 + +smbus-io-base wbsplit swap ( bits15:8 bits7:0 ) + d0 f0 rot mreg \ SMBUS IO Base Address low (port is 0500) + d1 ff rot mreg \ SMBUS IO Base Address high d2 0f 01 mreg \ Enable SMBUS and set other characteristics e2 80 80 mreg \ Inhibit C4 during USB isochronous transaction [ifdef] demo-board @@ -241,7 +250,7 @@ [then] [ifdef] xo-board e3 04 04 mreg \ Select GPIO8 (DCONBLNK) instead of SSPICLK - e4 ff c8 mreg \ Enable short C3/C4 (80), select GPO10 (10) (USB_PWR_EN), GPO10/11 (08) + e4 ff c8 mreg \ Enable short C3/C4 (80), select GPO10 (40) (USB_PWR_EN), GPI10/11 (08) [then] e5 60 60 mreg \ Enable NM bus master as source of bus master status, enable NB int to wakeup from Cx e6 20 20 mreg \ Enable USB Device Mode Bus Master as Break Event @@ -258,9 +267,11 @@ 0 [if] 61 ff 2a mreg \ Page C ROM shadow - C0000-CBFFF RO, CC000-CFFFF off 62 ff 00 mreg \ Page D ROM shadow - D0000-DFFFF off - 63 f3 a0 mreg \ Page E/F ROM shadow - E0000-EFFFF RO, F0000-FFFFF RO, no memory hole - 64 ff aa mreg \ Page E ROM shadow - E0000-EFFFF RO +\ 63 f3 a0 mreg \ Page E/F ROM shadow - E0000-EFFFF RO, F0000-FFFFF RO, no memory hole +\ 64 ff aa mreg \ Page E ROM shadow - E0000-EFFFF RW [then] + 63 fc f0 mreg \ Page E/F ROM shadow - E0000-EFFFF RW, F0000-FFFFF RW, no memory hole + 64 ff ff mreg \ Page E ROM shadow - E0000-EFFFF RW 70 fb 82 mreg \ CPU to PCI flow control - CPU to PCI posted write, Enable Delay Transaction 72 af ee mreg \ Read caching and prefix - various knobs (40 bit is reserved) 73 79 01 mreg \ Enable PCI broken master timer & various knobs @@ -304,3 +315,5 @@ \ x1 to write to SMM shadow memory behind VGA \ 00 to run - Axxxxx hits VGA in normal mode, hits shadow DRAM in SMM \ 01 to access VGA when in SMM (data cycles only) + +acpi-io-base h# 4c + port-rl h# 400 bitset ax dx out \ Set USB power high Modified: cpu/x86/pc/olpc/via/olpc.bth =================================================================== --- cpu/x86/pc/olpc/via/olpc.bth 2009-06-25 21:13:27 UTC (rev 1222) +++ cpu/x86/pc/olpc/via/olpc.bth 2009-06-25 21:15:53 UTC (rev 1223) @@ -27,9 +27,9 @@ in: ${BP}/dev/ide/build/idehier.fc \ in: ${BP}/dev/ide/build/leghier.fc \ in: ${BP}/cpu/x86/pc/olpc/via/build/camera.fc -\ in: ${BP}/cpu/x86/pc/olpc/via/build/dsdt.aml +in: ${BP}/cpu/x86/pc/olpc/via/build/dsdt.aml \ in: ${BP}/cpu/x86/pc/olpc/via/build/mcastnand.bin -\ in: ${BP}/dev/hdaudio/build/hdaudio.fc +in: ${BP}/dev/hdaudio/build/hdaudio.fc in: sd8686.bin @@ -112,8 +112,8 @@ " ${BP}/ofw/fcode/memtest.fth" " memtest.fth" $add-deflated-dropin + " ${BP}/dev/hdaudio/build/hdaudio.fc" " class040300" $add-deflated-dropin [ifdef] Later - " ${BP}/dev/hdaudio/build/hdaudio.fc" " class040300" $add-deflated-dropin " ${BP}/ofw/inet/telnetd.fth" " telnetd" $add-deflated-dropin @@ -154,13 +154,15 @@ " fs.public" " fspubkey" $add-dropin \ Incompressible " lease.public" " leasepubkey" $add-dropin \ Incompressible " developer.public" " develpubkey" $add-dropin \ Incompressible - +[then] " sourceurl" " sourceurl" $add-dropin " ${BP}/cpu/x86/pc/olpc/images/Edge1-8k-EQ-Comp-Amp-Short.wav" " splash" $add-deflated-dropin + " ${BP}/cpu/x86/pc/olpc/via/build/dsdt.aml" " dsdt" $add-deflated-dropin \ " ${BP}/cpu/x86/pc/olpc/via/build/ssdt.aml" " ssdt" $add-deflated-dropin +[ifdef] Later " ${BP}/cpu/x86/pc/olpc/via/build/nandblaster_rx.bin" " nb_rx" $add-deflated-dropin " ${BP}/cpu/x86/pc/olpc/via/build/nandblaster_tx.bin" " nb_tx" $add-deflated-dropin [then] Modified: cpu/x86/pc/olpc/via/resume.bth =================================================================== --- cpu/x86/pc/olpc/via/resume.bth 2009-06-25 21:13:27 UTC (rev 1222) +++ cpu/x86/pc/olpc/via/resume.bth 2009-06-25 21:15:53 UTC (rev 1223) @@ -65,7 +65,7 @@ ax si mov \ Save PDIR VA 0 [si] cx mov forget-msr \ Save old PDIR entry 0 h# 83 # 0 [ax] mov \ Punch a 4M mapping 0->0 into the page directory - cr3 ax mov ax cr3 mov \ Invalide the TLB to activate the mapping + cr3 ax mov ax cr3 mov \ Invalidate the TLB to activate the mapping h# f0060 # ax mov ax jmp \ Jump to suspend-physical, disabling paging h# 60 pad-to @@ -146,28 +146,34 @@ \ This is where the Geode sets up the sleep/wakeup sequence timing +[ifdef] notdef \ Clear existing wakeup status - h# 400 port-rw ax dx out + h# 400 port-rw op: ax dx out +[then] \ notdef \ The caller chooses the wakeup conditions, so we don't do it here - h# ffff h# 420 port-wl \ Clear all status bits + h# ffff h# 420 port-ww \ Clear all status bits h# fe resume-progress wbinvd \ Flush the cache +[ifdef] delete-me \ Setup the register values in advance so the active instruction sequence \ is as short as possible, thus keeping all the activity in one cache line. - h# 0400 h# 404 port-ww \ Setup sleep type +\ h# 0400 h# 404 port-ww \ Setup sleep type +[then] +[ifdef] notdef \ Align to a cache line boundary also forth begin here asm-base - h# 1f and while h# 90 c, repeat \ Align with NOPs previous +[then] h# 2400 h# 404 port-ww \ Go to sleep - h# fff # cx mov begin nop loopa \ Spin in this cache line while going down + h# 1000000 # cx mov begin nop loopa \ Spin in this cache line while going down \ If the processor didn't really go down, perhaps because a wakeup event was \ already pending, proceed as with a wakeup Modified: cpu/x86/pc/olpc/via/romreset.bth =================================================================== --- cpu/x86/pc/olpc/via/romreset.bth 2009-06-25 21:13:27 UTC (rev 1222) +++ cpu/x86/pc/olpc/via/romreset.bth 2009-06-25 21:15:53 UTC (rev 1223) @@ -120,15 +120,10 @@ acpi-io-base 1 + 8888 config-ww \ Set ACPI base address 8c 8881 config-wb \ Enable ACPI regs, 32-bit PM timer, guard RTC against power glitches acpi-io-base 4 + port-rw \ Get APCI Status register - d# 10 # ax shr 7 # ax and 1 # ax cmp = if \ Wakeup from S3 - char r report - resume-data # sp mov - resume-entry # ax mov ax call \ This might return if checksumming fails - char x report - else \ Not a wakeup from S3 + d# 10 # ax shr 7 # ax and 1 # ax cmp <> if \ Wakeup from S3 \ This turns an OS reboot into a real cold start - from coreboot - 380 config-rb ax ax or 0<> if \ C-page shadowing not on yet - 6 cf9 port-wb \ Force a full system reset + h# 380 config-rb ax ax or 0<> if \ C-page shadowing not on yet + 6 h# cf9 port-wb \ Force a full system reset char X report begin hlt again then @@ -165,6 +160,22 @@ \ fload ${BP}/cpu/x86/pc/ramtest.fth fload ${BP}/cpu/x86/pc/olpc/via/startmtrrinit.fth + + fload ${BP}/cpu/x86/pc/olpc/via/ioinit.fth + + acpi-io-base 4 + port-rw \ Get APCI Status register + ax bx mov + d# 10 # ax shr 7 # ax and 1 # ax cmp = if \ Wakeup from S3 + \ Set sleep type field to 0 to prevent looping here if resume fails + bx ax mov h# 1c00 invert # ax and acpi-io-base 4 + # dx mov op: ax dx out + char r report + + resume-data # sp mov + resume-entry # ax mov ax call \ This might return if checksumming fails + char x report + then \ Not a wakeup from S3 + + \ Cache is now setup normally, backed by memory h# 20.0000 # esp mov @@ -173,8 +184,6 @@ \ fload ${BP}/cpu/x86/pc/olpc/via/startgtlinit.fth - fload ${BP}/cpu/x86/pc/olpc/via/ioinit.fth - \ Enable the keyboard controller \ 8851 config-rb 2 # ax or ax bx mov Modified: cpu/x86/pc/olpc/via/suspend.fth =================================================================== --- cpu/x86/pc/olpc/via/suspend.fth 2009-06-25 21:13:27 UTC (rev 1222) +++ cpu/x86/pc/olpc/via/suspend.fth 2009-06-25 21:15:53 UTC (rev 1223) @@ -25,7 +25,8 @@ \ any status bits in the low half of the register. 0 acpi-l@ h# 100.0000 or 0 acpi-l! - h# ffff h# 20 acpi-w! \ Clear PME status bits +\ Unnecessary, as asm code does it +\ h# ffff h# 20 acpi-w! \ Clear PME status bits \ XXX may need to clear other status bits elsewhere as well \ sum-forth @@ -44,9 +45,9 @@ again ; : suspend -\ " video-save" screen-ih $call-method \ Freeze display - s3 -\ " video-restore" screen-ih $call-method \ Unfreeze display + " video-save" screen-ih $call-method \ Freeze display + s3 + " video-restore" screen-ih $call-method \ Unfreeze display \ " /usb@f,5" open-dev ?dup if " do-resume" 2 pick $call-method close-dev then ; alias s suspend Modified: cpu/x86/pc/olpc/via/versions.fth =================================================================== --- cpu/x86/pc/olpc/via/versions.fth 2009-06-25 21:13:27 UTC (rev 1222) +++ cpu/x86/pc/olpc/via/versions.fth 2009-06-25 21:15:53 UTC (rev 1223) @@ -2,7 +2,7 @@ \ The overall firmware revision macro: FW_MAJOR A -macro: FW_MINOR 03m +macro: FW_MINOR 03t \ The EC microcode macro: EC_VERSION 1_9_1 Modified: dev/olpc/dcon/viadcon.fth =================================================================== --- dev/olpc/dcon/viadcon.fth 2009-06-25 21:13:27 UTC (rev 1222) +++ dev/olpc/dcon/viadcon.fth 2009-06-25 21:15:53 UTC (rev 1223) @@ -28,8 +28,13 @@ \ h# 4000 constant DM_DEBUG \ h# 8000 constant DM_SELFTEST -: dcon-load ( -- ) h# 4c acpi-b@ h# 04 or h# 4c acpi-b! ; -: dcon-unload ( -- ) h# 4c acpi-b@ h# 04 invert and h# 4c acpi-b! ; +\ Enable SMBALRT# IRQ as DCON IRQ +: dcon-enable-irq ( -- ) 8 8 smb-reg! ; +\ Disable SMBALRT# IRQ as DCON IRQ; leaving it enabled causes spurious S3 wakeups +: dcon-disable-irq ( -- ) 0 8 smb-reg! ; + +: dcon-load ( -- ) h# 4f acpi-b@ h# 04 or h# 4f acpi-b! ; +: dcon-unload ( -- ) h# 4f acpi-b@ h# 04 invert and h# 4f acpi-b! ; : dcon-blnk? ( -- flag ) h# 4a acpi-b@ 4 and 0<> ; : dcon-stat@ ( -- n ) h# 4b acpi-b@ 3 and ; : dcon-irq? ( -- flag ) 1 smb-reg@ h# 20 and 0<> ; @@ -54,9 +59,11 @@ ; : wait-dcon-mode ( -- ) + dcon-enable-irq d# 100 ms-factor * tsc@ drop + ( end-time ) begin ( end-time ) dcon-irq? if + dcon-disable-irq dcon-stat@ dcon-clr-irq 2 = if \ DCONSTAT=10 drop exit then @@ -64,6 +71,7 @@ dup tsc@ drop - 0< ( end-time reached? ) until ( end-time ) drop + dcon-disable-irq ." Timeout entering DCON mode" cr ; @@ -121,7 +129,26 @@ h# dc02 = ; +: dcon-gpio-init ( -- ) + \ Redundant with code in cpu/x86/pc/olpc/via/ioinit.fth + h# 88e3 config-b@ 4 or h# 88e3 config-b! + h# 88e4 config-b@ h# 48 or h# 88e4 config-b! +; + : dcon-setup ( -- ) + dcon-gpio-init + + 0 dcon@ drop 0 dcon@ drop + +[ifdef] notdef + d# 1200 2 dcon! \ HResolution + d# 1240 3 dcon! \ HTotal + h# 0608 4 dcon! \ HSyncstart (6+900=906), HSyncwidth (8) + d# 900 5 dcon! \ VResolution + d# 912 6 dcon! \ VTotal + h# 0502 7 dcon! \ VSyncstart (5+900=905), VSyncwidth (2) +[then] + \ Switch to OLPC mode h# c040 h# 3a dcon! \ SDRAM Setup/Hold time. Default of e040 fails h# 0000 h# 41 dcon! \ Himax suggested this sequence (0 then 0101) @@ -137,6 +164,18 @@ h# f bright! ; +: video-save + 0 set-source \ Freeze image + olpc-lcd-off +; + +: video-restore + smb-init + dcon-gpio-init + olpc-lcd-mode + 1 set-source \ Unfreeze image +; + 0 [if] dconstat dconblnk or dconirq or constant in-gpios dconload constant out-gpios Modified: dev/via/unichrome/unichrome.fth =================================================================== --- dev/via/unichrome/unichrome.fth 2009-06-25 21:13:27 UTC (rev 1222) +++ dev/via/unichrome/unichrome.fth 2009-06-25 21:15:53 UTC (rev 1223) @@ -77,11 +77,18 @@ 640 w, 480 w, 800 w, 656 w, 752 w, 525 w, 489 w, 523 w, hex 8d 10 05 cf pll, decimal 800 w, 600 w, 1056 w, 840 w, 968 w, 628 w, 600 w, 619 w, hex 70 0c 05 0f pll, decimal 1024 w, 768 w, 1344 w, 1048 w, 1184 w, 806 w, 770 w, 776 w, hex b6 0c 05 cf pll, decimal -\ This clock value doesn't work very well with iga1, but it is good with iga2/lcd -\ 1200 w, 900 w, 1264 w, 1210 w, 1242 w, 912 w, 900 w, 910 w, hex 05 0c a0 cf pll, decimabl + +\ This clock value doesn't work very well with iga1, but it is good with iga2/lcd - 57.273 MHz +\ 1200 w, 900 w, 1264 w, 1210 w, 1242 w, 912 w, 900 w, 910 w, hex 05 0c a0 cf pll, decimal + +\ This supposedly matches the Geode setup - 56.199 MHz (Geode is 56.229) + 1200 w, 900 w, 1240 w, 1208 w, 1216 w, 912 w, 905 w, 910 w, hex 05 0c 9d cf pll, decimal + \ 1200 w, 900 w, 1264 w, 1210 w, 1242 w, 912 w, 900 w, 910 w, hex 9d 8c 85 cf pll, decimal \ 1200 w, 900 w, 1240 w, 1208 w, 1216 w, 912 w, 905 w, 907 w, hex 9d 8c 85 cf pll, decimal - 1200 w, 900 w, 1240 w, 1206 w, 1214 w, 912 w, 905 w, 907 w, hex 05 0c 9f cf pll, decimal + +\ VIA's latest recommendation - 56.916 MHz +\ 1200 w, 900 w, 1240 w, 1206 w, 1214 w, 912 w, 905 w, 907 w, hex 05 0c 9f cf pll, decimal 1280 w, 768 w, 1664 w, 1344 w, 1472 w, 798 w, 770 w, 777 w, hex 6f 08 05 4f pll, decimal 1280 w, 800 w, 1680 w, 1352 w, 1480 w, 831 w, 802 w, 808 w, hex 46 88 83 4f pll, decimal 1280 w, 1024 w, 1688 w, 1328 w, 1440 w, 1066 w, 1024 w, 1027 w, hex 97 08 05 0f pll, decimal @@ -536,6 +543,7 @@ d# 1200 d# 900 set-secondary-mode \ 60 60 9b crt-mask \ Sync polarity - negative + 60 60 78 seq-mask \ Sync polarity - negative 00 07 79 crt-mask \ Disable scaling 00 37 a3 crt-mask \ iga2 from S.L., start addr @@ -551,12 +559,15 @@ 0d fb crt! \ 00 08 h# 6b crt-mask \ Not simultaneous mode - 40 40 16 seq! \ Check what is VIASR - is it really seq! ? - reserved bits, apparently control something about using crt and lcd at the same time + 40 40 16 seq-mask \ reserved bits, apparently control something about using crt and lcd at the same time ; : olpc-crt-off ( -- ) 00 30 1b seq-mask \ IGA1 engine clock off 30 30 36 crt-mask \ DAC off ; +: olpc-lcd-off ( -- ) + 00 c0 1b seq-mask \ IGA2 engine clock off +; hex 0 [if]

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r1222 - cpu/x86/pc/olpc/via

by svn＠openfirmware.info

Author: wmb Date: 2009-06-25 23:13:27 +0200 (Thu, 25 Jun 2009) New Revision: 1222 Added: cpu/x86/pc/olpc/via/acpi.fth cpu/x86/pc/olpc/via/dsdt.dsl cpu/x86/pc/olpc/via/rtcwake.fth Log: Checked in new files Added: cpu/x86/pc/olpc/via/acpi.fth =================================================================== --- cpu/x86/pc/olpc/via/acpi.fth (rev 0) +++ cpu/x86/pc/olpc/via/acpi.fth 2009-06-25 21:13:27 UTC (rev 1222) @@ -0,0 +1,577 @@ +\ Make some ACPI descriptor tables + +h# 0. 2constant xsdt-adr + +create fadt +( 000 4 ) " FACP" $, \ Signature +( 004 4 ) h# 84 l, \ Table Length +( 008 1 ) h# 02 c, \ Revision (supports reset adr) +( 009 1 ) h# 00 c, \ Checksum +( 00A 6 ) " OLPC " $, \ Oem ID +( 010 8 ) " OLPC_000" $, \ Oem Table ID +( 018 4 ) " 0000" $, \ Oem Revision +( 01C 4 ) " OLPC" $, \ Asl Compiler ID +( 020 4 ) " 0000" $, \ Asl Compiler Revision +( 024 4 ) facs-adr l, \ FACS Address +( 028 4 ) dsdt-adr l, \ DSDT Address +( 02C 1 ) h# 00 c, \ Was Model, now reserved +( 02D 1 ) h# 00 c, \ PM Profile +( 02E 2 ) h# 000a w, \ SCI Interrupt + +\ Setting all of these to 0 tells the OS that the system is always in ACPI mode +( 030 4 ) h# 0 l, \ SMI Command Port +( 034 1 ) h# 0 c, \ ACPI Enable Value +( 035 1 ) h# 0 c, \ ACPI Disable Value + +( 036 1 ) h# 00 c, \ S4BIOS Command +( 037 1 ) h# 00 c, \ P-State Control +( 038 4 ) h# 400 l, \ PM1A Event Block Address +( 03C 4 ) h# 0 l, \ PM1B Event Block Address +\ ( 040 4 ) h# 9c28 l, \ PM1A Control Block Address +( 040 4 ) h# 404 l, \ PM1A Control Block Address +( 044 4 ) h# 0 l, \ PM1B Control Block Address +( 048 4 ) h# 0 l, \ PM2 Control Block Address (don't support) +\ ( 04C 4 ) h# 9c10 l, \ PM Timer Block Address +( 04C 4 ) h# 408 l, \ PM Timer Block Address +( 050 4 ) h# 420 l, \ GPE0 Block Address +( 054 4 ) h# 0 l, \ GPE1 Block Address +( 058 1 ) h# 4 c, \ PM1 Event Block Length +( 059 1 ) h# 2 c, \ PM1 Control Block Length +( 05A 1 ) h# 0 c, \ PM2 Control Block Length +( 05B 1 ) h# 4 c, \ PM Timer Block Length +( 05C 1 ) h# 4 c, \ GPE0 Block Length +( 05D 1 ) h# 0 c, \ GPE1 Block Length +( 05E 1 ) h# 10 c, \ GPE1 Base Offset +( 05F 1 ) h# 85 c, \ _CST Support +( 060 2 ) h# 1 w, \ C2 Latency +( 062 2 ) h# 1 w, \ C3 Latency +( 064 2 ) h# 0 w, \ CPU Cache Size +( 066 2 ) h# 0 w, \ Cache Flush Stride +( 068 1 ) h# 0 c, \ Duty Cycle Offset +( 069 1 ) h# 4 c, \ Duty Cycle Width +( 06A 1 ) h# 7d c, \ RTC Day Alarm Index +( 06B 1 ) h# 7e c, \ RTC Month Alarm Index +( 06C 1 ) h# 7f c, \ RTC Century Index +( 06D 2 ) h# 0 w, \ Boot Architecture Flags +( 06F 1 ) h# 0 c, \ Reserved +( 070 4 ) h# 5a5 l, \ Flags - see below for bit definitions +( 074 12 ) 1 c, 8 c, 0 c, 1 c, h# 92. d, \ Reset register - I/O, 8 bits, 0 offset, byte access + +( 080 1 ) h# 1 c, \ Reset value +( 081 3 ) 0 c, 0 c, 0 c, \ Reserved +here fadt - constant /fadt + +\ FADT Flags: +\ WBINVD is operational : 1 +\ WBINVD does not invalidate : 0 +\ All CPUs support C1 : 1 +\ C2 works on MP system : 0 +\ Power button is generic : 0 +\ Sleep button is generic : 1 +\ RTC wakeup not fixed : 0 +\ RTC wakeup/S4 not possible : 1 +\ 32-bit PM Timer : 1 +\ Docking Supported : 0 +\ Reset Register Supported: 1 + +create rsdp +( 00 8 ) " RSD PTR " $, \ Signature +( 08 1 ) 00 c, \ Checksum +( 09 6 ) " OLPC " $, \ Oem Id +( 0f 1 ) 2 c, \ ACPI revision (3.0b) +( 10 4 ) rsdt-adr l, \ RSDT Address + +( 14 4 ) d# 36 l, \ Length for extended version +( 18 8 ) xsdt-adr d, \ XSDT Address +( 20 1 ) 0 c, \ extended checksum +( 21 3 ) 0 c, 0 c, 0 c, \ reserved +here rsdp - constant /rsdp + +create madt \ Multiple APIC Descriptor Table +( 000 4 ) " APIC" $, \ Signature +( 004 4 ) h# 5a l, \ Table Length +( 008 1 ) h# 01 c, \ Revision +( 009 1 ) h# 00 c, \ Checksum +( 00A 6 ) " OLPC " $, \ Oem ID +( 010 8 ) " OLPC_000" $, \ Oem Table ID +( 018 4 ) " 0000" $, \ Oem Revision +( 01C 4 ) " OLPC" $, \ Asl Compiler ID +( 020 4 ) " 0000" $, \ Asl Compiler Revision +( 024 4 ) apic-mmio-base l, \ APIC base address +( 028 4 ) 1 l, \ Flags - 1 means that an 8259 PIC is present too + +( 02c 1 ) 0 c, \ Processor-local APIC +( 02d 1 ) 8 c, \ length +( 02e 1 ) 0 c, \ processor ID +( 02f 1 ) 0 c, \ ACPI ID +( 030 4 ) 1 l, \ Flags - 1 means this processor is usable + + +( 034 1 ) 1 c, \ I/O APIC +( 035 1 ) d# 12 c, \ length +( 036 1 ) 1 c, \ I/O APIC ID +( 037 1 ) 0 c, \ reserved +( 038 4 ) io-apic-mmio-base l, \ I/O APIC base address +( 03c 4 ) 0 l, \ Global system interrupt base + +( 040 1 ) 4 c, \ local APIC NMI +( 041 1 ) 6 c, \ length +( 042 1 ) 0 c, \ processor ID +( 043 2 ) 5 w, \ flags - edge-triggered, active high +( 045 1 ) 1 c, \ Local APIC LINT# + +( 046 1 ) 2 c, \ Int src override (for PIT timer) +( 047 1 ) d# 10 c, \ length +( 048 1 ) 0 c, \ Bus - ISA +( 049 1 ) 0 c, \ Bus-relative IRQ +( 04a 4 ) 2 l, \ Interrupt # that this source will trigger +( 04e 2 ) 5 w, \ flags - edge-triggered, active high + +( 050 1 ) 2 c, \ Int src override +( 051 1 ) d# 10 c, \ length +( 052 1 ) 0 c, \ Bus - ISA +( 053 1 ) 9 c, \ Bus-relative IRQ +( 054 4 ) 9 l, \ Interrupt # that this source will trigger +( 058 2 ) h# f w, \ Flags - active low, level triggered +here madt - constant /madt + +create hpet \ High Precision Event Timer table +( 000 4 ) " HPET" $, \ Signature +( 004 4 ) h# 38 l, \ Table Length +( 008 1 ) h# 01 c, \ Revision +( 009 1 ) h# 00 c, \ Checksum +( 00A 6 ) " OLPC " $, \ Oem ID +( 010 8 ) " OLPC_000" $, \ Oem Table ID +( 018 4 ) " 0000" $, \ Oem Revision +( 01C 4 ) " OLPC" $, \ Asl Compiler ID +( 020 4 ) " 0000" $, \ Asl Compiler Revision + +( 024 4 ) h# 11068201 l, \ Hardware ID of event timer block - 1106 is PCI VID, rest are misc, see HPET spec +( 028 1 ) 0 c, \ ID +( 029 1 ) 0 c, \ Bit width +( 02a 1 ) 0 c, \ Bit offset +( 02b 1 ) 0 c, \ Access width +( 02c 8 ) hpet-mmio-base d, \ HPET base address +( 034 1 ) 0 c, \ Sequence +( 035 2 ) 0 w, \ Min tick +( 037 1 ) 0 c, \ flags +here hpet - constant /hpet + +create rsdt +( 00 4 ) " RSDT" $, \ Signature +( 04 4 ) h# 34 l, \ Length +\ ( 04 4 ) h# 30 l, \ Length +\ ( 04 4 ) h# 2c l, \ Length +( 08 1 ) 1 c, \ Revision +( 09 1 ) 00 c, \ Checksum +( 0a 6 ) " OLPC " $, \ Oem Id +( 10 8 ) " OLPC_000" $, \ Oem Table Id +( 18 4 ) " 0000" $, \ Oem revision +( 1c 4 ) " OLPC" $, \ Creator ID +( 20 4 ) " 0000" $, \ Creator revision +( 24 4 ) fadt-adr l, \ FADT Address +( 28 4 ) dsdt-adr l, \ DSDT Address +( 2c 4 ) madt-adr l, \ MADT Address +( 30 4 ) hpet-adr l, \ HPET Address +\ ( 2c 4 ) dbgp-adr l, \ DBGP Address +\ ( 30 4 ) ssdt-adr l, \ SSDT Address +\ ( 30 4 ) prtn-adr l, \ PRTN Address +here rsdt - constant /rsdt + +0 [if] +create dbgp +( 00 4 ) " DBGP" $, \ Signature +( 04 4 ) d# 52 l, \ Length +( 08 1 ) 1 c, \ Revision +( 09 1 ) 00 c, \ Checksum +( 0a 6 ) " OLPC " $, \ Oem Id +( 10 8 ) " OLPC_000" $, \ Oem Table Id +( 18 4 ) " 0000" $, \ Oem revision +( 1c 4 ) " OLPC" $, \ Creator ID +( 20 4 ) " 0000" $, \ Creator revision +( 24 1 ) 0 c, \ Full 16550 interface +( 25 3 ) 0 c, 0 c, 0 c, \ reserved +( 28 c ) 1 c, 8 c, 0 c, 1 c, h# 3f8 l, 0 l, \ Port base address (generic register descriptor) +here dbgp - constant /dbgp +[then] + +create facs +( 00 4 ) " FACS" $, \ Signature +( 04 4 ) h# 40 l, \ Length +( 08 4 ) h# 1234 l, \ Hardware signature +( 0c 4 ) 0 l, \ Waking vector +( 10 4 ) 0 l, \ Global lock +( 14 4 ) 0 l, \ Flags +( 18 8 ) 0. d, \ 64-bit waking vector +( 20 1 ) 1 c, \ Version +( 21 1f ) here d# 31 dup allot erase +here facs - constant /facs + +: fix-checksum ( table /table checksum-offset -- ) + >r over >r ( table /table r: cksum-offset table ) + 0 -rot bounds ?do i c@ + loop ( sum ) + negate h# ff and r> r> + c! +; + +: memory-limit ( -- limit ) + " /memory" find-package 0= abort" No /memory node" ( phandle ) + " available" rot get-package-property abort" No available property" ( $ ) + -1 >r ( $ ) ( r: limit ) + begin dup 0> while ( $ ) + decode-int >r decode-int r> + ( $ piece-end ) + dup 1meg u<= if drop else ( $ piece-end ) + r> umin >r ( $ ) ( r: limit' ) + then ( $ ) + repeat ( $ ) + 2drop r> ( limit ) + h# 1000 - \ Safety page +; + +: setup-acpi ( -- ) +[ifdef] notdef + \ This has to agree with the _SB's _INI method, which gets the memory size + \ from offset h# 180 in the EBDA + memory-limit d# 10 rshift 'ebda h# 180 + l! +[then] + + \ Copy rsdt and fadt to low memory + rsdp rsdp-adr /rsdp move rsdp-adr h# 14 8 fix-checksum rsdp-adr /rsdp h# 20 fix-checksum + rsdt rsdt-adr /rsdt move rsdt-adr /rsdt 9 fix-checksum + fadt fadt-adr /fadt move fadt-adr /fadt 9 fix-checksum + madt madt-adr /madt move madt-adr /madt 9 fix-checksum + hpet hpet-adr /hpet move hpet-adr /hpet 9 fix-checksum +\ dbgp dbgp-adr /dbgp move dbgp-adr /dbgp 9 fix-checksum + facs facs-adr /facs move + + \ Copy in the DSDT + \ I suppose we could point to it in FLASH - if so don't compress it, + \ and fixup the address in the fadt and rechecksum the fadt + " dsdt" find-drop-in 0= abort" No DSDT " ( adr len ) + 2dup dsdt-adr swap move free-mem + +[ifdef] notdef + \ Copy in the SSDT + \ I suppose we could point to it in FLASH - if so don't compress it, + \ and fixup the address in the fadt and rechecksum the fadt + " ssdt" find-drop-in 0= abort" No SSDT " ( adr len ) + 2dup ssdt-adr swap move free-mem +[then] + + 4 acpi-w@ 1 or 4 acpi-w! \ Set SCI_EN bit + h# ffffffff h# 20 acpi-l! \ Ack all leftover events +; + +.( Not setting up ACPI automatically) cr +stand-init: ACPI tables +." Not setting up ACPI automatically" cr +\ setup-acpi +; + +\ Geode h# 6000 constant xp-smbus-base + +defer more-platform-fixup ' noop to more-platform-fixup +: rm-platform-fixup ( -- ) +[ifdef] Later +Geode xp-smbus-base h# f001 h# 5140.000b 3dup msr! find-msr-entry 2! +Geode xp-smbus-base 1+ h# 10 isa-hdr >hdr-value l! + + begin sci-queue@ 0= until \ Clean out the SCI queue + h# 20 acpi-w@ h# 20 acpi-w! \ Ack outstanding events +Geode h# 4e sci-mask! \ Include in the mask only events we care about + +Geode 0 h# 40 pm! \ Restore long delay for power-off button +[then] + more-platform-fixup +; + +0 [if] +===== +APIC @ 0x3beb6f32 + 0000: 41 50 49 43 5a 00 00 00 01 3c 50 54 4c 54 44 20 APICZ....<PTLTD + 0010: 09 20 41 50 49 43 20 20 00 00 04 06 20 4c 54 50 . APIC .... LTP + 0020: 00 00 00 00 + 00 00 e0 fe address of local apic + 01 00 00 00 flags - 1 means that an ISA PIC is present too + + 00 Processor-local APIC 08 length + 00 processor ID + 00 ACPI ID + 0030: 01 00 00 00 flags - 1 means usable + + 01 I/O APIC 0c length + 01 I/O APIC ID + 00 reserved + + 00 00 c0 fe I/O APIC address MMIO Address + 00 00 00 00 Global system interrupt base + + 0040: 04 local APIC NMI 06 length + 00 processor ID + 05 00 flags - edge-triggered, active high + 01 Local APIC LINT# + + 02 Int src override 0a length + 00 Bus - ISA + 00 Bus-relative IRQ + 02 00 00 00 Interrupt # that this source will trigger + 05 00 flags - edge-triggered, active high + + 0050: 02 Int src override 0a length + 00 Bus - ISA + 09 Bus-relative IRQ + 09 00 00 00 Interrupt # that this source will trigger + 0f 00 Flags - active low, level triggered + +MCFG is for memory-mapped PCI config space - unnecessary for us +MCFG @ 0x3beb6f8c + 0000: 4d 43 46 47 + 4 0000003c len + 8 01 rev + 9 67 csum + a "PTLTD " OEM ID + 0010: " MCFG " OEM Table ID + 0018: 00 00 04 06 OEM revision # + 1c: " LTP" Compiler ID + 0020: 00000000 compiler rev + 24: 00 00 00 00 00 00 00 00 reserved + 2c e0000000 00000000 BaseAddress.64 + 34: 0000 pci segment group # + 36: 00 start bus # + 37: 00 end bus # + 38: 00 00 00 00 res + +HPET @ 0x3beb6fc8 + 0000: 48 50 45 54 + 4: 00000038 length + 8: 01 rev + 9: 38 csum + a: "PTLTD " OEM ID + 0010: "HPETTBL " OEM table ID + 00 00 04 06 OEM revision # + 1c: " LTP" Compiler ID + 0020: 00000001 Compiler revision ID + 24: 01 82 06 11 hardware ID of event timer block + 28: 00 00 00 00 id bit_width bit_offset access_width + 2c: fed00000 00000000 address + 34: 00 0000 00 seq, min tick, flags + +XSDT @ 0x3beb2a81 + 0000: 58 53 44 54 4c 00 00 00 01 a2 50 54 4c 54 44 20 XSDTL.....PTLTD + 0010: 09 20 58 53 44 54 20 20 00 00 04 06 20 4c 54 50 . XSDT .... LTP + 0020: 00 00 00 00 + Pointers: +84 69 eb 3b 00 00 00 00 +78 6a eb 3b 00 00 00 00 +32 6f eb 3b 00 00 00 00 +8c 6f eb 3b 00 00 00 00 +c8 6f eb 3b 00 00 00 00 + +FACP @ 0x3beb6910 + 0000: 46 41 43 50 74 00 00 00 01 f6 56 58 38 35 35 20 FACPt.....VX855 + 0010: 50 54 4c 54 57 20 20 20 00 00 04 06 50 54 4c 5f PTLTW ....PTL_ + 0020: 40 42 0f 00 + c0 7f eb 3b &facs + cd 2a eb 3b &dsdt + 00 00 model, preferred profile + 0a 00 sci_interrupt !!! + 0030: 2f 40 00 00 sci_command port + 34 f0 acpi_enable + 35 f1 acpi_disable + 36 00 s4bios_request value + 37 80 pstate control + 38 00 40 00 00 pm1a event block + 3c 00 00 00 00 pm1b event block + 0040: 04 40 00 00 pm1a control block + 00 00 00 00 pm1b control block + 22 00 00 00 pm2 control block + 08 40 00 00 pm_timer block + 0050: 20 40 00 00 gpe0_block + 00 00 00 00 gpe1_block + 04 pm1 event block len + 02 pm1 control block len + 01 pm2 control block len + 04 pm timer block length + 04 gpe0 block len + 00 gpe1 block len + 10 gpe1 base offset + 85 _cst latency + 0060: 01 00 C2_latency + 01 00 C3_latency + 00 00 CPU cache size + 00 00 cache flus stride + 00 duty cycle offset + 04 duty cycle width + 7d rtc day alarm indes + 7e rtc month alarm index + 32 rtc century index + 00 00 boot architecture flags + 00 reserved + 0070: a5 00 00 00 flags + +RSDT @ 0x3beb2a49 + 0000: 52 53 44 54 38 00 00 00 01 1f 50 54 4c 54 44 20 RSDT8.....PTLTD + 0010: 20 20 52 53 44 54 20 20 00 00 04 06 20 4c 54 50 RSDT .... LTP + 0020: 00 00 00 00 + Pointers + 24 10 69 eb 3b + 78 6a eb 3b + 32 6f eb 3b + 0030: 8c 6f eb 3b + c8 6f eb 3b + +RSD PTR @ 0xf7c70 + 0000: 52 53 44 20 50 54 52 20 9e 50 54 4c 54 44 20 02 RSD PTR .PTLTD . + 0010: 49 2a eb 3b rsdt-adr + 24 00 00 00 len + 81 2a eb 3b 00 00 00 00 xdst-adr + 0020: 0b ext-csum res + 00 00 00 .... + +FACS @ 0x3beb7fc0 + 0000: 46 41 43 53 signature + 40 00 00 00 len + 00 00 00 00 HW signature + 00 00 00 00 waking vector + 0010: 00 00 00 00 global lock + 00 00 00 00 flags + 00 00 00 00 00 00 00 00 64-bit waking vector + 0020: 01 00 00 00 version + 00 00 00 00 00 00 00 00 00 00 00 00 working area + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 working area + +FACP @ 0x3beb6984 (version 3, 244 bytes) + 0000: 46 41 43 50 f4 00 00 00 03 27 56 58 38 35 35 20 FACP.....'VX855 + 0010: 50 54 4c 54 57 20 20 20 00 00 04 06 50 54 4c 5f PTLTW ....PTL_ + 0020: 40 42 0f 00 + c0 7f eb 3b facs-adr + cd 2a eb 3b dsdt-adr + 00 res + 00 pm-profile + 0a 00 sci-interrupt + 0030: 2f 40 00 00 + f0 + f1 + 00 + 80 + 00 40 00 00 + 00 00 00 00 /@.......@...... + 0040: 04 40 00 00 + 00 00 00 00 + 22 00 00 00 + 08 40 00 00 + 0050: 20 40 00 00 + 00 00 00 00 + 04 + 02 + 01 + 04 + 04 + 00 + 10 + 85 + 0060: 01 00 + 01 00 + 00 00 + 00 00 + 00 + 04 + 7d + 7e + 32 + 00 00 + 00 + 0070: a5 00 00 00 + + 00 00 00 00 00 00 00 00 00 00 00 00 reset register + 0080: 00 reset value + 00 00 00 res + c0 7f eb 3b 00 00 00 00 facs-adr-64 + cd 2a eb 3b 00 00 00 00 dsdt-adr-64 + 94: 01 20 00 00 00 40 00 00 00 00 00 00 pm1a-event-reg-block + 00a0: 00 00 00 00 00 00 00 00 00 00 00 00 pm1b-event-reg-block + 01 10 00 00 04 40 00 00 00 00 00 00 pm1a-cnt-block + b8: 00 00 00 00 00 00 00 00 00 00 00 00 pm1b-cnt-block + 01 08 00 00 22 00 00 00 00 00 00 00 pm2-cnt-block + 00d0: 01 20 00 00 08 40 00 00 00 00 00 00 pm_tmr_block + 01 20 00 00 20 40 00 00 00 00 00 00 gpe0-block + 00 00 00 00 00 00 00 00 00 00 00 00 gpe1-block + +SSDT @ 0x3beb6a78 + 0000: 53 53 44 54 ba 04 00 00 01 3c 50 50 6d 6d 52 65 SSDT.....<PPmmRe + 0010: 50 50 6d 00 00 00 00 00 00 00 04 06 49 4e 54 4c PPm.........INTL + 0020: 24 02 03 20 10 45 49 5c 2e 5f 50 52 5f 43 50 55 $.. .EI\._PR_CPU + 0030: 30 08 50 44 43 54 0a 00 08 50 44 43 52 0a 01 08 0.PDCT...PDCR... + 0040: 50 44 43 4d 0a 01 14 4c 06 5f 50 44 43 01 70 87 PDCM...L._PDC.p. + 0050: 68 60 08 50 44 43 42 11 03 0a 14 70 68 50 44 43 h`.PDCB....phPDC + 0060: 42 8a 50 44 43 42 0a 00 52 45 56 5f 8a 50 44 43 B.PDCB..REV_.PDC + 0070: 42 0a 04 53 49 5a 45 a0 0e 92 93 52 45 56 5f 50 B..SIZE....REV_P + 0080: 44 43 52 a4 0a 00 a0 0b 95 53 49 5a 45 0a 01 a4 DCR......SIZE... + 0090: 0a 00 8a 50 44 43 42 0a 08 44 41 54 30 a0 12 7b ...PDCB..DAT0..{ + 00a0: 44 41 54 30 50 44 43 4d 00 70 0a 01 50 44 43 54 DAT0PDCM.p..PDCT + 00b0: a4 0a 01 08 50 43 54 31 12 2c 02 11 14 0a 11 82 ....PCT1.,...... + 00c0: 0c 00 7f 00 00 00 00 00 00 00 00 00 00 00 79 00 ..............y. + 00d0: 11 14 0a 11 82 0c 00 7f 00 00 00 00 00 00 00 00 ................ + 00e0: 00 00 00 79 00 08 50 43 54 32 12 2c 02 11 14 0a ...y..PCT2.,.... + 00f0: 11 82 0c 00 01 08 00 00 2f 40 00 00 00 00 00 00 ......../@...... + 0100: 79 00 11 14 0a 11 82 0c 00 01 08 00 00 80 00 00 y............... + 0110: 00 00 00 00 00 79 00 08 58 43 54 31 12 2c 02 11 .....y..XCT1.,.. + 0120: 14 0a 11 82 0c 00 7f 40 00 00 99 01 00 00 00 00 .......@........ + 0130: 00 00 79 00 11 14 0a 11 82 0c 00 7f 40 00 00 00 ..y.........@... + 0140: 00 00 00 00 00 00 00 79 00 14 37 5f 50 43 54 00 .......y..7_PCT. + 0150: a0 19 5c 5f 4f 53 49 0d 57 69 6e 64 6f 77 73 20 ..\_OSI.Windows + 0160: 32 30 30 36 00 a4 58 43 54 31 a1 16 a0 0d 93 50 2006..XCT1.....P + 0170: 44 43 54 0a 00 a4 50 43 54 32 a1 06 a4 50 43 54 DCT...PCT2...PCT + 0180: 31 08 58 50 53 53 12 4b 1b 02 12 36 08 0c e8 03 1.XPSS.K...6.... + 0190: 00 00 0c 10 27 00 00 0c 0a 00 00 00 0c 0a 00 00 ....'........... + 01a0: 00 11 07 0a 04 06 0a 00 00 11 07 0a 04 00 00 00 ................ + 01b0: 00 11 07 0a 04 00 00 00 00 11 07 0a 04 06 0a 00 ................ + 01c0: 00 12 36 08 0c 90 01 00 00 0c a0 0f 00 00 0c 0a ..6............. + 01d0: 00 00 00 0c 0a 00 00 00 11 07 0a 04 06 04 00 00 ................ + 01e0: 11 07 0a 04 00 00 00 00 11 07 0a 04 00 00 00 00 ................ + 01f0: 11 07 0a 04 06 04 00 00 12 36 08 0c 90 01 00 00 .........6...... + 0200: 0c a0 0f 00 00 0c 0a 00 00 00 0c 0a 00 00 00 11 ................ + 0210: 07 0a 04 06 04 00 00 11 07 0a 04 00 00 00 00 11 ................ + 0220: 07 0a 04 00 00 00 00 11 07 0a 04 06 04 00 00 12 ................ + 0230: 36 08 0c 90 01 00 00 0c a0 0f 00 00 0c 0a 00 00 6............... + 0240: 00 0c 0a 00 00 00 11 07 0a 04 06 04 00 00 11 07 ................ + 0250: 0a 04 00 00 00 00 11 07 0a 04 00 00 00 00 11 07 ................ + 0260: 0a 04 06 04 00 00 12 36 08 0c 90 01 00 00 0c a0 .......6........ + 0270: 0f 00 00 0c 0a 00 00 00 0c 0a 00 00 00 11 07 0a ................ + 0280: 04 06 04 00 00 11 07 0a 04 00 00 00 00 11 07 0a ................ + 0290: 04 00 00 00 00 11 07 0a 04 06 04 00 00 12 36 08 ..............6. + 02a0: 0c 90 01 00 00 0c a0 0f 00 00 0c 0a 00 00 00 0c ................ + 02b0: 0a 00 00 00 11 07 0a 04 06 04 00 00 11 07 0a 04 ................ + 02c0: 00 00 00 00 11 07 0a 04 00 00 00 00 11 07 0a 04 ................ + 02d0: 06 04 00 00 12 36 08 0c 90 01 00 00 0c a0 0f 00 .....6.......... + 02e0: 00 0c 0a 00 00 00 0c 0a 00 00 00 11 07 0a 04 06 ................ + 02f0: 04 00 00 11 07 0a 04 00 00 00 00 11 07 0a 04 00 ................ + 0300: 00 00 00 11 07 0a 04 06 04 00 00 12 36 08 0c 90 ............6... + 0310: 01 00 00 0c a0 0f 00 00 0c 0a 00 00 00 0c 0a 00 ................ + 0320: 00 00 11 07 0a 04 06 04 00 00 11 07 0a 04 00 00 ................ + 0330: 00 00 11 07 0a 04 00 00 00 00 11 07 0a 04 06 04 ................ + 0340: 00 00 08 50 50 53 31 12 43 0a 02 12 13 06 0b e8 ...PPS1.C....... + 0350: 03 0b 10 27 0b 0a 00 0a 0a 0b 06 0a 0b 06 0a 12 ...'............ + 0360: 13 06 0b 90 01 0b a0 0f 0b 0a 00 0a 0a 0b 06 04 ................ + 0370: 0b 06 04 12 13 06 0b 90 01 0b a0 0f 0b 0a 00 0a ................ + 0380: 0a 0b 06 04 0b 06 04 12 13 06 0b 90 01 0b a0 0f ................ + 0390: 0b 0a 00 0a 0a 0b 06 04 0b 06 04 12 13 06 0b 90 ................ + 03a0: 01 0b a0 0f 0b 0a 00 0a 0a 0b 06 04 0b 06 04 12 ................ + 03b0: 13 06 0b 90 01 0b a0 0f 0b 0a 00 0a 0a 0b 06 04 ................ + 03c0: 0b 06 04 12 13 06 0b 90 01 0b a0 0f 0b 0a 00 0a ................ + 03d0: 0a 0b 06 04 0b 06 04 12 13 06 0b 90 01 0b a0 0f ................ + 03e0: 0b 0a 00 0a 0a 0b 06 04 0b 06 04 08 50 50 53 32 ............PPS2 + 03f0: 12 43 0a 02 12 13 06 0b e8 03 0b 10 27 0b 26 02 .C..........'.&. + 0400: 0a 0a 0b b0 00 0b b0 00 12 13 06 0b 90 01 0b a0 ................ + 0410: 0f 0b bc 02 0a 0a 0b b1 00 0b b1 00 12 13 06 0b ................ + 0420: 90 01 0b a0 0f 0b bc 02 0a 0a 0b b2 00 0b b2 00 ................ + 0430: 12 13 06 0b 90 01 0b a0 0f 0b bc 02 0a 0a 0b b3 ................ + 0440: 00 0b b3 00 12 13 06 0b 90 01 0b a0 0f 0b bc 02 ................ + 0450: 0a 0a 0b b4 00 0b b4 00 12 13 06 0b 90 01 0b a0 ................ + 0460: 0f 0b bc 02 0a 0a 0b b5 00 0b b5 00 12 13 06 0b ................ + 0470: 90 01 0b a0 0f 0b bc 02 0a 0a 0b b6 00 0b b6 00 ................ + 0480: 12 13 06 0b 90 01 0b a0 0f 0b bc 02 0a 0a 0b b7 ................ + 0490: 00 0b b7 00 14 1b 5f 50 53 53 00 a0 0d 93 50 44 ......_PSS....PD + 04a0: 43 54 0a 00 a4 50 50 53 32 a1 06 a4 50 50 53 31 CT...PPS2...PPS1 + 04b0: 14 09 5f 50 50 43 00 a4 0a 00 .._PPC.... +[then] + Added: cpu/x86/pc/olpc/via/dsdt.dsl =================================================================== --- cpu/x86/pc/olpc/via/dsdt.dsl (rev 0) +++ cpu/x86/pc/olpc/via/dsdt.dsl 2009-06-25 21:13:27 UTC (rev 1222) @@ -0,0 +1,2449 @@ +DefinitionBlock ("dsdt.aml", // AML file name + "DSDT", // Table signature, DSDT + 0x01, // Compliance Revision + "OLPC", // OEM ID + "XO-1.5 ", // Table ID + 0x00000001) // OEM Revision +{ + +OperationRegion(CMS1, SystemIO, 0x74, 0x2) +Field(CMS1, ByteAcc, NoLock, Preserve) { + CMSI, 8, + CMSD, 8 +} + +Method (CMSW, 2) +{ + Store (Arg0, CMSI) + Store (Arg1, CMSD) +} + // Processor Objects + Scope(\_PR) { + Processor(\_PR.CPU0,0x00,0x00000410,0x06){} + } + + // System Sleep States + Name(\_S0,Package(){0,0,0,0}) + Name(\_S1,Package(){4,4,4,4}) + Name(\_S3,Package(){1,1,1,1}) + Name(\_S4,Package(){2,2,2,2}) + Name(\_S5,Package(){2,2,2,2}) + + OperationRegion(\DEBG, SystemIO, 0x80, 0x1) + Field(\DEBG, ByteAcc, NoLock, Preserve) { + DBG1, 8, + } + + OperationRegion(\GPST, SystemIO, 0x0420, 0x2) + Field(\GPST, ByteAcc, NoLock, Preserve) { + GS00,1, + GS01,1, + GS02,1, + GS03,1, + GS04,1, + GS05,1, + GS06,1, + GS07,1, + GS08,1, + GS09,1, + GS10,1, + GS11,1, + GS12,1, + GS13,1, + GS14,1, + GS15,1, + } + + OperationRegion(\GPSE, SystemIO, 0x0424, 0x2) // Genernal Purpose SMI Enable + Field(\GPSE, ByteAcc, NoLock, Preserve) { + GPS0, 1, // GPI0 SMI Enable + GPS1, 1, // GPI1 SMI Enable + KBCE, 1, // PS2 KB PME Enable + , 1, + EXTE, 1, // EXT SMI Enable + PME, 1, // PCI PME Enable + , 2, + RING, 1, // Ring Wakeup + , 5, + USBE, 1, // USB Resume + , 1, + } + + OperationRegion(\Glos, SystemIO, 0x0428, 0x2) // Global Status + Field(\Glos, ByteAcc, NoLock, Preserve) { + , 6, // + SSMI, 1, // software SMI + PRII, 1, // primary IRQ + , 2, // + SLPE, 1, // sleep enable(Rx05) + SIRS, 1, // serirq status + , 4, + } + + OperationRegion(\WIRQ, SystemIO, 0x042a, 0x1) // IRQ Resume Reg + Field(\WIRQ, ByteAcc, NoLock, Preserve) { + IRQR, 8, + } + + OperationRegion(\Stus, SystemIO, 0x0430, 0x1) // Global Status + Field(\Stus, ByteAcc, NoLock, Preserve) { + PADS, 8, + } + + OperationRegion(\Prie, SystemIO, 0x0434, 0x1) + Field(\Prie, ByteAcc, NoLock, Preserve) { + , 5, + CMAE, 1, // COMA_EN + CMBE, 1, // COMB_EN + } + + // + // General Purpose Event + // + Scope(\_GPE) + { + Method(_L02) { + Notify(\_SB.PCI0.VT86.PS2K, 0x02) //Internal Keyboard PME Status + } + + Method(_L04) { + Notify(\_SB.SLPB, 0x80) + } + + Method(_L05) { + Notify(\_SB.PCI0,0x2) + } + + Method(_L08) { + Notify(\_SB.PCI0.VT86.EUR1, 0x2) + Notify(\_SB.PCI0.VT86.EUR2, 0x2) + } + + Method(_L09) { + Notify(\_SB.PCI0.VT86.PS2M, 0x02) //Internal Mouse Controller PME Status + } + + Method(_L0D) { + Notify(\_SB.PCI0.HDAC, 0x02) + } + + Method(_L0E) { //USB Wake up Status + Notify(\_SB.PCI0.USB1, 0x02) + Notify(\_SB.PCI0.USB2, 0x02) + Notify(\_SB.PCI0.USB3, 0x02) + Notify(\_SB.PCI0.EHCI, 0x02) + } + } + + Name(PICF,0x00) // PIC or APIC? + Method(_PIC, 0x01, NotSerialized) { + Store (Arg0, PICF) + } + + // + // System Wake up + // + Method(_WAK, 1, Serialized) + { + Notify(\_SB.PCI0.USB1, 0x00) + Notify(\_SB.PCI0.USB2, 0x00) + Notify(\_SB.PCI0.USB3, 0x00) + Notify(\_SB.PCI0.EHCI, 0x00) + + If (LEqual (Arg0, 1)) //S1 + { + Notify (\_SB.SLPB, 0x02) + } + + Or (Arg0, 0xA0, Local0) + Store (Local0, DBG1) //80 Port: A1, A2, A3.... + + IF (LEqual(Arg0, 0x01)) { //S1 + And(IRQR,0x7F,IRQR) //Disable IRQ Resume Reg, IRQR:Rx2A + While(PRII){ //PRII:Rx28[7] + Store (One, PRII) //Clear Primary IRQ resume Status + } + While(LNotEqual(PADS, 0x00)){ //PADS: Rx30[1:7] + Store (PADS, PADS) //Clear Primary Activity Detect Status + } + } + + Notify(\_SB.SLPB, 0x2) + + IF (LEqual(Arg0, 0x03)) //S3 + { + Store(0x2,\_SB.PCI0.MEMC.FSEG) //Set F Segment to Read only + } + + Or (Arg0, 0xB0, Local0) + Store (Local0, DBG1) //80 Port: B1, B2, B3.... + Return (0) + } + + // + // System sleep down + // + Method (_PTS, 1, NotSerialized) + { + + Or (Arg0, 0xF0, Local0) + Store (Local0, DBG1) //80 Port: F1, F2, F3.... + + IF (LEqual(Arg0, 0x01)) { // S1 + While(PRII) + { + Store (One, PRII) //Clear Primary IRQ resume Status + } + While(LNotEqual(PADS, 0x00)) + { + Store (PADS, PADS) //Clear Primary Activity Detect Status + } + Or(IRQR,0x80,IRQR) //Enable IRQ Resume Reg + + } //End of Arg0 EQ 0x01 + + IF (LEqual(Arg0, 0x03)) { //S3 + Store(0x0,\_SB.PCI0.MEMC.FSEG) //Disable F Segment Read/Write + } + + IF (LEqual(Arg0, 0x04)) { //S4 + } + + IF (LEqual(Arg0, 0x05)) { //S5 + Store (Zero, GS04) // Clear EXTSMI# Status, why? + } + sleep(0x64) + Return (0x00) + } + + + Method(STRC, 2) { // Compare two String + If(LNotEqual(Sizeof(Arg0), Sizeof(Arg1))) { + Return(1) + } + + Add(Sizeof(Arg0), 1, Local0) + + Name(BUF0, Buffer(Local0) {}) + Name(BUF1, Buffer(Local0) {}) + + Store(Arg0, BUF0) + Store(Arg1, BUF1) + + While(Local0) { + Decrement(Local0) + If(LNotEqual(Derefof(Index(BUF0, Local0)), Derefof(Index(BUF1, Local0)))) { + Return(1) + } + } + Return(0) // Str1 & Str2 are match + } + + + // + // System Bus + // + Scope(\_SB) + { + + // define Sleeping button as mentioned in ACPI spec 2.0 + Device (SLPB) + { + Name (_HID, EISAID("PNP0C0E")) // Hardware Device ID SLEEPBTN + Method(_STA, 0) { + Return(0x0B) // non-present, enabled, functioning + } + + Name(_PRW, Package(2){0x04,5}) //Internal Keyboard Controller PME Status; S5 + } + +Device(PCI0) +{ + Name(_HID,EISAID ("PNP0A08")) // Indicates PCI Express host bridge hierarchy + Name(_CID,EISAID ("PNP0A03")) // For legacy OS that doesn't understand the new HID + + Name(_ADR,0x00000000) // Device (HI WORD)=0, Func (LO WORD)=0 + + + Name (_BBN,0) + + Method(_INI, 0) + { + } + + Name (_S3D, 3) + + Method(_STA, 0) { + Return(0x0F) // present, enabled, functioning + } + + Name(_PRW, Package(2){0x5,0x4}) // PME# + + Method(_CRS,0) { + Name(BUF0,ResourceTemplate() { + WORDBusNumber( // Bus 0 + ResourceConsumer, + MinNotFixed, + MaxNotFixed, + PosDecode, + 0x0000, + 0x0000, + 0x00FF, + 0x0000, + 0x0100 + ) + + IO( // IO Resource for PCI Bus + Decode16, + 0x0CF8, + 0x0CF8, + 1, + 8 + ) + + WORDIO( // IO from 0x0000 - 0x0cf7 + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0000, + 0x0000, + 0x0CF7, + 0x0000, + 0x0CF8 + ) + + WORDIO( // IO from 0x0d00 - 0xffff + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0000, + 0x0D00, + 0xFFFF, + 0x0000, + 0xF300 + ) + + DWORDMemory( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, + 0x000A0000, + 0x000BFFFF, + 0x00000000, + 0x00020000 + ) + + DWORDMemory( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, + 0x000C0000, + 0x000DFFFF, + 0x00000000, + 0x00020000 + ) +// XXX I don't know what this is + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, + 0xFED40000, + 0xFED44FFF, + 0x00000000, + 0x00005000, + ) + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x80000000, // Min (calculated dynamically) + 0xBfffffff, // Max = 4GB - 1MB (fwh + fwh alias...) + 0x00000000, // Translation + 0x40000000, // Range Length (calculated dynamically) + , // Optional field left blank + , // Optional field left blank + MEM3 // Name declaration for this descriptor + ) + }) // end of BUF0 + + CreateDWordField(BUF0,MEM3._MIN, PMRN) + CreateDWordField(BUF0,MEM3._MAX, PMRM) + CreateDWordField(BUF0,MEM3._LEN, PMRL) + \\ XXX top of PCI memory space + Store(0xFFE80000, PMRM) + Store(\_SB.PCI0.MEMC.LTMA, Local0) + ShiftLeft(Local0, 16, PMRN) + Subtract (PMRM, PMRN, PMRL) + + Return(BUF0) + } // end of CRS + + Device(MEMC) { + Name(_ADR, 0x00000003) + + Method(_STA, 0) { + Return(0x0F) // present, enabled, functioning + } + + OperationRegion(MCPS,PCI_Config,0x00,0x100) + Field(MCPS,ByteAcc,NoLock,Preserve) + { + Offset(0x83), + , 4, + FSEG, 2, //Rx83[4:5] + , 2, + Offset(0x84), + LTMA, 16, //Rx84 and Rx85. Low Top Address of Memory + Offset(0x86), + , 2, + ENTS, 1, //Enable Top SMRAM Size + , 3, + TSMS, 2, // Top SMRAM Size + Offset(0xA1), + , 4, + FBSZ, 3, // Frame Buffer Size + ENIG, 1, // Enable Internal Graphic + } + } + + // USBD Controller + Device (USBD) + { + Name(_ADR, 0x000B0000) + + OperationRegion(RUDC,PCI_Config,0x00,0x100) + Field(RUDC,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + } + + Method(_STA, 0) + { + If(LNotEqual(\_SB.PCI0.USBD.VID, 0x1106)) { + Return(0x00) + }Else { + If(LEqual(\_SB.PCI0.USBD.CMDR, 0x00)) { + Return(0x0D) + }Else{ + Return(0x0F) // present, enabled, functioning + } + } + } + }//Device(USBD) + + // SDIO Controller + Device (SDIO) + { + Name(_ADR, 0x000C0000) + + OperationRegion(RSDC,PCI_Config,0x00,0x100) + Field(RSDC,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + } + + Method(_STA, 0) + { + If(LNotEqual(\_SB.PCI0.SDIO.VID, 0x1106)) { + Return(0x00) + }Else { + If(LEqual(\_SB.PCI0.SDIO.CMDR, 0x00)) { + Return(0x0D) + }Else{ + Return(0x0F) // present, enabled, functioning + } + } + } + }//Device(SDIO) + + // SD $ MS Controller + Device (SDMS) + { + Name(_ADR, 0x000D0000) + + OperationRegion(RSDM,PCI_Config,0x00,0x100) + Field(RSDM,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + } + + Method(_STA, 0) + { + If(LNotEqual(\_SB.PCI0.SDMS.VID, 0x1106)) { + Return(0x00) + }Else { + If(LEqual(\_SB.PCI0.SDMS.CMDR, 0x00)) { + Return(0x0D) + }Else{ + Return(0x0F) // present, enabled, functioning + } + } + } + }//Device(SDMS) + + // CE-ATA $ NF Controller(Card Boot) + Device(CENF) + { + Name(_ADR, 0x000E0000) + + OperationRegion(RENF,PCI_Config,0x00,0x100) + Field(RENF,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + } + + Method(_STA, 0) + { + If(LNotEqual(\_SB.PCI0.CENF.VID, 0x1106)) { + Return(0x00) + }Else { + If(LEqual(\_SB.PCI0.CENF.CMDR, 0x00)) { + Return(0x0D) + }Else{ + Return(0x0F) // present, enabled, functioning + } + } + } + } + +Device(IDEC) +{ + + Name(_ADR, 0x000F0000) //D15F0: a Pata device + + Method(_STA,0,NotSerialized) //Status of the Pata Device + { + If(LNot(LEqual(\_SB.PCI0.IDEC.VID,0x1106))) + { + Return(0x00) //device not exists + } + Else + { + If(LEqual(\_SB.PCI0.IDEC.CMDR,0x00)) + { + Return(0x0D) //device exists & disable + } + Else + { + Return(0x0F) //device exists & enable + } + } + } + OperationRegion(SAPR,PCI_Config,0x00,0xC2) + Field(SAPR,ByteAcc,NoLock,Preserve) + { + VID,16, + Offset(0x04), + CMDR,3, + Offset(0x40), + , 1, + EPCH, 1, // Enable Primary channel. + Offset(0x4A), + PSPT, 8, // IDE Timings, Primary Slave + PMPT, 8, // IDE Timings, Primary Master + Offset(0x52), + PSUT, 4, // Primary Slave UDMA Timing + PSCT, 1, // Primary Drive Slave Cabal Type + PSUE, 3, // Primary Slave UDMA Enable + PMUT, 4, // Primary Master UDMA Timing + PMCT, 1, // Primary Drive Master Cabal Type + PMUE, 3, // Primary Master UDMA Enable + } + + Name(REGF,0x01) //accessible OpRegion default + Method(_REG,2,NotSerialized) // is PCI Config space accessible as OpRegion? + { + If(LEqual(Arg0,0x02)) + { + Store(Arg1,REGF) + } + } + /* + Name(TIM0,Package(0x04){ + Package(){0x78,0xB4,0xF0,0x017F,0x0258}, + Package(){0x20,0x22,0x33,0x47,0x5D}, + Package(){0x78,0x50,0x3C,0x2D,0x1E,0x14,0x0F}, + Package(){0x06,0x05,0x04,0x04,0x03,0x03,0x02,0x02,0x01,0x01,0x01,0x01,0x01,0x01,0x00} + }) +*/ + Name(TIM0, Package() + { // Primary / Secondary channels timings + Package(){120, 180, 240, 383, 600}, // Timings in ns - Mode 4,3,2,1,0 defined from ATA spec. + Package(){0x20, 0x22, 0x33, 0x47, 0x5D }, // PIO Timing - Mode 4,3,2,1,0 + Package(){4, 3, 2, 1, 0}, // PIO mode (TIM0,0) + Package(){2, 1, 0, 0}, // Multi-word DMA mode + Package(){120, 80, 60, 45, 30, 20, 15}, // Min UDMA Timings in ns + Package(){6,5,4,4,3,3,2,2,1,1,1,1,1,1,0}, // UDMA mode + Package(){0x0E, 8, 6, 4, 2, 1, 0}, // UDMA timing + }) + + Name(TMD0,Buffer(0x14){}) + CreateDwordField(TMD0,0x00,PIO0) + CreateDwordField(TMD0,0x04,DMA0) + CreateDwordField(TMD0,0x08,PIO1) + CreateDwordField(TMD0,0x0C,DMA1) + CreateDwordField(TMD0,0x10,CHNF) + + Name(GMPT, 0) // Master PIO Timings + Name(GMUE, 0) // Master UDMA enable + Name(GMUT, 0) // Master UDMA Timings + Name(GSPT, 0) // Slave PIO Timings + Name(GSUE, 0) // Slave UDMA enable + Name(GSUT, 0) // Slave UDMA Timings + + Device(CHN0) //Primary Channel: Pata device + { + Name(_ADR,0x00) + + Method(_STA,0,NotSerialized) + { + If(LNotEqual(\_SB.PCI0.IDEC.EPCH, 0x1)) + { + Return(0x00) //channel disable + } + Else + { + Return(0x0F) //channel enable + } + } + Method(_GTM,0,NotSerialized) //Get Timing Mode + { + Return(GTM(PMPT,PMUE,PMUT,PSPT,PSUE,PSUT)) + } + Method(_STM, 3) // Set Timing PIO/DMA Mode + { + Store(Arg0, TMD0) // Copy Arg0 into TMD0 buffer + Store(PMPT, GMPT) // Master PIO Timings + Store(PMUE, GMUE) // Master UDMA enable + Store(PMUT, GMUT) // Master UDMA Timings + Store(PSPT, GSPT) // Slave PIO Timings + Store(PSUE, GSUE) // Slave UDMA enable + Store(PSUT, GSUT) // Slave UDMA Timings + STM() + Store(GMPT, PMPT) // Master PIO Timings + Store(GMUE, PMUE) // Master UDMA enable + Store(GMUT, PMUT) // Master UDMA Timings + Store(GSPT, PSPT) // Slave PIO Timings + Store(GSUE, PSUE) // Slave UDMA enable + Store(GSUT, PSUT) // Slave UDMA Timings + } // end Method _STM + + Device(DRV0) //Master Device + { + Name(_ADR,0x00) //0 indicates master drive + Method(_GTF,0,NotSerialized) //Get Task File: return a buffer of ATA command used to re-initialize the device + { + Return(GTF(0,PMUE,PMUT,PMPT)) + } + } + Device(DRV1) //Slave Device + { + Name(_ADR,0x01) //1 indicates slave drive + Method(_GTF,0,NotSerialized) //Get Task File: return a buffer of ATA command used to re-initialize the device + { + Return(GTF(0,PSUE,PSUT,PSPT)) + } + } + } + + Method(GTM,6,Serialized) + { + Store(Ones,PIO0) //default value: all bits set to 1 + Store(Ones,PIO1) //default value: all bits set to 1 + Store(Ones,DMA0) //default value: all bits set to 1 + Store(Ones,DMA1) //default value: all bits set to 1 + Store(0x10,CHNF) //default value: 0x10 + If(REGF) + { + } + Else + { + Return(TMD0) //unable to setup PCI config space as opRegion;return default value + } + Store(Match(DeRefOf(Index(TIM0,0x01)),MEQ,Arg0,MTR,0x00,0x00),Local6) + If(LLess(Local6,Ones)) + { + Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x00)),Local6)),Local7) + Store(Local7,DMA0) + Store(Local7,PIO0) + } + Store(Match(DeRefOf(Index(TIM0,0x01)),MEQ,Arg3,MTR,0x00,0x00),Local6) + If(LLess(Local6,Ones)) + { + Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x00)),Local6)),Local7) + Store(Local7,DMA1) + Store(Local7,PIO1) + } + If(Arg1) + { + Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x05)),Arg2)),Local5) + Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x04)),Local5)),DMA0) + Or(CHNF,0x01,CHNF) + } + If(Arg4) + { + Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x05)),Arg5)),Local5) + Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x04)),Local5)),DMA1) + Or(CHNF,0x04,CHNF) + } + Return(TMD0) //return timing mode + } + + + Method(STM, 0, Serialized) + { + + If(REGF){} // PCI space not accessible + Else { Return(TMD0) } + + Store(0x00, GMUE) // Master UDMA Disable + Store(0x00, GSUE) // Slave UDMA Disable + Store(0x07, GMUT) // Master UDMA Mode 0 + Store(0x07, GSUT) // Slave UDMA Mode 0 + + If(And(CHNF, 0x1)) + { + Store(Match(DeRefOf(Index(TIM0, 4)), MLE, DMA0, MTR,0,0), Local0) // Get DMA mode + Store(DeRefOf(Index(DeReFof(Index(TIM0, 6)), Local0)), GMUT) // Timing bit mask 66Mhz + Or(GMUE, 0x07, GMUE) // Enable UltraDMA for Device 0 + } + Else // non - UDMA mode. Possible Multi word DMA + { + If(Or(LEqual(PIO0,Ones), LEqual(PIO0,0))) + { + If(And(LLess(DMA0,Ones), LGreater(DMA0,0))) + { + Store(DMA0, PIO0) // Make PIO0=DMA0 + } + } + } + + If(And(CHNF, 0x4)) + { + Store(Match(DeRefOf(Index(TIM0, 4)), MLE, DMA1, MTR,0,0), Local0) + Store(DeRefOf(Index(DeReFof(Index(TIM0, 6)), Local0)), GSUT) // Timing bit mask 66Mhz + Or(GSUE, 0x07, GSUE) // Enable UltraDMA for Device 0 + } + Else // non - UDMA mode. Possible Multi word DMA + { + If(Or(LEqual(PIO1, Ones), LEqual(PIO1,0))) + { + If(And(LLess(DMA1, Ones), LGreater(DMA1,0))) + { + Store(DMA1, PIO1) // Make PIO1 = DMA1 + } + } + } + + And(Match(DeRefOf(Index(TIM0, 0)), MGE, PIO0, MTR,0,0), 0x3, Local0) + Store(DeRefOf(Index(DeReFof(Index(TIM0, 1)), Local0)), Local1) + Store(Local1, GMPT) + + And(Match(DeRefOf(Index(TIM0, 0)), MGE, PIO1, MTR,0,0), 0x3, Local0) + Store(DeRefOf(Index(DeReFof(Index(TIM0, 1)), Local0)), Local1) + Store(Local1, GSPT) + Return(TMD0) + } // end Method STM + + Method(GTF , 4 , Serialized) + { + Store(Buffer(7){0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF}, Local1) + Store(Buffer(7){0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF}, Local2) + CreateByteField(Local1, 1, Mode) // PIO mode + CreateByteField(Local2, 1, UMOD) // Ultra mode + CreateByteField(Local1, 5, PCHA) // master or slave + CreateByteField(Local2, 5, UCHA) // master or slave + And(Arg0,0x03,Local3) + + If(Lequal(And(Local3,0x01),0x01)) + { + Store(0xB0,PCHA) // drive 1 + Store(0xB0,UCHA) // drive 1 + } + + If(Arg1) + { + Store(DeRefOf(Index(DeReFof(Index(TIM0, 5)), Arg2)), UMOD) //Programming DMA Mode + Or( UMOD, 0x40, UMOD) + } + Else + { // non-UltraDMA + Store(Match(DeRefOf(Index(TIM0, 1)), MEQ, Arg3, MTR,0,0), Local0) + Or(0x20, DeRefOf(Index(DeReFof(Index(TIM0, 3)), Local0)), UMOD) + } + + Store(Match(DeRefOf(Index(TIM0, 1)), MEQ, Arg3, MTR,0,0), Local0) + Or(0x08, DeRefOf(Index(DeReFof(Index(TIM0, 2)), Local0)), Mode) + Concatenate(Local1, Local2, Local6) + Return(Local6) + + } // end of GTF +} + +//---------------------------------------------------------------- +// +// Copyright (c) 2005-2012 VIA Technologies, Inc. +// This program contains proprietary and confidential information. +// All rights reserved except as may be permitted by prior written +// consent. +// +//---------------------------------------------------------------- +//Rev Date Name Description +//---------------------------------------------------------------- + +Device(USB1) { + Name(_ADR,0x00100000) //Address+function. + + Name(_PRW, Package(2){0x0E,3}) + + Name(_S3D, 3) + + OperationRegion(U2F0,PCI_Config,0x00,0xC2) + Field(U2F0,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x3c), + U3IR, 4, //USB1 Interrupt Line + Offset(0x84), + ECDX, 2 //USB1 PM capability status register + } + + Method(_STA,0) { //Status of the USB1 Device + If(LEqual(\_SB.PCI0.USB1.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) + } + } +} + +Device(USB2) { + Name(_ADR,0x00100001) //Address+function. + + Name(_PRW, Package(2){0x0E,3}) + + Name(_S3D, 3) + + OperationRegion(U2F1,PCI_Config,0x00,0xC2) + Field(U2F1,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x3c), + U4IR, 4, //USB2 Interrupt Line + Offset(0x84), + ECDX, 2 //USB2 PM capability status register + } + + Method(_STA,0) { //Status of the USB2 Device + If(LEqual(\_SB.PCI0.USB2.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) + } + } +} + +Device(USB3){ + Name(_ADR,0x00100002) //Address+function. + + Name(_PRW, Package(2){0x0E,3}) + + Name(_S3D, 3) + + OperationRegion(U2F2,PCI_Config,0x00,0xC2) + Field(U2F2,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x3c), + U5IR, 4, //USB3 Interrupt Line + Offset(0x84), + ECDX, 2 //USB3 PM capability status register + } + + Method(_STA,0) { //Status of the USB3 Device + If(LEqual(\_SB.PCI0.USB3.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) + } + } +} + + +Device(EHCI) { + Name(_ADR,0x00100004) //Address+function. + + Name(_PRW, Package(2){0x0E,3}) + + Name(_S3D, 3) + + OperationRegion(U2F4,PCI_Config,0x00,0xC2) + Field(U2F4,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x3c), + U7IR, 4, //EHCI1 Interrupt Line + Offset(0x84), + ECDX, 2 //EHCI1 PM capability status register + } + + Method(_STA,0) { //Status of the EHCI1 Device + If(LEqual(\_SB.PCI0.EHCI.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) + } + } +} + + Device (PEXX) + { + Name (_HID, EISAID ("PNP0C01")) + Method (_STA, 0) + { + Return (0x0F) + } + Name (PXXE, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xE0000000, + 0x10000000, + ) + }) + Method (_CRS, 0) + { + + Return (PXXE) + } + } + +//---------------------------------------------------------------- +// +// Copyright (c) 2005-2012 VIA Technologies, Inc. +// This program contains proprietary and confidential information. +// All rights reserved except as may be permitted by prior written +// consent. +// +//---------------------------------------------------------------- +//Rev Date Name Description +//---------------------------------------------------------------- + + + + + +Device(VT86) { + Name(_ADR,0x00110000) //Address+function. + + + OperationRegion(VTSB, PCI_Config, 0x00, 0x100) + Field(\_SB.PCI0.VT86.VTSB,ByteAcc,NoLock,Preserve) { + Offset(0x2), + DEID, 16, // Device ID + Offset(0x2C), + ID2C,8, // RX2C + ID2D,8, // RX2D + ID2E,8, // RX2E + ID2F,8, // RX2F + Offset(0x44), + PIRE, 4, + PIRF, 4, + PIRG, 4, + PIRH, 4, // PIRQH# Routing + Offset(0x46), + POLE, 1, // INTE polarity + POLF, 1, // INTF polarity + POLG, 1, // INTG polarity + POLH, 1, // INTH polarity + ENR8, 1, // enable INTE~H routing by Rx44~Rx45. + , 1, + ECOM, 1, + Offset(0x4E), + , 3, + EP74, 1, // Enable 74/75 Access CMOS + , 4, + Offset(0x50), + , 1, + ESB3, 1, // RX5001 EHCI1 + ESB2, 1, // RX5002 USB3 + EIDE, 1, // RX5003 EIDE + EUSB, 1, // RX5004 USB1 + ESB1, 1, // RX5005 USB2 + USBD, 1, // RX5006 USB Device Mode controller + Offset(0x51), + EKBC, 1, // RX5100 Internal Keyboard controller + KBCC, 1, // RX5101 Internal KBC Configuration + EPS2, 1, // RX5102 Internal PS2 Mouse + ERTC, 1, // RX5103 Internal RTC + SDIO, 1, // RX5104 enable SDIO controller + , 2, + Offset(0x55), + , 4, + PIRA, 4, // PCI IRQA + PIRB, 4, // PCI IRQB + PIRC, 4, // PCI IRQC + , 4, + PIRD, 4, // PCI IRQD + + Offset(0x58), + , 6, + ESIA, 1, // Enable Source Bridge IO APIC + , 1, + + Offset(0x81), // Enable ACPI I/O + , 7, + ENIO, 1, + Offset(0x88), + , 7, + IOBA, 9, //Power Management I/O Base + + Offset(0x94), + , 5, + PLLD, 1, // RX9405 Internal PLL Reset During Suspend 0:Enable,1:Disable + + Offset(0xB0), + , 4, + EU1E, 1, //Embedded COM1 + EU2E, 1, //Embedded COM2 + , 2, + Offset(0xB2), + UIQ1, 4, // UART1 IRQ + UIQ2, 4, // UART2 IRQ + Offset(0xB4), + U1BA, 7, // UART1 I/O base address. + , 1, + U2BA, 7, // UART2 I/O base address. + , 1, + Offset(0xB7), + , 3, + UDFE, 1, // UART DMA Funtion Enable + Offset(0xB8), + , 2, + DIBA, 14, // UART DMA I/O Base Address + + Offset(0xBC), + SPIB, 24, + Offset(0xD0), + , 4, + SMBA, 12, //SMBus I/O Base (16-byte I/O space) + Offset(0xD2), + ENSM, 1, //Enable SMBus IO + , 7, + Offset(0xF6), + REBD, 8, //Internal Revision ID + } + + Device(APCM) // APIC MMIO + { + Name(_HID, EISAID("PNP0C02")) // Hardware Device ID, Motherboard Resources + Name(_UID, 0x1100) + + Name(CRS, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0xFEE00000, 0x00001000, LAPM) // Local APIC MMIO Space + Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, SIAM) // Sourth Bridge IO APIC MMIO Space + }) + + Method(_CRS, 0) + { + CreateDWordField(CRS, ^SIAM._BAS, BAS1) + CreateDWordField(CRS, ^SIAM._LEN, LEN1) + + + If(LEqual(\_SB.PCI0.VT86.ESIA, 1)) + { + Store(0xFEC00000, BAS1) + Store(0x1000, LEN1) + } + + Return(CRS) + } + + } + + +//---------------------------------------------------------------- +// +// Copyright (c) 2005-2012 VIA Technologies, Inc. +// This program contains proprietary and confidential information. +// All rights reserved except as may be permitted by prior written +// consent. +// +//---------------------------------------------------------------- +//Rev Date Name Description +//---------------------------------------------------------------- + + + + + + + +//---------------------------------------------------------------- +// +// Copyright (c) 2005-2012 VIA Technologies, Inc. +// This program contains proprietary and confidential information. +// All rights reserved except as may be permitted by prior written +// consent. +// +//---------------------------------------------------------------- +//Rev Date Name Description +//---------------------------------------------------------------- + + +Device(PS2M) //PS2 Mouse Device +{ + Name(_HID,EISAID("PNP0F13")) // Hardware Device ID + + Method(_STA,0) //Status of the PS2 Mouse device + { + Return(0x0F) + } + + Method(_CRS,0) + { // Current Resource + Name (BUF1, ResourceTemplate () + { + IRQNoFlags () + {12} + }) + Return(BUF1) + } + + Name(_PRW, Package(){0x09, 0x04}) +} + +Device(PS2K) // PS2 Keyboard Device +{ + Name(_HID,EISAID("PNP0303")) // Hardware Device ID + Name(_CID,EISAID("PNP030B")) // PNP030B is Microsoft reserved + + Method(_STA,0) //Status of the PS2 Keyboard device + { + Return(0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0060, // Address Range Minimum + 0x0060, // Address Range Maximum + 0x01, // Address Alignment + 0x01, // Address Length + ) + IO (Decode16, + 0x0064, // Address Range Minimum + 0x0064, // Address Range Maximum + 0x01, // Address Alignment + 0x01, // Address Length + ) + IRQNoFlags () + {1} + }) + Name(_PRW, Package(){0x02, 0x04}) +} + + +Device(DMAC) +{ + Name(_HID, EISAID("PNP0200")) + + Name(_CRS,ResourceTemplate() { + IO(Decode16, 0x0, 0x0, 0, 0x10) // Master DMA Controller + IO(Decode16, 0x81, 0x81, 0, 0x3) // DMA Page Registers + IO(Decode16, 0x87, 0x87, 0, 0x1) + IO(Decode16, 0x89, 0x89, 0, 0x3) + IO(Decode16, 0x8F, 0x8F, 0, 0x1) + IO(Decode16, 0xC0, 0xC0, 0, 0x20) // Slave DMA Controller + DMA(Compatibility,NotBusMaster,Transfer8) {4} // Channel 4 is used to cascade the two DMA controller. + }) +} + +Device(RTC) +{ + Name(_HID,EISAID("PNP0B00")) + + Name(BUF0,ResourceTemplate() + { + IO(Decode16, 0x70, 0x70, 0x00, 0x02) + IO(Decode16, 0x74, 0x74, 0x00, 0x00, AAAA) + IRQNoFlags() {8} // Active High, Edge Sensitive, Non-sharable + }) + + Method(_CRS,0,Serialized) + { + CreateByteField(BUF0, ^AAAA._LEN, LEN1) + If(LEqual(\_SB.PCI0.VT86.EP74, 0x01)) + { + Store(0x02, LEN1) + } + Return(BUF0) + } +} + +Device(PIC) +{ + Name(_HID,EISAID("PNP0000")) + + Name(_CRS,ResourceTemplate() { + IO(Decode16,0x20,0x20,0x00,0x02) + IO(Decode16,0xA0,0xA0,0x00,0x02) + }) +} + +Device(FPU) +{ + Name(_HID,EISAID("PNP0C04")) + + Name(_CRS,ResourceTemplate() { + IO(Decode16,0xF0,0xF0,0x00,0x1) + IRQNoFlags(){13} + }) +} + +Device(TMR) +{ + Name(_HID,EISAID("PNP0100")) + + Name(BUF0, ResourceTemplate() + { + IO(Decode16,0x40,0x40,0x00,0x04) + IRQNoFlags() {0} + }) + + Method(_CRS, 0, Serialized) + { + Return(BUF0) + } +} + +Device(SPKR) // System Speaker +{ + Name(_HID,EISAID("PNP0800")) + + Name(_CRS,ResourceTemplate() { + IO(Decode16,0x61,0x61,0x01,0x01) + }) +} + + + + + +//---------------------------------------------------------------- +// +// Copyright (c) 2005-2012 VIA Technologies, Inc. +// This program contains proprietary and confidential information. +// All rights reserved except as may be permitted by prior written +// consent. +// +//---------------------------------------------------------------- +//Rev Date Name Description +//---------------------------------------------------------------- + + + + + + +Name (ICRS, ResourceTemplate () +{ + IRQ (Level, ActiveLow, Shared) // The flags is the value of Byte 3 of IRQ Description Definition + { } // The value decides the value of Byte 1 and byte 2 of IRQ Description Definition +}) + +Name(PRSA, ResourceTemplate() +{ + IRQ(Level, ActiveLow, Shared) + {3, 4, 5, 6, 7, 10, 11, 12, 14, 15} +}) +Alias(PRSA, PRSB) +Alias(PRSA, PRSC) +Alias(PRSA, PRSD) +Alias(PRSA, PRSE) +Alias(PRSA, PRSF) +Alias(PRSA, PRSG) +Alias(PRSA, PRSH) + +Device(LNKA) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 1) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRA, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSA) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRA) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRA, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRA) + } +} + + +Device(LNKB) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 2) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRB, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSB) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRB) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRB, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRB) + } +} + + +Device(LNKC) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 3) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRC, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSC) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRC) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRC, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRC) + } +} + +Device(LNKD) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 4) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRD, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSD) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRD) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRD, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRD) + } +} +Device(LNKE) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 5) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRE, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSE) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRE) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRE, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRE) + Store(One,ENR8) + Store(Zero,POLE) + } +} +Device(LNKF) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 6) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRF, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSF) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRF) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRF, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRF) + Store(One,ENR8) + Store(Zero,POLF) + } +} +Device(LNK0) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 7) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRG, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSG) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRG) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRG, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRG) + Store(One,ENR8) + Store(Zero,POLG) + } +} +Device(LNK1) +{ + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 8) + Method(_STA, 0) + { + If(LEqual(\_SB.PCI0.VT86.PIRH, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSH) + } + + Method(_DIS) + { + Store(0x0, \_SB.PCI0.VT86.PIRH) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, \_SB.PCI0.VT86.PIRH, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, \_SB.PCI0.VT86.PIRH) + Store(One,ENR8) + Store(Zero,POLH) + } +} + +// +// Embedded UART1 +// +Device(EUR1) // Communication Device (Modem Port) +{ + Name(_HID, EISAID("PNP0501")) // PnP Device ID 16550 Type + Name(_UID, 0x1) + + Name(_PRW, Package(){8, 4}) + + Method(_PSW, 1) + { + Store(0x20, PADS) // clear _STS first //PMIO Rx30[5] + And(IRQR,0xFE,IRQR) // don not issue SMI //PMIO Rx2A[0] + + If (Arg0) + { + Store(One, CMAE) + } + Else + { + Store(Zero, CMAE) + } + } + + Method(_STA) // Status of the COM device + { + Store(0x00, Local0) + + If(LNotEqual(\_SB.PCI0.VT86.ECOM, Zero)) + { + If(\_SB.PCI0.VT86.EU1E) + { + Store(0x0F, Local0) + } + Else + { // if base address is not equal to zero. + If(LNotEqual(\_SB.PCI0.VT86.U1BA, Zero)) + { + Store(0x0D, Local0) + } + } + } + Return(Local0) + } + + Method(_DIS,0) + { + Store(Zero, \_SB.PCI0.VT86.EU1E) // disable embedded COM A. + } + + Name(RSRC,ResourceTemplate (){ + IO(Decode16,0x0,0x0,0x08,0x08) + IRQNoFlags() {} + }) + + Method(_CRS, 0) + { + And(_STA(), 0x04, Local0) // If the device is disabled, return the blank template. + If(LEqual(Local0,Zero)) // + { // + Return(RSRC) // + } // + + Name(BUF1,ResourceTemplate() { // This is the buffer prepared for OS. + IO(Decode16,0x3F8,0x3F8,0x08,0x08) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQNoFlags(){4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + }) + + CreateByteField(BUF1, 0x02, IOLO) // IO Port MIN Low + CreateByteField(BUF1, 0x03, IOHI) // IO Port MIN High + CreateByteField(BUF1, 0x04, IORL) // IO Port MAX Low + CreateByteField(BUF1, 0x05, IORH) // IO Port MAX High + + if(LNotEqual(\_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + CreateByteField(BUF1, 0x0A, DILO) // DMA IO Port MIN Low + CreateByteField(BUF1, 0x0B, DIHI) // DMA IO Port MIN High + CreateByteField(BUF1, 0x0C, DIRL) // DMA IO Port MAX Low + CreateByteField(BUF1, 0x0D, DIRH) // DMA IO Port MAX High + } + + CreateWordField(BUF1, 0x11, IRQV) // IRQ mask + + ShiftLeft(\_SB.PCI0.VT86.U1BA, 0x03, local0) // IO low. AD7~AD0 + ShiftRight(\_SB.PCI0.VT86.U1BA, 0x05, local1) // IO high. AD9~AD8 + + Store(local0, IOLO) + Store(local1, IOHI) + Store(local0, IORL) + Store(local1, IORH) + + Store(0x00, IRQV) // reset IRQ resource. + If(LNotEqual(\_SB.PCI0.VT86.UIQ1, 0x00)) + { // put assigned IRQ to return buffer if there is any. + ShiftLeft(One, \_SB.PCI0.VT86.UIQ1, IRQV) + } + + if(LNotEqual(\_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + ShiftLeft(\_SB.PCI0.VT86.DIBA, 0x02, local0) // IO low. AD7~AD0 + ShiftRight(\_SB.PCI0.VT86.DIBA, 0x06, local1) // IO high. AD16~AD8 + + Store(local0, DILO) + Store(local1, DIHI) + Store(local0, DIRL) + Store(local1, DIRH) + } + Return(BUF1) + + } // _CRS + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,0) + { + IO(Decode16,0x3F8,0x3F8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFnNoPri() + { + IO(Decode16,0x2F8,0x2F8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFnNoPri() + { + IO(Decode16,0x3E8,0x3E8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFnNoPri() + { + IO(Decode16,0x2E8,0x2E8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFn(2,2) + { + IO(Decode16,0x3F8,0x3F8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFn(2,2) + { + IO(Decode16,0x2F8,0x2F8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFn(2,2) + { + IO(Decode16,0x3E8,0x3E8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFn(2,2) + { + IO(Decode16,0x2E8,0x2E8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + EndDependentFn() + })// _PRS + + Method(_SRS, 1) + { + // + // The Arg0 format is the same as _PRS, and _CRS. + // + CreateByteField (Arg0, 0x02, IOLO) // IO Port Low + CreateByteField (Arg0, 0x03, IOHI) // IO Port High + if(LNotEqual(\_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + CreateByteField (Arg0, 0x0A, DILO) // DMA IO Port Low + CreateByteField (Arg0, 0x0B, DIHI) // DMA IO Port High + } + CreateWordField (Arg0, 0x11, IRQW) // IRQ + + Store(One, \_SB.PCI0.VT86.EU1E) // enable embedded COM A. + + ShiftRight(IOLO, 0x03, local0) // set embedded COM A IO base. + ShiftLeft(IOHI, 0x05, local1) // + Or(local0, local1, \_SB.PCI0.VT86.U1BA)// + + if(LNotEqual(\_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + ShiftRight(DILO, 0x02, local0) // set embedded COM A DMA IO base. + ShiftLeft(DIHI, 0x06, local1) // + Or(local0, local1, \_SB.PCI0.VT86.DIBA) // + } + + FindSetLeftBit(IRQW, Local0) // set embedded COM A IRQ. + If(LNotEqual(Local0, Zero)) // + { // + Subtract(Local0, 0x01, Local0) // IRQ is in a bit-mask fashion. + } // + // + Store(Local0, \_SB.PCI0.VT86.UIQ1) + + }// _SRS + +}// embedded UART1. + +// +// Embedded UART2 +// +Device(EUR2) // Communication Device (Modem Port) +{ + Name(_HID, EISAID("PNP0501")) // PnP Device ID 16550 Type + Name(_UID, 0x2) + + Name(_PRW, Package(){8, 4}) + + Method(_PSW, 1) + { + Store(0x40, PADS) // clear _STS first //PMIO Rx30[6] + And(IRQR,0xFE,IRQR) // don not issue SMI //PMIO Rx2A[0]I + + If (Arg0) + { + Store(One, CMBE) + } + Else + { + Store(Zero, CMBE) + } + } + + // + // An empty resource. + // + Name(RSRC,ResourceTemplate (){ + IO(Decode16,0x0,0x0,0x08,0x08) + IRQNoFlags() {} + }) + + Method(_STA) // Status of the COM device + { + Store(0x00, Local0) + + If(LNotEqual(\_SB.PCI0.VT86.ECOM, Zero)) + { + If(\_SB.PCI0.VT86.EU2E) + { + Store(0x0F, Local0) + } + Else + { // if base address is not equal to zero. + If(LNotEqual(\_SB.PCI0.VT86.U2BA, Zero)) + { + Store(0x0D, Local0) + } + } + } + Return(Local0) + } + + Method(_DIS,0) + { + Store(Zero, \_SB.PCI0.VT86.EU2E) // disable embedded COM B. + } + + Method(_CRS, 0) + { + And(_STA(), 0x04, Local0) // If the device is disabled, return the blank template. + If(LEqual(Local0,Zero)) // + { // + Return(RSRC) // + } // + + Name(BUF1,ResourceTemplate() { // This is the buffer prepared for OS. + IO(Decode16,0x2F8,0x2F8,0x08,0x08) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQNoFlags(){3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + }) + + CreateByteField(BUF1, 0x02, IOLO) // IO Port MIN Low + CreateByteField(BUF1, 0x03, IOHI) // IO Port MIN High + CreateByteField(BUF1, 0x04, IORL) // IO Port MAX Low + CreateByteField(BUF1, 0x05, IORH) // IO Port MAX High + + if(LNotEqual(\_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + CreateByteField(BUF1, 0x0A, DILO) // DMA IO Port MIN Low + CreateByteField(BUF1, 0x0B, DIHI) // DMA IO Port MIN High + CreateByteField(BUF1, 0x0C, DIRL) // DMA IO Port MAX Low + CreateByteField(BUF1, 0x0D, DIRH) // DMA IO Port MAX High + } + CreateWordField(BUF1, 0x11, IRQV) // IRQ mask + + ShiftLeft(\_SB.PCI0.VT86.U2BA, 0x03, local0) // IO low. AD7~AD0 + ShiftRight(\_SB.PCI0.VT86.U2BA, 0x05, local1) // IO high. AD9~AD8 + + Store(local0, IOLO) + Store(local1, IOHI) + Store(local0, IORL) + Store(local1, IORH) + + Store(0x00, IRQV) // reset IRQ resource. + If(LNotEqual(\_SB.PCI0.VT86.UIQ2, 0x00)) + { // put assigned IRQ to return buffer if there is any. + ShiftLeft(One, \_SB.PCI0.VT86.UIQ2, IRQV) + } + + if(LNotEqual(\_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + ShiftLeft(\_SB.PCI0.VT86.DIBA, 0x02, local0) // IO low. AD7~AD0 + ShiftRight(\_SB.PCI0.VT86.DIBA, 0x06, local1) // IO high. AD16~AD8 + + Store(local0, DILO) + Store(local1, DIHI) + Store(local0, DIRL) + Store(local1, DIRH) + } + Return(BUF1) + + } // _CRS + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,0) + { + IO(Decode16,0x3F8,0x3F8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFnNoPri() + { + IO(Decode16,0x2F8,0x2F8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFnNoPri() + { + IO(Decode16,0x3E8,0x3E8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFnNoPri() + { + IO(Decode16,0x2E8,0x2E8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFn(2,2) + { + IO(Decode16,0x3F8,0x3F8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFn(2,2) + { + IO(Decode16,0x2F8,0x2F8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFn(2,2) + { + IO(Decode16,0x3E8,0x3E8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFn(2,2) + { + IO(Decode16,0x2E8,0x2E8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + EndDependentFn() + })// _PRS + + Method(_SRS, 1) + { + // + // The Arg0 format is the same as _PRS, and _CRS. + // + CreateByteField (Arg0, 0x02, IOLO) // IO Port Low + CreateByteField (Arg0, 0x03, IOHI) // IO Port High + if(LNotEqual(\_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + CreateByteField (Arg0, 0x0A, DILO) // DMA IO Port Low + CreateByteField (Arg0, 0x0B, DIHI) // DMA IO Port High + } + CreateWordField (Arg0, 0x11, IRQW) // IRQ + + Store(One, \_SB.PCI0.VT86.EU2E) // enable embedded COM A. + + ShiftRight(IOLO, 0x03, local0) // set embedded COM A IO base. + ShiftLeft(IOHI, 0x05, local1) // + Or(local0, local1, \_SB.PCI0.VT86.U2BA) // + + if(LNotEqual(\_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + ShiftRight(DILO, 0x02, local0) // set embedded COM A DMA IO base. + ShiftLeft(DIHI, 0x06, local1) // + Or(local0, local1, \_SB.PCI0.VT86.DIBA) // + } + FindSetLeftBit(IRQW, Local0) // set embedded COM A IRQ. + If(LNotEqual(Local0, Zero)) // + { // + Subtract(Local0, 0x01, Local0) // IRQ is in a bit-mask fashion. + } // + // + Store(Local0, \_SB.PCI0.VT86.UIQ2) + + }// _SRS + +}// embedded UART2. + + + + + Device(RMSC) // all "PNP0C02" devices- pieces that don't fit anywhere else + { + Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices + Name (_UID, 0x13) + + Name(CRS,ResourceTemplate(){ + + IO(Decode16,0x10,0x10,0x00,0x10) + IO(Decode16,0x22,0x22,0x00,0x1E) + IO(Decode16,0x44,0x44,0x00,0x1C) + IO(Decode16,0x62,0x62,0x00,0x02) + IO(Decode16,0x65,0x65,0x00,0x0B) + IO(Decode16,0x72,0x72,0x00,0x02) + IO(Decode16,0x76,0x76,0x00,0x09) + IO(Decode16,0x80,0x80,0x00,0x01) + IO(Decode16,0x84,0x84,0x00,0x03) + IO(Decode16,0x88,0x88,0x00,0x01) + IO(Decode16,0x8c,0x8c,0x00,0x03) + IO(Decode16,0x90,0x90,0x00,0x02) + IO(Decode16,0x92,0x92,0x00,0x01) // INIT & Fast A20 port + IO(Decode16,0x93,0x93,0x00,0x0C) + IO(Decode16,0xA2,0xA2,0x00,0x1E) + IO(Decode16,0xE0,0xE0,0x00,0x10) + IO(Decode16,0x3E0,0x3E0,0x00,0x8) + + // Reserve 4D0 and 4D1 for IRQ edge/level control port + IO(Decode16, 0x4D0,0x4D0,0x00,0x2) + // ACPI IO base address allocation + IO(Decode16, 0, 0, 0, 0, IO0) + // SMBus I/O space if applicable + IO(Decode16, 0, 0, 0, 0, IO1) + // SPI Memory Map IO Base + Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, MEM0) + }) + + Method(_CRS, 0){ + If(LEqual(\_SB.PCI0.VT86.ENIO, 0x01)) // If we should privide the DSDT, ACPI IO must be enabled. + { + CreateWordField(CRS, ^IO0._MIN, MIN0) + CreateWordField(CRS, ^IO0._MAX, MAX0) + CreateByteField(CRS, ^IO0._LEN, LEN0) + Store(\_SB.PCI0.VT86.IOBA, Local0) + ShiftLeft(Local0, 7, Local0) + Store(Local0, MIN0) + Store(Local0, MAX0) + Store(0x80, LEN0) + } + + If(LEqual(\_SB.PCI0.VT86.ENSM, 0x01)) + { + CreateWordField(CRS, ^IO1._MIN, MIN1) + CreateWordField(CRS, ^IO1._MAX, MAX1) + CreateByteField(CRS, ^IO1._LEN, LEN1) + Store(\_SB.PCI0.VT86.SMBA, Local0) + ShiftLeft(Local0, 4, Local0) + Store(Local0, MIN1) + Store(Local0, MAX1) + Store(0x10, LEN1) // Length: 16 Byte + } + + If(LNotEqual(\_SB.PCI0.VT86.SPIB, 0x00)) + { + CreateDWordField(CRS, ^MEM0._BAS, BAS2) + CreateDWordField(CRS, ^MEM0._LEN, LEN2) + Store(\_SB.PCI0.VT86.SPIB, Local0) + ShiftLeft(Local0, 8, Local0) + Store(Local0, BAS2) + Store(0x100, LEN2) + } + + Return(CRS) + } + } + + +} // End of VT86 + + + +//---------------------------------------------------------------- +// +// Copyright (c) 2005-2012 VIA Technologies, Inc. +// This program contains proprietary and confidential information. +// All rights reserved except as may be permitted by prior written +// consent. +// +//---------------------------------------------------------------- +//Rev Date Name Description +//---------------------------------------------------------------- + +Name(PICM, Package(){ + + // VIA VGA Device(Integrated Graphics Device) + Package(){0x0001ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // VGA, INTA + + //PCI Slot 1 + Package(){0x0008ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTA + Package(){0x0008ffff, 1, \_SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTB + Package(){0x0008ffff, 2, \_SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTC + Package(){0x0008ffff, 3, \_SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTD + + //PCI Slot 2 + Package(){0x0009ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTA + Package(){0x0009ffff, 1, \_SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTB + Package(){0x0009ffff, 2, \_SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTC + Package(){0x0009ffff, 3, \_SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTD + + //PCI Slot 3 + Package(){0x000Affff, 0, \_SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTA + Package(){0x000Affff, 1, \_SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTB + Package(){0x000Affff, 2, \_SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTC + Package(){0x000Affff, 3, \_SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTD + + // USB Device Controller + Package(){0x000Bffff, 0, \_SB.PCI0.VT86.LNKA, 0}, + + // SDIO Controller + Package(){0x000cffff, 0, \_SB.PCI0.VT86.LNKA, 0}, + // SD $ MS Controller + Package(){0x000dffff, 0, \_SB.PCI0.VT86.LNKB, 0}, + // CE-ATA $ NF Controller(Card Boot) + Package(){0x000effff, 0, \_SB.PCI0.VT86.LNKC, 0}, + // VIA VX800 IDE + Package(){0x000fffff, 0, \_SB.PCI0.VT86.LNKB, 0}, + + // VIA UHCI USB1 Device + Package(){0x0010ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, + // VIA UHCI USB2 Device + Package(){0x0010ffff, 1, \_SB.PCI0.VT86.LNKB, 0}, + // VIA UHCI USB3 Device + Package(){0x0010ffff, 2, \_SB.PCI0.VT86.LNKC, 0}, + // VIA EHCI USB 2.0 Device + Package(){0x0010ffff, 3, \_SB.PCI0.VT86.LNKD, 0}, + + // SB HDAC(Azalia) Audio + Package(){0x0014ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // HD Audio, INTA + + }) + +Name(APIC, Package(){ + + // VIA VGA Device(Integrated Graphics Device) + Package(){0x0001ffff, 0, 0, 0x10}, + + //PCI Slot 1 + Package(){0x0008ffff, 0, 0, 0x10}, + Package(){0x0008ffff, 1, 0, 0x10}, + Package(){0x0008ffff, 2, 0, 0x10}, + Package(){0x0008ffff, 3, 0, 0x10}, + + //PCI Slot 2 + Package(){0x0009ffff, 0, 0, 0x10}, + Package(){0x0009ffff, 1, 0, 0x10}, + Package(){0x0009ffff, 2, 0, 0x10}, + Package(){0x0009ffff, 3, 0, 0x10}, + + //PCI Slot 3 + Package(){0x000Affff, 0, 0, 0x10}, + Package(){0x000Affff, 1, 0, 0x10}, + Package(){0x000Affff, 2, 0, 0x10}, + Package(){0x000Affff, 3, 0, 0x10}, + + // USB Device Controller + Package(){0x000Bffff, 0, 0, 0x13}, // USBD, INTA + + // SDIO Controller + Package(){0x000cffff, 0, 0, 0x16}, // SDIO, INTA + // SD $ MS Controller + Package(){0x000dffff, 0, 0, 0x17}, // Card Reader, INTA + // CE-ATA $ NF Controller(Card Boot) + Package(){0x000effff, 0, 0, 0x14}, // Card Boot(NAND Flash), INTA + // VIA VX800 IDE + Package(){0x000fffff, 0, 0, 0x15}, //IDE, INTA + + // VIA UHCI USB1 Device + Package(){0x0010ffff, 0, 0, 0x14}, + // VIA UHCI USB2 Device + Package(){0x0010ffff, 1, 0, 0x16}, + // VIA UHCI USB3 Device + Package(){0x0010ffff, 2, 0, 0x15}, + // VIA EHCI USB 2.0 Device + Package(){0x0010ffff, 3, 0, 0x17}, + + // SB HDAC(Azalia) Audio + Package(){0x0014ffff, 0, 0, 0x11}, //HD Audio , INTA + +}) // end of APIX + +Method(_PRT, 0, NotSerialized) +{ + If(LNot(PICF)) + { + //PIC + Return(PICM) + }Else{ + //APIC + Return(APIC) + } +} + + Device(P2PB) + { + Name (_ADR, 0x00130000) + + OperationRegion(RP2P,PCI_Config,0x00,0x100) + Field(RP2P,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x19), + BUS1, 8, + } + + Method(_BBN,0) + { + Return(BUS1) + } + + Method(_STA, 0) + { + If(LNotEqual(\_SB.PCI0.P2PB.VID, 0x1106)) { + Return(0x00) + }Else { + If(LEqual(\_SB.PCI0.P2PB.CMDR, 0x00)) { + Return(0x0D) + }Else{ + Return(0x0F) // present, enabled, functioning + } + } + } + + Name(PIC4, Package(){ + Package(){0x0003ffff, 0,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0003ffff, 1,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0003ffff, 2,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0003ffff, 3,\_SB.PCI0.VT86.LNKA , 0}, + + Package(){0x0004ffff, 0,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0004ffff, 1,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0004ffff, 2,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0004ffff, 3,\_SB.PCI0.VT86.LNKA , 0}, + + Package(){0x0005ffff, 0,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0005ffff, 1,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0005ffff, 2,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0005ffff, 3,\_SB.PCI0.VT86.LNKA , 0}, + + }) + + Name(API4, Package(){ + Package(){0x0003ffff, 0, 0, 0x10}, + Package(){0x0003ffff, 1, 0, 0x10}, + Package(){0x0003ffff, 2, 0, 0x10}, + Package(){0x0003ffff, 3, 0, 0x10}, + + Package(){0x0004ffff, 0, 0, 0x10}, + Package(){0x0004ffff, 1, 0, 0x10}, + Package(){0x0004ffff, 2, 0, 0x10}, + Package(){0x0004ffff, 3, 0, 0x10}, + + Package(){0x0005ffff, 0, 0, 0x10}, + Package(){0x0005ffff, 1, 0, 0x10}, + Package(){0x0005ffff, 2, 0, 0x10}, + Package(){0x0005ffff, 3, 0, 0x10}, + + }) + + Method(_PRT, 0x0, NotSerialized) + { + If(LNot(PICF)) + { + Return(PIC4) + }Else { + Return(API4) + } + } + + Method(_PRW, 0x00, NotSerialized) + { + Return(Package(){0x05,4}) //PME# + } + Device(P4D3) + { + Name(_ADR, 0x00030000) + } + } // Device(P2PB) + + Device(HDAC) + { + Name(_ADR, 0x00140000) + + OperationRegion(RHDA,PCI_Config,0x00,0x100) + Field(RHDA,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + } + + Method(_STA, 0) + { + If(LNotEqual(\_SB.PCI0.HDAC.VID, 0x1106)) { + Return(0x00) + }Else { + If(LEqual(\_SB.PCI0.HDAC.CMDR, 0x00)) { + Return(0x0D) + }Else{ + Return(0x0F) // present, enabled, functioning + } + } + } + + Method(_PRW) + { + Return (Package(){0xD, 4}) + } + }//Device(HDAC) + + +} // Device(PCI0) + +//----------------------------------------------------------------------- +// System board extension Device node for ACPI BIOS +//----------------------------------------------------------------------- +/* + +Procedure: RMEM + +Description: System board extension Device node for ACPI BIOS +Place the device under \_SB scope, As per Msft the MEM +Device is used to reserve Resources that are decoded out of PCI Bus +Important consideration : +Logic to reserve the memory within 0xC0000 - 0xFFFFF Extended BIOS area is based on assumption, that +the BIOS Post has detected all expansion ROMs in the region and made their memory ranges +shadowable ( copied to RAM at the same address, for performance reasons). The rest of the region is left non-Shadowable, +hence no memory is decoded there. Such region is decoded to PCI bus (to be reserved in PCI0._CRS) +Whatever memory is Shadowed, thus, decoded as non "FF"s, is required to be reserved in "SYSM" System board extension Device node, +unless is not already reserved by some of PCI Device drivers. There have been observed the difference of how Win9x & Win2000 +OSes deal with Expansion ROM memory. Win9x Device drivers are tend to claim its expension ROMs regions as used +by the device; Win2000 never use such ROM regions for its devices. Therefore there can be different +approach used for different OSes in reservation unclaimed memory in "SYSM" Device node. +is forwarded to PCI Bus + +Input: Nothing + +Output: _CRS buffer + +**************************************************************************/ + +Device(RMEM) { + Name(_HID, EISAID("PNP0C01")) // Hardware Device ID, System Board + + Name(_UID, 1) + Name(CRS, ResourceTemplate() + { + // Base Address 0 - 0x9FFFF , 640k DOS memory + Memory32Fixed(ReadWrite,0x0000, 0xA0000 ) //Writeable + // Shadow RAM1, C0000 - E0000, 128k Expansion BIOS + Memory32Fixed(ReadOnly, 0x00000, 0x00000, RAM1) //Non-writeable + // Shadow RAM2, E0000 - 1M, 128k System BIOS + Memory32Fixed(ReadOnly, 0xE0000, 0x20000, RAM2) //Non-writeable + // Base Address 1M - Top of system present memory + Memory32Fixed(ReadWrite,0x100000,0x00000, RAM3) //Writeable + + }) + + Method (_CRS, 0) + { + CreateDWordField(CRS, ^RAM1._BAS, BAS1) + CreateDWordField(CRS, ^RAM1._LEN, LEN1) + CreateDWordField(CRS, ^RAM2._BAS, BAS2) + CreateDWordField(CRS, ^RAM2._LEN, LEN2) + CreateDWordField(CRS, ^RAM3._LEN, LEN3) + + //RAM3 + Store(\_SB.PCI0.MEMC.LTMA, Local0) + ShiftLeft(Local0, 0x10, Local2) + Store(\_SB.PCI0.MEMC.ENIG, Local1) + If(LEqual(Local1, 1)) // Check whether the Internal Graphic is enabled. + { + Add(\_SB.PCI0.MEMC.FBSZ, 2, Local3) + ShiftLeft(1, Local3, Local4) + ShiftLeft(Local4, 0x14, Local4) + Subtract(Local2, Local4, Local2) // Subtract the Framebuffer Size + } + Store(\_SB.PCI0.MEMC.ENTS, Local1) + If(LEqual(Local1, 1)) // Check Whether the Top SMRAM Segment is Enabled + { + ShiftLeft(1, \_SB.PCI0.MEMC.TSMS, Local5) + ShiftLeft(Local5, 0x14, Local5) + Subtract(Local2, Local5, Local2) // Subtract Top SM RAM Size + } + Subtract(Local2, 0x100000, LEN3) + + Return(CRS) + } +} + + }//Scope(\_SB) +} Added: cpu/x86/pc/olpc/via/rtcwake.fth =================================================================== --- cpu/x86/pc/olpc/via/rtcwake.fth (rev 0) +++ cpu/x86/pc/olpc/via/rtcwake.fth 2009-06-25 21:13:27 UTC (rev 1222) @@ -0,0 +1,97 @@ +purpose: Suspend/resume test with RTC wakeup +\ See license at end of file + +h# 7d constant cmos-alarm-day \ Offset of day alarm in CMOS +h# 7e constant cmos-alarm-month \ Offset of month alarm in CMOS +h# 7f constant cmos-century \ Offset of century byte in CMOS + +dev /rtc + +cmos-alarm-day " alarm_day" integer-property +cmos-alarm-month " alarm_month" integer-property +cmos-century " century" integer-property + +\ There are a couple of reasons why you might not want to enable the IRQ: +\ a) It might be shared with the timer IRQ so it is already enabled +\ b) When using the alarm to wakeup from sleep, the IRQ might be unnecessary. + +0 value alarm-irq +false value enable-alarm-irq? + +defer alarm-hook ' noop to alarm-hook + +: disable-alarm ( -- ) + enable-alarm-irq? if alarm-irq disable-interrupt then + h# b cmos@ h# 20 invert and h# b cmos! +; + +: rtc-handler ( -- ) + disable-alarm + h# c cmos@ drop \ Clear RTC interrupt flags + alarm-hook +; + +: enable-alarm ( -- ) + ['] rtc-handler 8 interrupt-handler! + enable-alarm-irq? if alarm-irq disable-interrupt then + h# c cmos@ drop \ Clear RTC interrupt flags + h# b cmos@ h# 20 or h# b cmos! +; + +: set-alarm ( [ handler-xt ] secs -- ) \ No handler-xt if secs is 0 + disable-alarm + ?dup 0= if exit then ( handler-xt secs ) + swap to alarm-hook ( secs ) + now ( secs s m h ) + d# 60 * d# 60 * swap d# 60 * + + + ( s ) + d# 60 /mod d# 60 /mod d# 24 mod ( s m h ) + h# c0 cmos-alarm-month cmos! ( s m h ) \ Any day + h# c0 cmos-alarm-day cmos! ( s m h ) \ Any month + 5 bcd! 3 bcd! 1 bcd! ( ) + enable-alarm +; + +dend + +: show-rtc-wake ." R" ; + +d# 1 constant rtc-alarm-delay +: pm-sleep-rtc ( -- ) + 0 acpi-l@ h# 400.0000 or 0 acpi-l! \ Enable RTC SCI + ['] show-rtc-wake rtc-alarm-delay " set-alarm" clock-node @ $call-method + s + 0 acpi-l@ h# 400.0000 invert and 0 acpi-l! \ Disable RTC SCI +; +: rtc-wackup + 0 + begin pm-sleep-rtc space dup . (cr 1+ key? until + key drop +; + +stand-init: Century + h# 20 cmos-century cmos! \ The century is in BCD, hence h# +; + +\ LICENSE_BEGIN +\ Copyright (c) 2009 FirmWorks +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END

10 years

1
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r1221 - in dev: . hdaudio

by svn＠openfirmware.info

Author: wmb Date: 2009-06-10 19:26:33 +0200 (Wed, 10 Jun 2009) New Revision: 1221 Added: dev/hdaudio/ dev/hdaudio/audio.fth dev/hdaudio/build/ dev/hdaudio/conexant.fth dev/hdaudio/core.fth dev/hdaudio/extra.fth dev/hdaudio/hdaudio.bth Log: Added HDAudio driver from Luke Gorrie. Added: dev/hdaudio/audio.fth =================================================================== --- dev/hdaudio/audio.fth (rev 0) +++ dev/hdaudio/audio.fth 2009-06-10 17:26:33 UTC (rev 1221) @@ -0,0 +1,17 @@ +purpose: High-level glue and codec selection +\ Intel HD Audio top-level +hex + +" audio" device-name +" sound" device-type + +: vendor-id ( -- id ) 0 to node h# f0000 cmd? ; + +: setup-defers ( -- ) + vendor-id case + h# 14f1.5066 of cx2058x-init endof + endcase +; + +' setup-defers to detect-codec + Added: dev/hdaudio/conexant.fth =================================================================== --- dev/hdaudio/conexant.fth (rev 0) +++ dev/hdaudio/conexant.fth 2009-06-10 17:26:33 UTC (rev 1221) @@ -0,0 +1,88 @@ +purpose: Conexant CX2058x codec +\ See license at end of file +hex + +\ \ Conexant + +: power-on ( -- ) h# 70500 cmd ; +: power-off ( -- ) h# 70503 cmd ; +: power-on-all ( -- ) + " "(01 10 11 12 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24)" + bounds do i c@ to node power-on loop +; + +: volume-on-all ( -- ) + h# 14 to node h# 36006 cmd h# 35006 cmd + h# 23 to node h# 36004 cmd h# 35004 cmd + h# 17 to node h# 3a004 cmd h# 39004 cmd + h# 18 to node h# 3a004 cmd h# 39004 cmd + h# 14 to node h# 36200 cmd h# 35200 cmd + h# 10 to node h# 3a03e cmd h# 3903e cmd +; + +: cx2058x-open ( -- ) + h# 10 to dac + h# 14 to adc + power-on-all + volume-on-all +; + +: cx2058x-close ( -- ) + 1 to node ( function group) power-off +; + +h# 1a value mic-in \ Port B +h# 1b value mic \ Port C +h# 17 value mux \ mux between the two + +: pin-sense? ( -- ? ) h# f0900 cmd? h# 8000.0000 and 0<> ; +: set-connection ( n -- ) h# 70100 or cmd ; +: enable-hp-input ( -- ) h# 70721 cmd ; + +: cx2058x-enable-recording ( -- ) + mic-in to node pin-sense? if + mux to node 0 set-connection mic-in to node enable-hp-input + else + mux to node 1 set-connection mic to node enable-hp-input + then +; + +: cx2058x-disable-recording ( -- ) ; + +: cx2058x-enable-playback ( -- ) + h# 10 to node h# 70640 cmd h# 20000 stream-format or cmd +; +: cx2058x-disable-playback ( -- ) ; + +: cx2058x-init ( -- ) + ['] cx2058x-open to open-codec + ['] cx2058x-close to close-codec + ['] cx2058x-enable-recording to enable-codec-recording + ['] cx2058x-disable-recording to disable-codec-recording + ['] cx2058x-enable-playback to enable-codec-playback + ['] cx2058x-enable-playback to disable-codec-playback +; + +\ LICENSE_BEGIN +\ Copyright (c) 2009 Luke Gorrie <luke(a)bup.co.nz> +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END Added: dev/hdaudio/core.fth =================================================================== --- dev/hdaudio/core.fth (rev 0) +++ dev/hdaudio/core.fth 2009-06-10 17:26:33 UTC (rev 1221) @@ -0,0 +1,505 @@ +\ Intel HD Audio driver +\ See license at end of file + +\ warning off +hex + +\ \ Defers + +\ detect-codec fills in the defers below to suit the available hardware +defer detect-codec + +defer open-codec ' noop to open-codec +defer close-codec ' noop to close-codec +defer enable-codec-recording ' noop to enable-codec-recording +defer disable-codec-recording ' noop to disable-codec-recording +defer enable-codec-playback ' noop to enable-codec-playback +defer disable-codec-playback ' noop to disable-codec-playback + +0 value dac \ digital to analogue converter node id +0 value adc \ analogue to digital converter node id + +\ \ DMA setup + +0 value au + +my-address my-space encode-phys +0 encode-int encode+ 0 encode-int encode+ + +0 0 my-space h# 0300.0010 + encode-phys encode+ +0 encode-int encode+ h# 4000 encode-int encode+ +" reg" property + +: my-w@ ( offset -- w ) my-space + " config-w@" $call-parent ; +: my-w! ( w offset -- ) my-space + " config-w!" $call-parent ; + +: map-regs ( -- ) + 0 0 my-space h# 0300.0010 + h# 4000 " map-in" $call-parent to au + 4 my-w@ 6 or 4 my-w! +; +: unmap-regs ( -- ) + 4 my-w@ 7 invert and 4 my-w! + au h# 4000 " map-out" $call-parent +; + +: dma-alloc ( len -- adr ) " dma-alloc" $call-parent ; +: dma-free ( adr size -- ) " dma-free" $call-parent ; +: dma-map-in ( adr len flag -- adr ) " dma-map-in" $call-parent ; +: dma-map-out ( adr len -- ) " dma-map-out" $call-parent ; + +\ \ Register definitions + +: icw h# 60 au + ; \ Immediate Command Write +: irr h# 64 au + ; \ Immediate Response Read +: ics h# 68 au + ; \ Immediate Command Status +: gctl h# 08 au + ; +: wakeen h# 0c au + ; \ Wake enable +: statests h# 0e au + ; \ Wake status +: counter h# 30 au + ; \ Wall Clock Counter +: corblbase h# 40 au + ; +: corbubase h# 44 au + ; +: corbwp h# 48 au + ; \ CORB write pointer (last valid command) +: corbrp h# 4a au + ; \ CORB read pointer (last processed command) +: corbctl h# 4c au + ; +: corbsts h# 4d au + ; +: corbsize h# 4e au + ; +: rirblbase h# 50 au + ; +: rirbubase h# 54 au + ; +: rirbwp h# 58 au + ; +: rirbctl h# 5c au + ; +: rirbsts h# 5d au + ; +: rirbsize h# 5e au + ; +: dplbase h# 70 au + ; +: dpubase h# 74 au + ; + +: running? ( -- ? ) gctl rl@ 1 and 0<> ; +: reset ( -- ) 0 gctl rl! begin running? 0= until ; +: start ( -- ) 1 gctl rl! begin running? until ; + +\ \\ Stream Descriptors +\ Default: 48kHz 16bit stereo +1 value scale-factor +0 value sample-base +0 value sample-mul +0 value sample-div +1 value sample-format +2 value #channels + +: stream-format ( -- u ) + sample-base d# 14 lshift ( acc ) + sample-mul d# 11 lshift or ( acc ) + sample-div d# 8 lshift or ( acc ) + sample-format 4 lshift or ( acc ) + #channels 1- or ( fmt ) +; + +: sample-rate! ( base mul div ) to sample-div to sample-mul to sample-base ; + +: 48kHz ( -- ) 0 0 0 sample-rate! ; +: 44.1kHz ( -- ) 1 0 0 sample-rate! ; +: 96kHz ( -- ) 0 1 0 sample-rate! ; +: 192kHz ( -- ) 0 3 0 sample-rate! ; + +: 8bit ( -- ) 0 to sample-format ; +: 16bit ( -- ) 1 to sample-format ; +: 20bit ( -- ) 2 to sample-format ; +: 24bit ( -- ) 3 to sample-format ; +: 32bit ( -- ) 4 to sample-format ; + +\ Stream descriptor register interface. +\ There are multiple stream descriptors, each with their own register set. +0 constant sd# +: sd+ ( offset -- adr ) sd# h# 20 * + au + ; + +: sdctl h# 80 sd+ ; +: sdsts h# 83 sd+ ; +: sdlpib h# 84 sd+ ; +: sdcbl h# 88 sd+ ; +: sdlvi h# 8c sd+ ; +: sdfifos h# 90 sd+ ; +: sdfmt h# 92 sd+ ; +: sdbdpl h# 98 sd+ ; +: sdbdpu h# 9c sd+ ; +: sdlicba h# 2084 sd+ ; + +\ \ CORB/RIRB command interface +\ DMA-based circular command / response buffers. + +\ \\ CORB - Command Output Ring Buffer + +d# 1024 constant /corb +0 value corb +0 value corb-phys +0 value corb-pos + +: corb-dma-on ( -- ) 2 corbctl rb! ; +: corb-dma-off ( -- ) 0 corbctl rb! begin corbctl rb@ 2 and 0= until ; + +: init-corb ( -- ) + /corb dma-alloc to corb + corb /corb 0 fill + corb /corb true dma-map-in to corb-phys + corb-dma-off + corb-phys corblbase rl! + 0 corbubase rl! + 2 corbsize rb! \ 256 entries + corbrp rw@ to corb-pos + corb-dma-on +; + +: wait-for-corb-sync ( -- ) begin corbrp rw@ corb-pos = until ; + +: corb-tx ( u -- ) + corb-pos 1+ d# 256 mod to corb-pos + corb-pos cells corb + ! ( ) + corb-pos corbwp rw! + wait-for-corb-sync +; + +\ \\ RIRB - Response Inbound Ring Buffer + +d# 256 2* cells constant /rirb +0 value rirb +0 value rirb-phys +0 value rirb-pos + +: rirb-dma-off ( -- ) 0 rirbctl rb! ; +: rirb-dma-on ( -- ) 2 rirbctl rb! ; + +: init-rirb ( -- ) + rirb-dma-off + /rirb dma-alloc to rirb + rirb /rirb 0 fill + rirb /rirb true dma-map-in to rirb-phys + rirb-phys rirblbase rl! + 0 rirbubase rl! + 2 rirbsize rb! \ 256 entries + rirbwp rw@ to rirb-pos + rirb-dma-on +; + +: rirb-data? ( -- ) rirb-pos rirbwp rw@ <> ; + +: rirb-read ( -- resp solicited? ) + begin rirb-data? until + rirb-pos 1+ d# 256 mod to rirb-pos + rirb-pos 2 * cells rirb + ( adr ) + dup @ ( adr resp ) + swap cell+ @ ( resp resp-ex ) + h# 10 and 0= ( resp? solicited? ) +; + +: rirb-rx ( -- ) + begin + rirb-read ( resp solicited? ) + if exit else ." unsolicited response: " . cr then + again +; + +\ \ Commands to codecs + +0 0 value codec value node \ current target for commands + +: encode-command ( codec node verb -- ) + codec d# 28 lshift node d# 20 lshift or or +; + +: cmd? ( verb -- resp ) encode-command corb-tx rirb-rx ; +: cmd ( verb -- ) cmd? drop ; + +\ \ Streams +\ \\ Starting and stopping channels + +: assert-stream-reset ( -- ) 1 sdctl rb! begin sdctl rb@ 1 and 1 = until ; +: deassert-stream-reset ( -- ) 0 sdctl rb! begin sdctl rb@ 1 and 0 = until ; + +: reset-stream ( -- ) assert-stream-reset deassert-stream-reset ; +: stop-stream ( -- ) 0 sdctl rb! begin sdctl rb@ 2 and 0= until ; +: start-stream ( -- ) 2 sdctl rb! begin sdctl rb@ 2 and 0<> until ; + +\ \ Device open and close + +: restart-controller ( -- ) reset start 1 ms ( 250us wait required ) ; +: init-controller ( -- ) map-regs restart-controller init-corb init-rirb ; +: init-codec ( -- ) detect-codec open-codec ; +: close-controller ( -- ) reset unmap-regs ; + +: open ( -- flag ) init-controller init-codec true ; +: close ( -- ) close-codec close-controller ; + +d# 48.000 value sample-rate + +: low-rate? ( Hz ) dup d# 48.000 < swap d# 44.100 <> and ; + +: set-sample-rate ( Hz -- ) + to sample-rate + dup low-rate? if + 48kHz d# 48.000 swap / to scale-factor + else + 1 to scale-factor + d# 48.000 / case \ find nearest supported rate + 0 of 44.1kHz endof + 1 of 48kHz endof + 2 of 96kHz endof + 3 of 48kHz 2 to scale-factor endof + dup of 192kHz endof + endcase + then +; + +\ \ Streams + +\ \\ Sound buffer +\ Sample data for playback or recording. + +0 value sound-buffer +0 value sound-buffer-phys +0 value /sound-buffer + +: install-sound-buffer ( adr len -- ) + 2dup to /sound-buffer to sound-buffer + true dma-map-in to sound-buffer-phys +; + +\ Pad buffer: filled with zeros to pad out the end of the stream. +\ (Streams automatically repeat -- this is so we'll have time to stop +\ before that happens.) + +0 value pad-buffer +0 value pad-buffer-phys +d# 2048 value /pad-buffer + +: alloc-pad-buffer ( -- ) + /pad-buffer dma-alloc to pad-buffer + pad-buffer /pad-buffer true dma-map-in to pad-buffer-phys + pad-buffer /pad-buffer 0 fill +; + +: free-pad-buffer ( -- ) + pad-buffer pad-buffer-phys /pad-buffer dma-map-out + pad-buffer /pad-buffer dma-free +; + +\ \\ Buffer Descriptor List + +struct ( buffer descriptor ) + 4 field >bd-laddr + 4 field >bd-uaddr + 4 field >bd-len + 4 field >bd-ioc +constant /bd + +0 value bdl +0 value bdl-phys +d# 256 /bd * value /bdl + +: buffer-descriptor ( n -- adr ) /bd * bdl + ; + +: allocate-bdl ( -- ) + /bdl dma-alloc to bdl + bdl /bdl 0 fill + bdl /bdl true dma-map-in to bdl-phys +; + +: free-bdl ( -- ) bdl bdl-phys /bdl dma-map-out bdl /bdl dma-free ; + +: setup-bdl ( -- ) + allocate-bdl + sound-buffer-phys 0 buffer-descriptor >bd-laddr ! ( len ) + 0 0 buffer-descriptor >bd-uaddr ! ( len ) + /sound-buffer 0 buffer-descriptor >bd-len ! ( ) + 1 0 buffer-descriptor >bd-ioc ! + \ pad buffer + alloc-pad-buffer + pad-buffer-phys 1 buffer-descriptor >bd-laddr ! + 0 1 buffer-descriptor >bd-uaddr ! + /pad-buffer 1 buffer-descriptor >bd-len ! + 0 1 buffer-descriptor >bd-ioc ! +; + +: teardown-bdl ( -- ) + free-bdl + free-pad-buffer +; + +\ \\ Stream descriptor (DMA engine) + +: setup-stream ( -- ) + reset-stream + /sound-buffer /pad-buffer + sdcbl rl! \ bytes of stream data + h# 440000 sdctl rl! \ stream 4 + 1 sdlvi rw! \ two buffers + 1c sdsts c! \ clear status flags + bdl-phys sdbdpl rl! + 0 sdbdpu rl! + stream-format sdfmt rw! +; + +: stream-done? ( -- ) sdsts c@ 4 and 0<> ; +: wait-stream-done ( -- ) begin stream-done? until ; + +\ \\ Upsampling + +0 value src +0 value /src +0 value dst +0 value /dst +0 value upsample-factor + +: dst! ( value step# sample# -- ) + upsample-factor * + ( value dst-sample# ) 4 * dst + w! +; + +\ Copy source sample N into a series of interpolated destination samples. +: copy-sample ( n -- ) + dup 4 * src + ( n src-adr ) + dup <w@ swap 4 + <w@ ( n s1 s2 ) + over - upsample-factor / ( n s1 step ) + upsample-factor 0 do + 2dup i * + ( n s1 step s ) + i 4 pick ( n s1 step s i n ) + dst! + loop + 3drop +; + +: upsample-channel ( -- ) + /src 4 / 1 do + i copy-sample + loop +; + +: upsample ( adr len factor -- adr len ) + to upsample-factor to /src to src + /src upsample-factor * to /dst + /dst dma-alloc to dst + upsample-channel \ left + src 2+ to src dst 2+ to dst + upsample-channel \ right + dst 2 - /dst ( dst dst-len ) +; + +\ \\ Amplifier control + +: output-gain ( gain -- ) h# 3b000 or cmd ; +: input-gain ( gain -- ) h# 37000 or cmd ; + +: amp-caps ( -- u ) h# f0012 cmd? ; + +: gain-steps ( -- n ) amp-caps 8 rshift h# 7f and 1+ ; \ how many steps? +: step-size ( -- n ) amp-caps d# 16 rshift h# 7f and 1+ ; \ in units of -0.25dB +: 0dB-step ( -- n ) amp-caps h# 7f and ; \ which step is 0dB? + +: steps/dB ( -- #steps ) step-size 4 * ; +: dB>steps ( dB -- #steps ) -4 * step-size / ; +: step# ( dB -- step ) dB>steps 0dB-step + ; + +\ \\ Playback + +: upsampling? ( -- ? ) scale-factor 1 <> ; + +: open-out ( -- ) + 4 to sd# + 48kHz + upsampling? if scale-factor upsample then ( adr len ) +; + +: audio-out ( adr len -- actual ) + install-sound-buffer ( ) + setup-bdl + setup-stream + enable-codec-playback + start-stream + /sound-buffer ( actual ) +; + +: write ( adr len -- actual ) + open-out audio-out +; + +: release-sound-buffer ( -- ) + sound-buffer sound-buffer-phys /sound-buffer dma-map-out + upsampling? if sound-buffer /sound-buffer dma-free then +; + +: write-done ( -- ) + wait-stream-done + stop-stream + free-bdl + release-sound-buffer +; + +: set-volume ( dB -- ) dac to node step# output-gain ; + +\ \\ Recording + +0 value recbuf +0 value recbuf-phys +d# 65535 value /recbuf + +: open-in ( -- ) 48kHz ; + +: record-stream ( -- ) + 0 to sd# + 1 to #channels + reset-stream + /sound-buffer /pad-buffer + sdcbl rl! \ buffer length + h# 100000 sdctl rl! \ stream 1, input + 1 sdlvi rw! \ two buffers + h# 1c sdsts c! \ clear status flags + bdl-phys sdbdpl rl! + 0 sdbdpu rl! + stream-format sdfmt rw! + adc to node + h# 70610 cmd \ stream 1, channel 0 + h# 20000 stream-format or cmd \ stream format +; + +: audio-in ( adr len -- actual ) + install-sound-buffer ( ) + setup-bdl + record-stream + enable-codec-recording + start-stream + wait-stream-done + stop-stream + release-sound-buffer + free-pad-buffer + /recbuf +; + +: close-in ( -- ) disable-codec-recording ; + +0 value boost-db + +: mic+20db ( -- ) d# 20 to boost-db ; +: mic+0db ( -- ) 0 to boost-db ; + +: set-record-gain ( dB -- ) ; \ adc to node step# input-gain ; +: in-amp-caps ( -- u ) h# f000d cmd? ; +: in-gain-steps ( -- n ) in-amp-caps 8 rshift h# 7f and 1+ ; +: set-record-gain ( dB -- ) drop ( hardcoded for now ) adc to node h# 40 input-gain ; + +\ LICENSE_BEGIN +\ Copyright (c) 2009 Luke Gorrie <luke(a)bup.co.nz> +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END Added: dev/hdaudio/extra.fth =================================================================== --- dev/hdaudio/extra.fth (rev 0) +++ dev/hdaudio/extra.fth 2009-06-10 17:26:33 UTC (rev 1221) @@ -0,0 +1,172 @@ +purpose: Additional utility routines for the HD Audio driver +\ See license at end of file + +\ \ Widget graph +\ \\ Traversal + +' noop value do-xt +0 value do-tree-level + +defer do-subtree + +: #subnodes ( -- u ) h# f0004 cmd? h# ff and ; +: first-subnode ( -- node ) h# f0004 cmd? d# 16 rshift ; + +: do-subtree-recursive ( xt codec node -- ) + to node to codec ( ) + do-xt execute ( ) + codec first-subnode #subnodes bounds ?do ( codec ) + do-tree-level 1 + to do-tree-level + dup i do-subtree + do-tree-level 1 - to do-tree-level + loop ( codec ) + drop +; + +' do-subtree-recursive is do-subtree + +: do-tree ( xt -- ) to do-xt 0 0 do-subtree ; + +\ - Inspecting widgets + +\ \\ Getting parameters + +: config-default ( -- c ) h# f1c00 cmd? ; +: default-device ( -- d ) config-default d# 20 rshift f and ; +: connectivity ( -- c ) config-default d# 30 rshift ; + +: #subnodes h# f0004 cmd? h# ff and ; +: first-subnode h# f0004 cmd? d# 16 rshift ; + +: widget-type ( -- u ) h# f0009 cmd? d# 20 rshift f and ; +: pin-widget? ( -- ? ) widget-type 4 = ; +: builtin? ( -- ? ) connectivity 2 = ; +: speaker? ( -- ? ) default-device 1 = ; +: headphone? ( -- ? ) default-device 2 = ; +: mic? ( -- ? ) default-device h# a = ; + +: config-default ( -- c ) h# f1c00 cmd? ; +: connection-select ( -- n ) h# f0100 cmd? ; +: default-device ( -- d ) config-default d# 20 rshift f and ; +: location ( -- l ) config-default d# 24 rshift 3f and ; +: color ( -- c ) config-default d# 12 rshift f and ; +: connectivity ( -- c ) config-default d# 30 rshift ; +: connection-list ( -- n ) f0200 cmd? ; + +: gain/mute ( output? left? -- gain mute? ) + 0 swap if h# 2000 or then + swap if h# 8000 or then + h# b0000 or cmd? + dup h# 7f and ( res gain ) + swap h# 80 and 0<> ( gain mute? ) +; + +: .connectivity ( -- ) + case connectivity + 0 of ." external " endof + 1 of ." unused " endof + 2 of ." builtin " endof + 3 of ." builtin/external " endof + endcase +; + +: .color ( -- ) + case color + 1 of ." black " endof + 2 of ." grey " endof + 3 of ." blue " endof + 4 of ." green " endof + 5 of ." red " endof + 6 of ." orange " endof + 7 of ." yellow " endof + 8 of ." purple " endof + 9 of ." pink " endof + e of ." white " endof + endcase +; + +: .location ( -- ) + case location + 1 of ." rear " endof + 2 of ." front " endof + 3 of ." left " endof + 4 of ." right " endof + 5 of ." top " endof + 6 of ." bottom " endof + 7 of ." special " endof + endcase +; + +: .default-device ( -- ) + case default-device + 0 of ." line out)" endof + 1 of ." speaker)" endof + 2 of ." HP out)" endof + 3 of ." CD)" endof + 4 of ." SPDIF out)" endof + 5 of ." digital other out)" endof + 6 of ." modem line side)" endof + 7 of ." modem handset side)" endof + 8 of ." line in)" endof + 9 of ." aux)" endof + a of ." mic in)" endof + b of ." telephony)" endof + c of ." SPDIF in)" endof + d of ." digital other in)" endof + dup of ." unknown)" endof + endcase +; + +: .node ( -- ) + do-tree-level spaces + codec . ." / " node . + f0200 cmd? lbsplit 4 0 do <# u# u# u#> type space loop 2 spaces + widget-type case + 0 of ." audio output" endof + 1 of ." audio input" endof + 2 of ." audio mixer" endof + 3 of ." audio selector" endof + 4 of ." pin widget (" .connectivity .color .location .default-device endof + 5 of ." power widget" endof + 6 of ." volume knob" endof + 7 of ." beep generator" endof + dup of endof + endcase + cr +; + +\ : in-amp-caps ( -- u ) h# f000d cmd? ; +\ : in-gain-steps ( -- n ) in-amp-caps 8 rshift h# 7f and 1+ ; +: in-step-size ( -- n ) in-amp-caps d# 16 rshift h# 7f and 1+ ; +: in-0dB-step ( -- n ) in-amp-caps h# 7f and ; +: in-steps/dB ( -- #steps ) in-step-size 4 * ; + +: .input-amp ( -- ) + ." gain steps: " in-gain-steps . cr + ." left gain: " false true gain/mute swap . if ." (muted)" then cr + ." right gain: " false false gain/mute swap . if ." (muted)" then cr +; + +\ LICENSE_BEGIN +\ Copyright (c) 2009 Luke Gorrie <luke(a)bup.co.nz> +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END Added: dev/hdaudio/hdaudio.bth =================================================================== --- dev/hdaudio/hdaudio.bth (rev 0) +++ dev/hdaudio/hdaudio.bth 2009-06-10 17:26:33 UTC (rev 1221) @@ -0,0 +1,19 @@ +purpose: Load file for Intel HDAudio interface + +command: &tokenize &this +build-now + +silent on + +begin-tokenizing hdaudio.fc + +FCode-version2 +fload ${BP}/dev/hdaudio/core.fth +fload ${BP}/dev/hdaudio/conexant.fth +fload ${BP}/dev/hdaudio/audio.fth +fload ${BP}/dev/hdaudio/extra.fth +fload ${BP}/forth/lib/isin.fth +fload ${BP}/dev/geode/ac97/selftest.fth +end0 + +end-tokenizing

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openfirmware June 2009