September 2011 - openfirmware - mail.coreboot.org

[commit] r2505 - dev/olpc/mmp2camera
by repository service Sept. 12, 2011

Sept. 12, 2011

Author: quozl Date: Mon Sep 12 04:06:15 2011 New Revision: 2505 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2505 Log: OLPC XO-1.75 B1 - move CAM_RST from GPIO 73 to GPIO 102, silently breaks camera test validity on A3, restores camera test validity on B1, fixes "EDI byte in timeout" failure reported by " flash-ec " after " test /camera " on B1 with R92 removed, requires cforth 17efd8f, see #11227 Modified: dev/olpc/mmp2camera/platform.fth Modified: dev/olpc/mmp2camera/platform.fth ============================================================================== --- dev/olpc/mmp2camera/platform.fth Fri Sep 9 03:48:38 2011 (r2504) +++ dev/olpc/mmp2camera/platform.fth Mon Sep 12 04:06:15 2011 (r2505) @@ -13,7 +13,7 @@ h# 42 to smb-slave ; -: reset-sensor ( -- ) d# 73 gpio-clr 1 ms d# 73 gpio-set ; +: reset-sensor ( -- ) d# 102 gpio-clr 1 ms d# 102 gpio-set ; [ifdef] cl2-a1 : sensor-power-on ( -- ) d# 145 gpio-set ;

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[commit] r2504 - cpu/arm/olpc/1.75
by repository service Sept. 9, 2011

Sept. 9, 2011

Author: wmb Date: Fri Sep 9 03:48:38 2011 New Revision: 2504 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2504 Log: OLPC XO-1.75 - automatically pull and build cforth in a subdirectory of the OFW build directory. Added: cpu/arm/olpc/1.75/cforth-version.fth cpu/arm/olpc/1.75/cforth.bth Modified: cpu/arm/olpc/1.75/olpc.bth Added: cpu/arm/olpc/1.75/cforth-version.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/olpc/1.75/cforth-version.fth Fri Sep 9 03:48:38 2011 (r2504) @@ -0,0 +1,15 @@ +\ This file controls which CForth source version to include in the OFW build +\ and the method for fetching it + +\ If CFORTH_VERSION is "modify", the repository will be cloned with git+ssh: so can push changes. +\ You need ssh access to the server. +\ macro: CFORTH_VERSION modify + +\ If CFORTH_VERSION is "clone", the repository will be cloned with git:. You won't be able to +\ push changes, but you will get the full metadata so you can use commands like git grep. +\ You don't need ssh access to the server. +\ macro: CFORTH_VERSION clone + +\ Otherwise, the source code will be will be downloaded as a tarball via gitweb. +\ macro: CFORTH_VERSION 59859f04454bc2574ab68cf0fd76ebdbc5f26fb6 +macro: CFORTH_VERSION HEAD Added: cpu/arm/olpc/1.75/cforth.bth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/olpc/1.75/cforth.bth Fri Sep 9 03:48:38 2011 (r2504) @@ -0,0 +1,42 @@ +purpose: Fetch and compile CForth for the Security Processor + +command: &builder &this +build-now + +fload ${BP}/cpu/arm/olpc/1.75/cforth-version.fth + +macro: CFORTH_BUILD_DIR cforth/build/arm-xo-1.75 + +\ Don't re-fetch the cforth source, thus preventing overwrites of development modifications. +\ If you change cforth-version.fth to specify a different cforth source version, you must +\ manually delete the old cforth subtree. + +" ${CFORTH_BUILD_DIR}/Makefile" expand$ $file-exists? 0= [if] + " ${CFORTH_VERSION}" expand$ " modify" $= [if] + " git clone -q git+ssh://dev.laptop.org/git/users/wmb/cforth" expand$ $sh + [else] + " ${CFORTH_VERSION}" expand$ " clone" $= [if] + " git clone -q git://dev.laptop.org/users/wmb/cforth" expand$ $sh + [else] + " wget -q -O - http://dev.laptop.org/git/users/wmb/cforth/snapshot/cforth-${CFORTH_VERSION… | tar xfz -" expand$ $sh + " mv cforth-${CFORTH_VERSION} cforth" expand$ $sh + " wget -q -O - http://dev.laptop.org/git/users/wmb/cforth/patch | head -1 | cut -f 2 -d ' ' >>${CFORTH_BUILD_DIR}/version" expand$ $sh + \ " echo -n const char cforth_version[] = '""' >${CFORTH_BUILD_DIR}/cforth_version.c" expand$ $sh + \ " wget -q -O - http://dev.laptop.org/git/users/wmb/cforth/patch | head -1 | cut -f 2 -d ' ' >>${CFORTH_BUILD_DIR}/cforth_version.c" expand$ $sh + \ " echo '"";' >>${CFORTH_BUILD_DIR}/cforth_version.c" expand$ $sh + [then] + [then] +[then] + +" (cd ${CFORTH_BUILD_DIR}; make --no-print-directory)" expand$ $sh + +\ If the above make changed either cforth.img or shim.img, copy the new one into this directory, +\ thus triggering a rebuild of the OFW .rom file + +" cforth.img" modtime " ${CFORTH_BUILD_DIR}/cforth.img" expand$ modtime < [if] + " (cp ${CFORTH_BUILD_DIR}/cforth.img .)" expand$ $sh +[then] + +" shim.img" modtime " ${CFORTH_BUILD_DIR}/shim.img" expand$ modtime < [if] + " (cp ${CFORTH_BUILD_DIR}/shim.img .)" expand$ $sh +[then] Modified: cpu/arm/olpc/1.75/olpc.bth ============================================================================== --- cpu/arm/olpc/1.75/olpc.bth Sat Sep 3 17:55:57 2011 (r2503) +++ cpu/arm/olpc/1.75/olpc.bth Fri Sep 9 03:48:38 2011 (r2504) @@ -15,6 +15,7 @@ in: ${BP}/dev/usb2/device/storage/build/usbstorage.fc in: testicons.bin in: ${BP}/clients/emacs/arm/emacs +in: cforth.img build-now fload ${BP}/cpu/arm/olpc/1.75/fw-version.fth @@ -48,8 +49,8 @@ \ Main Processor code loaded into DRAM image: OBMI 800 d101c000 ${BP}/cpu/arm/olpc/1.75/dummy.img \ Secure Processor code loaded into SRAM -image: WTMI 1000 d1018000 ${BP}/../cforth/build/arm-xo-1.75/shim.img -image: CFTH 2000 d1000000 ${BP}/../cforth/build/arm-xo-1.75/app.img +image: WTMI 1000 d1018000 shim.img +image: CFTH 2000 d1000000 cforth.img \ anonymous: 20000 ${BP}/cpu/arm/olpc/1.75/build/fw.img reserved: \ fload ${BP}/cpu/arm/olpc/1.75/ddr_samsung_1g.fth

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[commit] r2503 - cpu/arm/olpc/1.75
by repository service Sept. 3, 2011

Sept. 3, 2011

Author: rsmith Date: Sat Sep 3 17:55:57 2011 New Revision: 2503 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2503 Log: Q4B09 Modified: cpu/arm/olpc/1.75/fw-version.fth Modified: cpu/arm/olpc/1.75/fw-version.fth ============================================================================== --- cpu/arm/olpc/1.75/fw-version.fth Fri Sep 2 22:23:04 2011 (r2502) +++ cpu/arm/olpc/1.75/fw-version.fth Sat Sep 3 17:55:57 2011 (r2503) @@ -1,3 +1,3 @@ \ The overall firmware revision macro: FW_MAJOR B -macro: FW_MINOR 08 +macro: FW_MINOR 09

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[commit] r2502 - cpu/arm/olpc/1.75
by repository service Sept. 2, 2011

Sept. 2, 2011

Author: wmb Date: Fri Sep 2 22:23:04 2011 New Revision: 2502 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2502 Log: OLPC XO-1.75 - when reprogramming the EC FLASH, skip the page that contains the EC configuration flags. Modified: cpu/arm/olpc/1.75/ecflash.fth cpu/arm/olpc/1.75/edi.fth Modified: cpu/arm/olpc/1.75/ecflash.fth ============================================================================== --- cpu/arm/olpc/1.75/ecflash.fth Fri Sep 2 21:22:45 2011 (r2501) +++ cpu/arm/olpc/1.75/ecflash.fth Fri Sep 2 22:23:04 2011 (r2502) @@ -46,7 +46,6 @@ load-base /ec-flash + /ec-flash 0 " read-flash" $call-ec [else] use-edi-spi edi-open - ." Erasing ..." erase-chip cr ." Writing ..." load-base /ec-flash 0 edi-program-flash cr ." Verifying ..." load-base /ec-flash + /ec-flash 0 edi-read-flash Modified: cpu/arm/olpc/1.75/edi.fth ============================================================================== --- cpu/arm/olpc/1.75/edi.fth Fri Sep 2 21:22:45 2011 (r2501) +++ cpu/arm/olpc/1.75/edi.fth Fri Sep 2 22:23:04 2011 (r2502) @@ -131,13 +131,17 @@ h# 70 flash-cmd ( ) wait-flash-busy ( ) ; +h# 7e80 constant ec-flags-offset : edi-program-flash ( adr len offset -- ) - cr - swap 0 ?do - (cr i . - over i + over i + edi-program-page ( adr offset ) - /flash-page +loop ( adr offset ) - 2drop ( ) + cr ( adr len offset ) + swap 0 ?do ( adr offset ) + (cr i . ( adr offset ) + dup i + ec-flags-offset <> if ( adr offset ) + dup i + erase-page ( adr offset ) + over i + over i + edi-program-page ( adr offset ) + then ( adr offset ) + /flash-page +loop ( adr offset ) + 2drop ( ) ; : edi-read-flash ( adr len offset -- ) over 0= if 3drop exit then ( adr len offset )

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[commit] r2501 - cpu/arm
by repository service Sept. 2, 2011

Sept. 2, 2011

Author: wmb Date: Fri Sep 2 21:22:45 2011 New Revision: 2501 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2501 Log: ARM - deleted obsolete ARM_RAMDISK atag Modified: cpu/arm/linux.fth Modified: cpu/arm/linux.fth ============================================================================== --- cpu/arm/linux.fth Fri Sep 2 19:37:19 2011 (r2500) +++ cpu/arm/linux.fth Fri Sep 2 21:22:45 2011 (r2501) @@ -61,12 +61,6 @@ 0 tag-l, \ start_address /ramdisk if - 5 tag-l, \ size - h# 54410004 tag-l, \ ATAG_RAMDISK - 0 tag-l, \ load flag == 0 - d# 4096 tag-l, \ 4k kilobytes = 4 megabytes (calculate dynamically?) - 0 tag-l, \ unused floppy block number - 4 tag-l, h# 54420005 tag-l, \ ATAG_INITRD2 ramdisk-adr >physical tag-l, \ physical starting address

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[commit] r2500 - dev/olpc/keyboard
by repository service Sept. 2, 2011

Sept. 2, 2011

Author: wmb Date: Fri Sep 2 19:37:19 2011 New Revision: 2500 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2500 Log: OLPC keyboard selftest improvements for the case where the SP manages PS/2 and handles game buttons. Modified: dev/olpc/keyboard/selftest.fth Modified: dev/olpc/keyboard/selftest.fth ============================================================================== --- dev/olpc/keyboard/selftest.fth Fri Sep 2 19:35:05 2011 (r2499) +++ dev/olpc/keyboard/selftest.fth Fri Sep 2 19:37:19 2011 (r2500) @@ -575,6 +575,9 @@ false ; +" name" parent-device get-package-property drop decode-string ( name$ ) +" ec-spi" $= [if] + \ For XO-1.75, the game buttons are connected directly to the CPU SoC, \ instead of going through the EC. To preserve the rest of the test \ logic, we generate a stream of up-down events from the game button @@ -664,18 +667,19 @@ then ( false | scancode true ) ; -0 value ec-spi-buttons? - \ Check for a change in button state if necessary. : or-button? ( [scancode] key? -- [scancode] flag ) \ If there is already a key from get-data?, handle it before checking the game buttons - dup if exit then ( false ) + ?dup if exit then ( ) \ If the /ec-spi device node is present, the game buttons are directly connected \ so we must handle them here. Otherwise the EC will handle them and fold their \ events into the keyboard scancode stream. - ec-spi-buttons? if drop button-event? then + button-event? ; +[else] +alias or-button? noop immediate +[then] 0 value last-timestamp : selftest-keys ( -- ) @@ -728,13 +732,6 @@ : selftest ( -- error? ) open 0= if true exit then - " /ec-spi" locate-device if ( ) - false ( flag ) - else ( phandle ) - drop true ( flag ) - then ( flag ) - to ec-spi-buttons? ( ) - set-keyboard-type make-keys

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[commit] r2499 - cpu/arm/olpc/1.75
by repository service Sept. 2, 2011

Sept. 2, 2011

Author: wmb Date: Fri Sep 2 19:35:05 2011 New Revision: 2499 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2499 Log: OLPC XO-1.75 - changes in convenience commands like "newrom" to match my new network setup. Modified: cpu/arm/olpc/1.75/fw.bth Modified: cpu/arm/olpc/1.75/fw.bth ============================================================================== --- cpu/arm/olpc/1.75/fw.bth Fri Sep 2 19:32:54 2011 (r2498) +++ cpu/arm/olpc/1.75/fw.bth Fri Sep 2 19:35:05 2011 (r2499) @@ -518,10 +518,10 @@ ; : newrom - " flash! http:\\10.20.0.14\~wmb\new.rom" eval + " flash! http:\\10.20.0.14\new.rom" eval ; : newec - " flash-ec http:\\10.20.0.14\~wmb\ecimage.bin" eval + " flash-ec http:\\10.20.0.14\ecimage.bin" eval ; : qz " qz" $essid " http:\\qz\" included \ qa test bed scripting, james cameron

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[commit] r2498 - cpu/arm/olpc/1.75
by repository service Sept. 2, 2011

Sept. 2, 2011

Author: wmb Date: Fri Sep 2 19:32:54 2011 New Revision: 2498 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2498 Log: OLPC XO-1.75 - removed some more boring startup messages. Modified: cpu/arm/olpc/1.75/devices.fth cpu/arm/olpc/1.75/emmc.fth Modified: cpu/arm/olpc/1.75/devices.fth ============================================================================== --- cpu/arm/olpc/1.75/devices.fth Fri Sep 2 19:26:52 2011 (r2497) +++ cpu/arm/olpc/1.75/devices.fth Fri Sep 2 19:32:54 2011 (r2498) @@ -36,7 +36,6 @@ : stand-init-io ( -- ) stand-init-io inituarts install-uart-io - ." UART installed" cr ; warning on Modified: cpu/arm/olpc/1.75/emmc.fth ============================================================================== --- cpu/arm/olpc/1.75/emmc.fth Fri Sep 2 19:26:52 2011 (r2497) +++ cpu/arm/olpc/1.75/emmc.fth Fri Sep 2 19:32:54 2011 (r2498) @@ -1,6 +1,5 @@ \ XXX do we need to set the internal SD for fast drive in boardgpio.fth ? : select-internal-sd ( -- ) - ." Using internal SD" cr h# 18c3 d# 113 af! \ SD_CMD h# 18c3 d# 126 af! \ SD_DATA2 h# 18c3 d# 127 af! \ SD_DATA0 @@ -19,7 +18,6 @@ h# c1 d# 168 af! \ eMMC_D1 as GPIO ; : select-emmc ( -- ) - ." Using eMMC" cr h# c1 d# 113 af! \ SD_CMD as GPIO h# c1 d# 126 af! \ SD_DATA2 as GPIO h# c0 d# 127 af! \ SD_DATA0 as GPIO

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[commit] r2497 - cpu/arm
by repository service Sept. 2, 2011

Sept. 2, 2011

Author: wmb Date: Fri Sep 2 19:26:52 2011 New Revision: 2497 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2497 Log: ARM - fixes to initrd loading found by Daniel Drake. Modified: cpu/arm/linux.fth Modified: cpu/arm/linux.fth ============================================================================== --- cpu/arm/linux.fth Fri Sep 2 09:02:34 2011 (r2496) +++ cpu/arm/linux.fth Fri Sep 2 19:26:52 2011 (r2497) @@ -31,17 +31,11 @@ + ( limit ) ; -: add-root-dev ( cmdline$ -- cmdline$' ) - /ramdisk if ( cmdline$ ) - " root=/dev/ram0" $cat2 ( cmdline$' ) - then ( cmdline$ ) -; - \ see http://www.simtec.co.uk/products/SWLINUX/files/booting_article.html 0 value arm-linux-machine-type \ Set this after loading this file h# 100 value linux-params \ The location recommended by the above article -def-load-base value linux-base +h# 10.0000 value linux-base 0 value rootdev# \ Set externally 0 value tag-adr @@ -74,13 +68,12 @@ 0 tag-l, \ unused floppy block number 4 tag-l, - h# 54420005 tag-l, \ ATAG_RAMDISK2 + h# 54420005 tag-l, \ ATAG_INITRD2 ramdisk-adr >physical tag-l, \ physical starting address /ramdisk tag-l, \ size of compressed ramdisk in bytes then \ Command line - ( cmdline$ ) add-root-dev ( cmdline$ ) ( adr len ) dup if ( adr len ) 1+ 4 round-up ( adr len+null_rounded ) @@ -121,7 +114,7 @@ : linux-place-ramdisk ( adr len -- ) to /ramdisk ( adr ) - memory-limit umin /ramdisk - ( adr new-ramdisk-adr ) + dup memory-limit umin /ramdisk - ( adr new-ramdisk-adr ) tuck /ramdisk move ( new-ramdisk-adr ) \ dup to linux-memtop to ramdisk-adr

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[commit] r2496 - in cpu/arm: . mmp2 olpc/1.75
by repository service Sept. 2, 2011

Sept. 2, 2011

Author: wmb Date: Fri Sep 2 09:02:34 2011 New Revision: 2496 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2496 Log: OLPC XO-1.75 - checkpoint current state of low-power test code. Modified: cpu/arm/assem.fth cpu/arm/mmp2/dramrecal.fth cpu/arm/olpc/1.75/addrs.fth Modified: cpu/arm/assem.fth ============================================================================== --- cpu/arm/assem.fth Wed Aug 31 10:31:46 2011 (r2495) +++ cpu/arm/assem.fth Fri Sep 2 09:02:34 2011 (r2496) @@ -1401,7 +1401,7 @@ : sev ( -- ) 0320f004 {cond} op( )op ; : nop ( -- ) e1a00000 {} op( )op ; \ mov r0,r0 -: dsb ( -- ) f57ff040 {} op( )op ; \ "dsb sy" is f57ff04f +: dsb ( -- ) f57ff04f {} op( )op ; \ "dsb" is equivalent to "dsb sy" - f57ff04f : dmb ( -- ) f57ff050 {} op( )op ; : isb ( -- ) f57ff060 {} op( )op ; Modified: cpu/arm/mmp2/dramrecal.fth ============================================================================== --- cpu/arm/mmp2/dramrecal.fth Wed Aug 31 10:31:46 2011 (r2495) +++ cpu/arm/mmp2/dramrecal.fth Fri Sep 2 09:02:34 2011 (r2496) @@ -72,25 +72,22 @@ \ orr r1, r1, #0x000a \ ODT{1,0}_SWITCH_MODE: Termination controlled by Read and Write enables \ str r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 -[ifdef] notdef +\ Store registers in SRAM so CForth can see them, for debugging +\ set r2, #0xd102.0400 +\ stmia r2, {r0-r15} + + \ Linux sets the register to 0x860 ldr r1, [r0, #0x1e0] \ PHY_CTRL8 bic r1,r1,#0x07700000 \ PHY_ADCM_ZPDRV: 0 PHY_ADCM_ZNDRV: 0 (Disable drivers 6:0) str r1, [r0, #0x1e0] \ PHY_CTRL8 -[then] - set r2, #0xfe086000 - set r3, #0xfe050000 - str r2, [r3] \ Final write to SP votes - - mcr p15,0,r0,7,10,4 \ Data Synchronization Barrier -\ dsb \ Data Synchronization Barrier + dsb \ Data Synchronization Barrier wfi \ Wait for interrupt -[ifdef] notdef + \ Linux sets the register to 0x07700860, hardcoding the drive strength ldr r1, [r0, #0x1e0] \ PHY_CTRL8 orr r1,r1,#0x07700000 \ PHY_ADCM_ZPDRV: 7 PHY_ADCM_ZNDRV: 7 (Enable drivers 6:0) str r1, [r0, #0x1e0] \ PHY_CTRL8 -[then] \ This block was commented-out in the Linux code, and the value is incorrect for OLPC in any case \ mov r1, #0x02000000 \ PAD_TERM_SWITCH_MODE: Termination enabled during all reads @@ -100,11 +97,11 @@ mov r1, #0x80000000 \ PHY_SYNC_EN str r1, [r0, #0x240] \ PHY_CTRL14 - ldr r1, [r0, #230] \ PHY_CTRL13 + ldr r1, [r0, #0x230] \ PHY_CTRL13 orr r1,r1,#0xf0000000 \ DLL_RESET_TIMER: 15*256 memory clocks \ mov r1, #0xf0000000 \ DLL_RESET_TIMER: 15*256 memory clocks \ orr r1, r1, #0x0040 \ DLL_PHSEL: 4 (45 + 4*3 = 57 degrees) - adjust? - str r1, [r0, #230] \ PHY_CTRL13 + str r1, [r0, #0x230] \ PHY_CTRL13 mov r1, #0x20000000 \ PHY_DLL_RESET str r1, [r0, #0x240] \ PHY_CTRL14 @@ -168,8 +165,11 @@ code do-self-refresh ( -- ) set r0,`memctrl-va #` \ Memory controller virtual address set r1,`'ddr-self-refresh #` \ Address of ddr-self-refresh routine in SRAM + mov r7,sp + set sp,`'ddr-self-refresh-sp #` mov lr,pc mov pc,r1 + mov sp,r7 c; : +apbc ( offset -- io-offset ) h# 01.5000 + ; @@ -217,16 +217,28 @@ h# f0 h# 1c +scu io-clr \ SCU_MCB_CONF ; : disable-apmu-clks ( -- ) - h# 3f h# d8 +apmu io-clr \ PMUA_MSPRO_CLK_RES_CTRL - h# 1fffd h# dc +apmu io-clr \ PMUA_GLB_CLK_RES_CTRL -\ 0 h# 68 +apmu io! \ PMUA_WTM_CLK_RES_CTRL - h# 9 h# 5c +apmu io-clr \ PMUA_USB_CLK_RES_CTRL + h# 1b h# 54 +apmu io-clr \ PMUA_SDH0_CLK_RES_CTRL + h# 1b h# 58 +apmu io-clr \ PMUA_SDH1_CLK_RES_CTRL + h# 1b h# e8 +apmu io-clr \ PMUA_SDH2_CLK_RES_CTRL + h# 1b h# d4 +apmu io-clr \ PMUA_SMC_CLK_RES_CTRL + h# 3f h# 60 +apmu io-clr \ PMUA_NF_CLK_RES_CTRL + h# 3f h# d8 +apmu io-clr \ PMUA_MSPRO_CLK_RES_CTRL - XO does not use MSPRO + h# 12 h# 10c +apmu io-clr \ PMUA_AUDIO_CLK_RES_CTRL + h# 1fffd h# dc +apmu io-clr \ PMUA_GLB_CLK_RES_CTRL +\ 0 h# 68 +apmu io! \ PMUA_WTM_CLK_RES_CTRL + h# 9 h# 5c +apmu io-clr \ PMUA_USB_CLK_RES_CTRL ; : enable-apmu-clks ( -- ) - h# 3f h# d8 +apmu io-set \ PMUA_MSPRO_CLK_RES_CTRL - h# 1fffd h# dc +apmu io-set \ PMUA_GLB_CLK_RES_CTRL -\ h# 1b h# 68 +apmu io! \ PMUA_WTM_CLK_RES_CTRL - h# 9 h# 5c +apmu io-set \ PMUA_USB_CLK_RES_CTRL + h# 1b h# 54 +apmu io-set \ PMUA_SDH0_CLK_RES_CTRL + h# 1b h# 58 +apmu io-set \ PMUA_SDH1_CLK_RES_CTRL + h# 1b h# e8 +apmu io-set \ PMUA_SDH2_CLK_RES_CTRL + h# 1b h# d4 +apmu io-set \ PMUA_SMC_CLK_RES_CTRL \ ??? what is this and why is it on? + h# 3f h# 60 +apmu io-set \ PMUA_NF_CLK_RES_CTRL \ Should this be on? +\ h# 3f h# d8 +apmu io-set \ PMUA_MSPRO_CLK_RES_CTRL + h# 12 h# 10c +apmu io-set \ PMUA_AUDIO_CLK_RES_CTRL + h# 1fffd h# dc +apmu io-set \ PMUA_GLB_CLK_RES_CTRL +\ h# 1b h# 68 +apmu io! \ PMUA_WTM_CLK_RES_CTRL + h# 9 h# 5c +apmu io-set \ PMUA_USB_CLK_RES_CTRL ; : disable-mpmu-clks ( -- ) h# a010 h# 1024 +mpmu io! \ MPMU_ACGR @@ -310,9 +322,37 @@ save-apcr h# 1000 +mpmu io! ( ) \ Restore APCR save-idlecfg h# 18 +apmu io! ( ) \ Restore IDLE_CFG ; +\ Questions: +\ Meaning of various connect type options +\ do LP mode settings take effect immediately if SP is already at WFI, or only on entry to WFI +\ does WFI make any difference on SP? I don't see any difference in power +\ Which WFI instruction on SP? +\ Which WFI instruction on PJ4? +\ Any undocumented bits that affect the situation? +\ What are the _INT versions of the XDB config files? +\ What does CS stand for in ARM/CS ? +\ When using XDB on XO with OFW, XDB can see entry to LP state - core Status stays running - LowPower Internal +\ How to recapture short of restarting XDB? +\ Pushing button on JTAG box often seems to have no effect + : setup-sleep-state ( -- ) \ begin mmp2_pm_enter_lowpower_mode(state) + \ Security processor setup + sleep-depth 4 >= if \ state at least POWER_MODE_CHIP_SLEEP (turn off most of SoC) + h# fe08.6000 0 +mpmu io! \ In SP, set AXISD, resvd, SLPEN, SPSD, DDRCORSD, APBSD resvd, VCXOSD + then + + sleep-depth 3 = if \ state at least POWER_MODE_APPS_SLEEP (turn off slow IO) + h# de00.6000 0 +mpmu io! \ In SP, set AXISD, resvd, SPSD, DDRCORSD, APBSD resvd, + then + +\ Linux value +\ h# 8030.0020 h# 14 +apmu io! \ IN PMUA_SP_IDLE_CFG, set , DIVIDER_RESET_EN, SP_DIS_MC_SW_REQ, SP_MC_WAKE_EN, TCM_STATE_RETAIN + h# 8020.0020 h# 14 +apmu io! \ IN PMUA_SP_IDLE_CFG, set , DIVIDER_RESET_EN, SP_DIS_MC_SW_REQ, TCM_STATE_RETAIN + + \ PJ4 setup + h# 1000 +mpmu io@ to save-apcr h# 18 +apmu io@ to save-idlecfg @@ -323,28 +363,23 @@ h# 0008.0000 or ( apcr' ) \ Set VCXOSD then - h# 2000.0000 0 +mpmu io-clr \ In SP, clear SLPEN - we might set it later - sleep-depth 4 >= if \ state at least POWER_MODE_CHIP_SLEEP (turn off most of SoC) - h# 2008.0000 0 +mpmu io-set \ In SP, also set SLPEN, VCXOSD h# 2000.0000 or ( apcr' ) \ Set SLPEN setup-wakeup-sources and ( apcr' ) then sleep-depth 3 >= if \ state at least POWER_MODE_APPS_SLEEP (turn off slow IO) - h# de00.0000 0 +mpmu io-set \ In SP, set AXISD, resvd, SPSD, DDRCORSD, APBSD resvd, h# 0400.0000 or ( apcr' ) \ Set APBSD then - h# 8030.0020 h# 14 +apmu io! ( apcr ) \ IN PMUA_SP_IDLE_CFG, set , DIVIDER_RESET_EN, SP_DIS_MC_SW_REQ, SP_MC_WAKE_EN, TCM_STATE_RETAIN - sleep-depth 2 >= if \ state at least POWER_MODE_APPS_IDLE (turn off fast IO and DDR) h# 8800.0000 or ( apcr' ) \ Set AXISD, DDRCORSD then h# 5200.0000 or ( apcr' ) \ Set DSPSD (bit 30, reserved), SPSD (bit 28), BBSD (bit 25, resvd) - save-idlecfg 1 invert and ( apcr idle ) \ PMUA_MOH_IDLE + save-idlecfg 2 invert and ( apcr idle ) \ Clear PMUA_MOH_IDLE (AKA PJ_IDLE) +\ h# 8000.0000 invert and ( apcr idle' ) \ Clear PJ_DBG_CLOCK_EN sleep-depth 2 >= if \ state at least POWER_MODE_APPS_IDLE h# 0000.0020 or ( apcr idle' ) \ PJ_PWRDWN @@ -352,7 +387,7 @@ sleep-depth 1 >= if \ state at least POWER_MODE_CORE_EXTIDLE h# 3000.0000 invert and ( apcr idle' ) \ PJ_ISO_MODE_CNTRL - isolation controlled by processor logic and active - h# 000a.0000 or ( apcr idle' ) \ 2 L2 power switches, 1 L1 power switch, 3 core power switches + h# 000a.0002 or ( apcr idle' ) \ 2 L2 power switches, 1 L1 power switch, 3 core power switches then h# 0020.0000 or ( apcr idle' ) \ PJ_DIS_MC_SW_REQ - disable idle entry using software register bits @@ -376,7 +411,16 @@ : stdin-idle-on ['] safe-idle to stdin-idle d# 15 enable-interrupt ; : stdin-idle-off ['] noop to stdin-idle install-uart-io d# 15 disable-interrupt ; +: timers-off ( -- ) + 0 h# 14048 io! \ Disable interrupts from the tick timer + 7 h# 1407c io! \ Clear any pending interrupts + h# f disable-interrupt \ Block timer interrupt +; + : str ( -- ) + timers-off + + screen-dark stdin-idle-off 5 h# 38 +mpmu io! \ Use 32 kHz clock instead of VCXO for slow clock @@ -391,7 +435,7 @@ setup-sleep-state -\ h# 00c0.0000 h# 8c +apmu io-set \ Power down CoreSight SRAM + h# 000c.0000 h# 8c +apmu io-set \ Power down CoreSight SRAM \ TODO - need to power down sram/l2$ \ mmp2_cpu_disable_l2(0); @@ -402,7 +446,7 @@ disable-clks \ begin mmp2_cpu_do_idle() - block-irqs ( ) \ Block IRQs - will be cleared by PMU + block-irqs ( ) \ Block IRQs - will be cleared by PMU do-self-refresh ( ) restore-run-state Modified: cpu/arm/olpc/1.75/addrs.fth ============================================================================== --- cpu/arm/olpc/1.75/addrs.fth Wed Aug 31 10:31:46 2011 (r2495) +++ cpu/arm/olpc/1.75/addrs.fth Fri Sep 2 09:02:34 2011 (r2496) @@ -71,5 +71,6 @@ sram-va h# 2.0000 + constant 'ddr-recal sram-va h# 2.0100 + constant 'ddr-self-refresh +sram-va h# 2.0400 + constant 'ddr-self-refresh-sp sram-pa h# 2.4000 + constant diagfb-pa \ Low-resolution frame buffer for startup numbers

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