September 2011 - openfirmware - mail.coreboot.org

[commit] r2545 - in clients: emacs/arm lib/arm
by repository service Sept. 28, 2011

Sept. 28, 2011

Author: pgf Date: Wed Sep 28 23:22:57 2011 New Revision: 2545 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2545 Log: allow use of $CROSS to locate cross-compiler default path to cross-compiler in /usr/local/arm is unchanged if CROSS is unset. Modified: clients/emacs/arm/Makefile clients/lib/arm/makefile Modified: clients/emacs/arm/Makefile ============================================================================== --- clients/emacs/arm/Makefile Wed Sep 28 03:06:17 2011 (r2544) +++ clients/emacs/arm/Makefile Wed Sep 28 23:22:57 2011 (r2545) @@ -6,10 +6,12 @@ ifneq (arm, $(findstring arm,$(shell uname -p))) # Cross-compiler setup - TOOLPREFIX=/usr/local/arm/bin/arm-linux- - CC=$(TOOLPREFIX)gcc - LD=$(TOOLPREFIX)ld - STRIP=$(TOOLPREFIX)strip +ifeq ($(CROSS),) + CROSS=/usr/local/arm/arm-linux/bin/ +endif + CC := $(CROSS)gcc + LD := $(CROSS)ld + STRIP := $(CROSS)strip else CC := gcc STRIP := strip Modified: clients/lib/arm/makefile ============================================================================== --- clients/lib/arm/makefile Wed Sep 28 03:06:17 2011 (r2544) +++ clients/lib/arm/makefile Wed Sep 28 23:22:57 2011 (r2545) @@ -4,11 +4,11 @@ # functions that conflict with gcc builtins ifneq (arm, $(findstring arm,$(shell uname -p))) - # Cross-compiler setup - ARCH := /usr/local/arm - UTILS := $(ARCH)/arm-linux/bin - CC := $(UTILS)/gcc - LD := $(UTILS)/ld +ifeq ($(CROSS),) + CROSS=/usr/local/arm/arm-linux/bin/ +endif + CC := $(CROSS)gcc + LD := $(CROSS)ld else CC := gcc endif

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[commit] r2544 - cpu/arm/mmp2
by repository service Sept. 28, 2011

Sept. 28, 2011

Author: wmb Date: Wed Sep 28 03:06:17 2011 New Revision: 2544 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2544 Log: OLPC XO-1.75 - suspend/resume test4 improvements - slightly longer cycle time to ensure at least one whole clock tick, display power info. Modified: cpu/arm/mmp2/rtc.fth Modified: cpu/arm/mmp2/rtc.fth ============================================================================== --- cpu/arm/mmp2/rtc.fth Wed Sep 28 03:04:52 2011 (r2543) +++ cpu/arm/mmp2/rtc.fth Wed Sep 28 03:06:17 2011 (r2544) @@ -48,7 +48,7 @@ int5-mask@ 1 invert and int5-mask! \ Unmask alarm enable-rtc-wakeup - 0 soc-rtc@ d# 1 + 4 soc-rtc! \ Set alarm for 3 seconds from now + 0 soc-rtc@ d# 2 + 4 soc-rtc! \ Set alarm for 2 seconds from now 7 8 soc-rtc! \ Ack old interrupts and enable new ones ['] cancel-alarm 5 interrupt-handler! 5 enable-interrupt @@ -91,15 +91,15 @@ key? until ; : test4 - begin - 0 d# 13 at-xy + d# 1000000 0 do + 0 d# 13 at-xy i .d 5 0 do - wake1 str cr i . + wake1 strp d# 500 ms - key? if unloop exit then + key? if unloop unloop exit then loop - again + 5 +loop ; \ test3

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[commit] r2543 - in cpu: arm/olpc/1.75 x86/pc/olpc/via
by repository service Sept. 28, 2011

Sept. 28, 2011

Author: wmb Date: Wed Sep 28 03:04:52 2011 New Revision: 2543 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2543 Log: OLPC XO-1.75 and XO-1.5 - use new version of multicast-nand tree to pick up a Makefile change. Modified: cpu/arm/olpc/1.75/mcnand-version.fth cpu/x86/pc/olpc/via/mcnand-version.fth Modified: cpu/arm/olpc/1.75/mcnand-version.fth ============================================================================== --- cpu/arm/olpc/1.75/mcnand-version.fth Wed Sep 28 03:02:22 2011 (r2542) +++ cpu/arm/olpc/1.75/mcnand-version.fth Wed Sep 28 03:04:52 2011 (r2543) @@ -3,6 +3,6 @@ \ With a specific ID, mcastnand.bth will download a tarball without .git stuff. \ With "test", mcastnand.bth will clone the git head if build/multicast-nand/ \ is not already present, then you can modify the git subtree as needed. -macro: MCNAND_VERSION 6c53cac2dba11d6d0f0a6d7607b2f831d566356b +macro: MCNAND_VERSION 60b7230fcfb4abd42c3274475b5447e0bc344a5b \ macro: MCNAND_VERSION test \ macro: MCNAND_VERSION HEAD Modified: cpu/x86/pc/olpc/via/mcnand-version.fth ============================================================================== --- cpu/x86/pc/olpc/via/mcnand-version.fth Wed Sep 28 03:02:22 2011 (r2542) +++ cpu/x86/pc/olpc/via/mcnand-version.fth Wed Sep 28 03:04:52 2011 (r2543) @@ -3,6 +3,6 @@ \ With a specific ID, mcastnand.bth will download a tarball without .git stuff. \ With "test", mcastnand.bth will clone the git head if build/multicast-nand/ \ is not already present, then you can modify the git subtree as needed. -macro: MCNAND_VERSION 059bd03137c19d67a28c67665c4ce50fd5d35565 +macro: MCNAND_VERSION 60b7230fcfb4abd42c3274475b5447e0bc344a5b \ macro: MCNAND_VERSION test \ macro: MCNAND_VERSION HEAD

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[commit] r2542 - cpu/arm/olpc/1.75
by repository service Sept. 28, 2011

Sept. 28, 2011

Author: wmb Date: Wed Sep 28 03:02:22 2011 New Revision: 2542 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2542 Log: OLPC XO-1.75 - Changed audio driver to use audio PLL instead of I2SCLOCK at Marvell's recommendation. Modified: cpu/arm/olpc/1.75/sound.fth Modified: cpu/arm/olpc/1.75/sound.fth ============================================================================== --- cpu/arm/olpc/1.75/sound.fth Wed Sep 28 03:00:13 2011 (r2541) +++ cpu/arm/olpc/1.75/sound.fth Wed Sep 28 03:02:22 2011 (r2542) @@ -9,40 +9,63 @@ : adma! ( n offset -- ) adma-base + rl! ; : adma@ ( offset -- n ) adma-base + rl@ ; -: audio-clock-on ( -- ) - h# 600 h# 28.290c io! d# 10 us \ Enable - h# 610 h# 28.290c io! d# 10 us \ Release reset - h# 710 h# 28.290c io! d# 10 us \ Enable - h# 712 h# 28.290c io! d# 10 us \ Release reset +: audio-clock! ( -- ) h# 10c pmua! ; +: audio-clock-off ( -- ) + 0 h# 38 sspa! + 0 audio-clock! +; +: start-audio-pll ( -- error? ) + \ For VCXO=26 MHz, OCLK=12.2880 MHz + h# 200d.a189 h# 38 sspa! \ DIV_OCLK_MODULO=010 FRACT=00da1 ENA_DITHER=1 ICP=0 DIV_FBCCLK=01 DIV_MCLK=0 PU=1 + h# 0000.0801 h# 3c sspa! \ CLK_SEL=1 (AudioPLL) DIV_OCLK_PATTERN=01 + d# 50 0 do + h# 3c sspa@ h# 10000 and if + false unloop exit + then + d# 10 us + loop + ." Audio PLL did not start" cr + true +; -[ifdef] 24mhz - \ * 10 / 27 gives about 147.456 - \ The M/N divisor gets 199.33 MHz (Figure 283 - clock tree - in Datasheet) - \ But the M/N divisors always have an implicit /2 (section 7.3.7 in datasheet), - \ so the input frequency is 99.67 with respect to NOM (sic) and DENOM. - \ we want 24.576 MHz SYSCLK. 99.67 * 18 / 73 = 24.575 so 50 ppm error. - d# 18 d# 15 lshift d# 73 or h# d000.0000 or h# 050040 io! +: audio-clock-on ( -- error? ) + h# 600 audio-clock! d# 10 us \ Enable + h# 610 audio-clock! d# 10 us \ Release reset + h# 710 audio-clock! d# 10 us \ Enable + h# 712 audio-clock! d# 10 us \ Release reset + +[ifdef] setup-audio-pll + start-audio-pll if true exit then + + \ Bits 14:9 set the divisor from SYSCLK to BITCLK. The setting below + \ is d# 8, which gives BITCLK = 1.536 MHz. That's 32x 48000, just enough + \ for two (stereo) 16-bit samples. + \ The 80 bit is 0, choosing the AudioPLL instead of the I2SCLK + h# 1103 h# 34 sspa! \ SSPA_AUD_CTRL0 [else] + \ This section of the code uses I2SCLK instead of the Audio PLL. Marvell + \ says that I2SCLK is prone to jitter so the Audio PLL is preferred. + \ * 10 / 27 gives about 147.456 \ The M/N divisor gets 199.33 MHz (Figure 283 - clock tree - in Datasheet) \ But the M/N divisors always have an implicit /2 (section 7.3.7 in datasheet), \ so the input frequency is 99.67 with respect to NOM (sic) and DENOM. \ we want 12.288 MHz SYSCLK. 99.67 * 9 / 73 = 12.2876 so 50 ppm error. - d# 9 d# 15 lshift d# 73 or h# d000.0000 or h# 050040 io! -[then] + d# 9 d# 15 lshift d# 73 or h# d000.0000 or h# 40 mpmu! - h# 05.0024 io@ h# 20 or h# 05.0024 io! \ Enable 12S clock out to SSPA1 +\ The manual says that bit 5 enables I2SCLK to SSPA1, but empirically, bit 21 seems to do it +\ h# 1024 mpmu@ h# 20 or h# 1024 mpmu! \ Enable 12S clock out to SSPA1 + h# 1024 mpmu@ h# 20.0000 or h# 1024 mpmu! \ Enable 12S clock out to SSPA1 h# 10800 h# 38 sspa! - -[ifdef] 24mhz + \ Bits 14:9 set the divisor from SYSCLK to BITCLK. The setting below - \ is d# 16, which gives BITCLK = 3.072 MHz. That's 32x 48000, just enough + \ is d# 8, which gives BITCLK = 1.536 MHz. That's 32x 48000, just enough \ for two (stereo) 16-bit samples. - h# 2183 h# 34 sspa! \ Divisor 16 - BITCLK = 3.072 Mhz -[else] - h# 1183 h# 34 sspa! \ Divisor 8 - BITCLK = 3.072 Mhz + \ The 80 bit is 1, choosing the I2SCLK instead of the AudioPLL + h# 1183 h# 34 sspa! \ SSPA_AUD_CTRL0 [then] + false ; : reset-rx ( -- ) h# 8000.0002 h# 0c sspa! ; @@ -245,17 +268,9 @@ ( default ) true abort" Unsupported audio sample rate" endcase ( sspareg34val timeout ) to buf-timeout - 9 lshift h# 183 or h# 34 sspa! + 9 lshift h# 34 sspa@ h# 7e00 invert and or h# 34 sspa! ; -\ I think we don't need to use the audio PLL, because we are using the PMUM M/N divider -\ DIV_MCL 0 DIV_FBCLK 01 FRACT 00da1 -\ POSTDIV 1 DIV_OCLK_MODULO 000 (NA) DIV_OCLK_PATTERN 00 (NA) -\ : setup-audio-pll ( -- ) -\ h# 000d.a189 h# 38 sspa! -\ h# 0000.0000 h# 3c sspa! -\ ; - : dma-alloc ( len -- adr ) " dma-alloc" $call-parent ; : dma-free ( adr len -- ) " dma-free" $call-parent ; @@ -405,7 +420,7 @@ \ Resetting the clock at this point seems to prevent intermittent channel \ reversal on reception. - audio-clock-on ( ) \ This will mess up any frequency settings + audio-clock-on drop ( ) \ This will mess up any frequency settings setup-sspa-tx ( ) setup-sspa-rx ( ) @@ -504,21 +519,27 @@ set-default-gains d# 48000 set-sample-rate ; +: (close) +\ Reinstate audio-clock-off when Linux turns on its own clock +\ audio-clock-off + adma-base h# 800 " map-out" $call-parent + 0 to adma-base 0 to sspa-base +; 0 value open-count : open ( -- flag ) open-count 0= if my-space h# 800 " map-in" $call-parent to adma-base adma-base h# 400 + to sspa-base - audio-clock-on init-codec + audio-clock-on if (close) false exit then + init-codec then open-count 1+ to open-count true ; : close ( -- ) open-count 1 = if - uninstall-playback-alarm codec-off ( audio-clock-off ) - adma-base h# 800 " map-out" $call-parent - 0 to adma-base 0 to sspa-base + uninstall-playback-alarm codec-off + (close) then open-count 1- 0 max to open-count ;

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[commit] r2541 - cpu/x86
by repository service Sept. 28, 2011

Sept. 28, 2011

Author: wmb Date: Wed Sep 28 03:00:13 2011 New Revision: 2541 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2541 Log: WAV playing - defer freeing the WAV DMA buffer to prevent spurious sounds caused by later actions overwriting the buffer. Modified: cpu/x86/adpcm.fth Modified: cpu/x86/adpcm.fth ============================================================================== --- cpu/x86/adpcm.fth Wed Sep 28 02:57:26 2011 (r2540) +++ cpu/x86/adpcm.fth Wed Sep 28 03:00:13 2011 (r2541) @@ -392,8 +392,9 @@ h# 11 of play-ima-adpcm endof ( default ) ." Cannot play .wav format type: " dup .wav-cc true swap cr endcase - \ audio-ih close-dev - free-wav + + \ We can't do this here because we may overlap the playing with other startup steps + \ audio-ih close-dev free-wav ; : ($play-wav) ( file-str -- )

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[commit] r2540 - dev/olpc/dcon
by repository service Sept. 28, 2011

Sept. 28, 2011

Author: wmb Date: Wed Sep 28 02:57:26 2011 New Revision: 2540 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2540 Log: OLPC XO-1.75 - retry DCON init 5 times. Modified: dev/olpc/dcon/mmp2dcon.fth Modified: dev/olpc/dcon/mmp2dcon.fth ============================================================================== --- dev/olpc/dcon/mmp2dcon.fth Tue Sep 27 23:21:29 2011 (r2539) +++ dev/olpc/dcon/mmp2dcon.fth Wed Sep 28 02:57:26 2011 (r2540) @@ -169,11 +169,13 @@ : dcon-off ( -- ) smb-init h# 12 ['] mode! catch if drop then ; : dcon2? ( -- flag ) - 0 ['] dcon@ catch if ( x ) - drop smb-init ( ) - 0 ['] dcon@ catch if drop false exit then - then - h# dc02 = + 5 0 do + 0 ['] dcon@ catch 0= if ( x ) + h# dc02 = unloop exit + then ( x ) + drop d# 50 ms smb-init ( ) + loop + false ; : dcon-setup ( -- error? )

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[commit] r2539 - cpu/arm/mmp2
by repository service Sept. 27, 2011

Sept. 27, 2011

Author: wmb Date: Tue Sep 27 23:21:29 2011 New Revision: 2539 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2539 Log: OLPC XO-1.75 - version of dramrecal.fth used in q4b10mn Modified: cpu/arm/mmp2/dramrecal.fth Modified: cpu/arm/mmp2/dramrecal.fth ============================================================================== --- cpu/arm/mmp2/dramrecal.fth Tue Sep 27 22:10:43 2011 (r2538) +++ cpu/arm/mmp2/dramrecal.fth Tue Sep 27 23:21:29 2011 (r2539) @@ -59,66 +59,53 @@ here ddr-recal - constant /ddr-recal label ddr-self-refresh ( r0:memctrl-va -- ) - mov r1, #0x1 \ Block all data requests - str r1, [r0, #0x7e0] \ SDRAM_CTRL14 + mov r1, #0x1 \ Block all data requests + str r1, [r0, #0x7e0] \ SDRAM_CTRL14 - ldr r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 - orr r1, r1, #0x03000000 \ PAD_TERM_SWITCH_MODE: Termination disabled - str r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 + ldr r2, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 + orr r1, r2, #0x03000000 \ PAD_TERM_SWITCH_MODE: Termination disabled + str r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 - mov r1, #0x40 \ Enter Self Refresh value - str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 + mov r1, #0x40 \ Enter Self Refresh value + str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 - ldr r1, [r0, #0x1e0] \ PHY_CTRL8 - bic r1,r1,#0x07700000 \ PHY_ADCM_ZPDRV: 0 PHY_ADCM_ZNDRV: 0 (Disable drivers 6:0) - str r1, [r0, #0x1e0] \ PHY_CTRL8 + ldr r3, [r0, #0x1e0] \ PHY_CTRL8 + bic r1, r3, #0x07700000 \ PHY_ADCM_ZPDRV: 0 PHY_ADCM_ZNDRV: 0 (Disable drivers 6:0) + str r1, [r0, #0x1e0] \ PHY_CTRL8 - mov r1, #0x70000 str r1, [r0, #0x110] \ MMAP1 - breadcrumb + dsb \ Data Synchronization Barrier + wfi \ Wait for interrupt - dsb \ Data Synchronization Barrier - wfi \ Wait for interrupt + str r3, [r0, #0x1e0] \ PHY_CTRL8 - restore previous value - ldr r1, [r0, #0x1e0] \ PHY_CTRL8 - orr r1,r1,#0x07700000 \ PHY_ADCM_ZPDRV: 7 PHY_ADCM_ZNDRV: 7 (Enable drivers 6:0) - str r1, [r0, #0x1e0] \ PHY_CTRL8 + mov r1, #0x20000000 \ PHY_DLL_RESET + str r1, [r0, #0x240] \ PHY_CTRL14 - mov r1, #0x20000000 \ PHY_DLL_RESET - str r1, [r0, #0x240] \ PHY_CTRL14 + mov r1, #0x40000000 \ DLL_UPDATE_EN + str r1, [r0, #0x240] \ PHY_CTRL14 - mov r1, #0x40000000 \ DLL_UPDATE_EN - str r1, [r0, #0x240] \ PHY_CTRL14 + mov r1, #0x80 \ Exit Self Refresh value + str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 - mov r1, #0x80 \ Exit Self Refresh value - str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 - - ldr r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 - bic r1, r1, #0x02000000 \ PAD_TERM_SWITCH_MODE: Change 3 to 1 to enable termination for Read and Write - str r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 - - mov r1, #0x20 \ 32 spins, takes about 16 uS (from SRAM) - begin - decs r1, #1 - 0= until + str r2, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 - restore previous value [ifdef] notdef - mov r1, #0x01000000 \ Chip select 0 - orr r1, r1, #0x00001000 \ Initiate ZQ calibration long - str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 - - \ ZQ calibration long takes 512 memory clock cycles after a reset - \ At 400 MHz, that's a little more than 2 us. We spin here to - \ ensure that the recal is complete before we touch the DRAM again. - mov r1, #0x20 \ 32 spins, takes about 16 uS (from SRAM) - begin - decs r1, #1 - 0= until + mov r1, #0x01000000 \ Chip select 0 + orr r1, r1, #0x00001000 \ Initiate ZQ calibration long + str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 + + \ ZQ calibration long takes 512 memory clock cycles after a reset + \ At 400 MHz, that's a little more than 2 us. We spin here to + \ ensure that the recal is complete before we touch the DRAM again. + mov r1, #0x20 \ 32 spins, takes about 16 uS (from SRAM) + begin + decs r1, #1 + 0= until [then] + mov r1, #0x0 \ Unblock data requests + str r1, [r0, #0x7e0] \ SDRAM_CTRL14 - mov r1, #0x0 \ Unblock data requests - str r1, [r0, #0x7e0] \ SDRAM_CTRL14 - - dsb - mov pc, lr + mov pc, lr end-code here ddr-self-refresh - constant /ddr-self-refresh @@ -154,17 +141,10 @@ set r0,`memctrl-va #` \ Memory controller virtual address set r1,`'ddr-self-refresh #` \ Address of ddr-self-refresh routine in SRAM - mov r7,sp - set sp,`'ddr-self-refresh-sp #` ldr r2,[r1] \ Force the code translation into the TLB ldr r3,[r0,#0x110] \ Force the memory controller translation into the TLB mov lr,pc mov pc,r1 - -[ifdef] notdef1 - mov r1,#0xa0000 str r1,[r0,#0x110] \ MMAP1 - breadcrumb -[then] - mov sp,r7 c; : apbc-clr-rst ( offset -- ) +apbc 4 swap io-clr ; @@ -688,7 +668,9 @@ : keyboard-power-on ( -- ) d# 148 gpio-clr ; : keyboard-power-off ( -- ) d# 148 gpio-set ; : wlan-power-on ( -- ) d# 34 gpio-set ; -: wlan-power-off ( -- ) d# 34 gpio-clr ; +: wlan-power-off ( -- ) d# 34 gpio-clr h# 040 d# 34 af! h# 040 d# 57 af! h# 040 d# 58 af! ; +: wlan-stay-on ( -- ) h# 140 d# 34 af! h# 140 d# 57 af! h# 140 d# 58 af! ; + 0 value sleep-mask : screen-off sleep-mask 1 and if \ DCON power down @@ -702,7 +684,7 @@ \ 0 h# 54 pmua! \ Kill the SDIO 0 clocks - insignificant savings \ 0 h# 58 pmua! \ Kill the SDIO 1 clocks - insignificant savings sleep-mask 2 and 0= if keyboard-power-off then \ Should save about 17 mW - sleep-mask 4 and 0= if wlan-power-off then \ saves 100 mW + sleep-mask 4 and if wlan-stay-on else wlan-power-off then \ saves 100 mW ; : screen-on ( -- ) sleep-mask 4 and 0= if wlan-power-on then @@ -767,14 +749,10 @@ disable-clks -\ hdd-led-off - \ begin mmp2_cpu_do_idle() block-irqs ( ) \ Block IRQs - will be cleared by PMU do-self-refresh ( ) -\ hdd-led-on - restore-run-state \ end mmp2_cpu_do_idle() @@ -792,7 +770,7 @@ enable-interrupts hdd-led-off ; -: strp ( -- ) ec-rst-pwr str ec-max-pwr .d ." mW " ; +: strp ( -- ) ec-rst-pwr str ec-max-pwr .d ." mW " soc .% space ; \ LICENSE_BEGIN \ Copyright (c) 2011 FirmWorks

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[commit] r2538 - cpu/arm/mmp2
by repository service Sept. 27, 2011

Sept. 27, 2011

Author: wmb Date: Tue Sep 27 22:10:43 2011 New Revision: 2538 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2538 Log: OLPC XO-1.75 - version of dramrecal.fth for q4b10ml.rom - working pretty well. Modified: cpu/arm/mmp2/dramrecal.fth Modified: cpu/arm/mmp2/dramrecal.fth ============================================================================== --- cpu/arm/mmp2/dramrecal.fth Tue Sep 27 06:59:20 2011 (r2537) +++ cpu/arm/mmp2/dramrecal.fth Tue Sep 27 22:10:43 2011 (r2538) @@ -59,128 +59,58 @@ here ddr-recal - constant /ddr-recal label ddr-self-refresh ( r0:memctrl-va -- ) -\ dsb -\ mcr p15,0,r0,cr8,cr5,0 \ Invalidate TLB -\ \ mcr p15,0,r0,cr7,cr10,4 \ Write data synchronization barrier - mov r1, #0x1 \ Block all data requests str r1, [r0, #0x7e0] \ SDRAM_CTRL14 -\ Latest test -\ ldr r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 -\ bic r1, r1, #0xc0 \ USER_SR_REQUEST field -\ orr r1, r1, #0x40 \ Enter Self Refresh value -\ str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 - - \ This block was commented-out in the Linux code, and the value is incorrect for OLPC in any case - \ mov r1, #0x03000000 \ PAD_TERM_SWITCH_MODE: Termination disabled - \ orr r1, r1, #0x000a \ ODT{1,0}_SWITCH_MODE: Termination controlled by Read and Write enables - \ str r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 - \ OLPC - ldr r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 - orr r1, r1, #0x03000000 \ PAD_TERM_SWITCH_MODE: Termination disabled - str r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 + ldr r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 + orr r1, r1, #0x03000000 \ PAD_TERM_SWITCH_MODE: Termination disabled + str r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 -\ mov r1, #0x1000000 \ Chip select 0 -\ orr r1, r1, #0x40 \ Enter Self Refresh value mov r1, #0x40 \ Enter Self Refresh value str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 -\ Store registers in SRAM so CForth can see them, for debugging - set r2, #0xd102.0400 - stmia r2, {r0-r15} - - \ Linux sets the register to 0x860 ldr r1, [r0, #0x1e0] \ PHY_CTRL8 bic r1,r1,#0x07700000 \ PHY_ADCM_ZPDRV: 0 PHY_ADCM_ZNDRV: 0 (Disable drivers 6:0) str r1, [r0, #0x1e0] \ PHY_CTRL8 - mov r1, #0x70000 str r1, [r0, #0x110] \ MMAP1 - breadcrumb + mov r1, #0x70000 str r1, [r0, #0x110] \ MMAP1 - breadcrumb dsb \ Data Synchronization Barrier wfi \ Wait for interrupt - \ Linux sets the register to 0x07700860, hardcoding the drive strength ldr r1, [r0, #0x1e0] \ PHY_CTRL8 orr r1,r1,#0x07700000 \ PHY_ADCM_ZPDRV: 7 PHY_ADCM_ZNDRV: 7 (Enable drivers 6:0) str r1, [r0, #0x1e0] \ PHY_CTRL8 - \ This block was commented-out in the Linux code, and the value is incorrect for OLPC in any case - \ mov r1, #0x02000000 \ PAD_TERM_SWITCH_MODE: Termination enabled during all reads - \ orr r1, r1, #0x000a \ ODT{1,0}_SWITCH_MODE: Termination controlled by Read and Write enables - \ str r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 - -\ mov r1, #0x80000000 \ PHY_SYNC_EN \ Wad suggests commenting out... -\ str r1, [r0, #0x240] \ PHY_CTRL14 - - \ There used to be code to set register 230, but Marvell says it is unnecessary. - mov r1, #0x20000000 \ PHY_DLL_RESET str r1, [r0, #0x240] \ PHY_CTRL14 mov r1, #0x40000000 \ DLL_UPDATE_EN str r1, [r0, #0x240] \ PHY_CTRL14 -\ ldr r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 -\ bic r1, r1, #0xc0 \ USER_SR_REQUEST field -\ orr r1, r1, #0x80 \ Exit Self Refresh value -\ str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 - -\ mov r1, #0x01000000 \ Chip select 0 -\ orr r1, r1, #0x80 \ Exit Self Refresh value - mov r1, #0x80 \ Exit Self Refresh value + mov r1, #0x80 \ Exit Self Refresh value str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 -\ ldr r1, [r0, #0x80] \ SDRAM_CTRL1 -\ orr r1, r1, #0x40 \ DLL_RESET -\ str r1, [r0, #0x80] \ SDRAM_CTRL1 - -\ mov r1, #0x01000000 \ Chip select 0 -\ orr r1, r1, #0x0100 \ USER_LMR0_REQ - Initiate Mode Register Set -\ str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 - - \ ZQ calibration long takes 512 memory clock cycles after a reset - \ At 400 MHz, that's a little more than 2 us. We spin here to - \ ensure that the recal is complete before we touch the DRAM again. - mov r1, #0x200 \ 512 spins, takes about 4 uS (from SRAM) - begin - decs r1, #1 - 0= until - ldr r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 bic r1, r1, #0x02000000 \ PAD_TERM_SWITCH_MODE: Change 3 to 1 to enable termination for Read and Write str r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 - \ ZQ calibration long takes 512 memory clock cycles after a reset - \ At 400 MHz, that's a little more than 2 us. We spin here to - \ ensure that the recal is complete before we touch the DRAM again. - mov r1, #0x20 \ 32 spins, takes about 16 uS (from SRAM) - begin - decs r1, #1 - 0= until - + mov r1, #0x20 \ 32 spins, takes about 16 uS (from SRAM) + begin + decs r1, #1 + 0= until [ifdef] notdef - mov r1, #0x01000000 \ Chip select 0 - orr r1, r1, #0x00001000 \ Initiate ZQ calibration long - str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 - - \ ZQ calibration long takes 512 memory clock cycles after a reset - \ At 400 MHz, that's a little more than 2 us. We spin here to - \ ensure that the recal is complete before we touch the DRAM again. - mov r1, #0x20 \ 32 spins, takes about 16 uS (from SRAM) - begin - decs r1, #1 - 0= until - - \ ldr r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 - \ bic r1, r1, #0xc0 \ USER_SR_REQUEST field - \ orr r1, r1, #0x80 \ Exit Self Refresh value - \ str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 - - mov r1, #0x100 \ 256 spins, takes about 32 uS (from SRAM) + mov r1, #0x01000000 \ Chip select 0 + orr r1, r1, #0x00001000 \ Initiate ZQ calibration long + str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 + + \ ZQ calibration long takes 512 memory clock cycles after a reset + \ At 400 MHz, that's a little more than 2 us. We spin here to + \ ensure that the recal is complete before we touch the DRAM again. + mov r1, #0x20 \ 32 spins, takes about 16 uS (from SRAM) begin - decs r1,#1 + decs r1, #1 0= until [then] @@ -188,20 +118,6 @@ str r1, [r0, #0x7e0] \ SDRAM_CTRL14 dsb -\ mcr p15,0,r0,cr8,cr5,0 \ Invalidate TLB - - mov r1, #0x80000 str r1, [r0, #0x110] \ MMAP1 - breadcrumb - - mov r1, #0x10000 \ 64k spins, takes about 32 mS (from SRAM) - begin - decs r1,#1 - 0= until - - set r2, #0xd102.0440 - stmia r2, {r0-r15} - - mov r1, #0x90000 str r1, [r0, #0x110] \ MMAP1 - breadcrumb - mov pc, lr end-code here ddr-self-refresh - constant /ddr-self-refresh @@ -245,7 +161,9 @@ mov lr,pc mov pc,r1 +[ifdef] notdef1 mov r1,#0xa0000 str r1,[r0,#0x110] \ MMAP1 - breadcrumb +[then] mov sp,r7 c; @@ -849,23 +767,19 @@ disable-clks - hdd-led-off +\ hdd-led-off \ begin mmp2_cpu_do_idle() block-irqs ( ) \ Block IRQs - will be cleared by PMU do-self-refresh ( ) - hdd-led-on +\ hdd-led-on restore-run-state \ end mmp2_cpu_do_idle() - h# b0000 breadcrumb - enable-clks - h# c0000 breadcrumb - power-islands-on \ mmp2_cpu_enable_l2(0); @@ -873,12 +787,9 @@ \ idle_cfg &= (~PMUA_MOH_SRAM_PWRDWN); stdin-idle-on - h# d0000 breadcrumb screen-on timers-on - h# e0000 breadcrumb enable-interrupts - h# f0000 breadcrumb hdd-led-off ; : strp ( -- ) ec-rst-pwr str ec-max-pwr .d ." mW " ;

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[commit] r2537 - in ofw: inet inetv6
by repository service Sept. 27, 2011

Sept. 27, 2011

Author: wmb Date: Tue Sep 27 06:59:20 2011 New Revision: 2537 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2537 Log: DNS - use source port 53 which works better with dnscache than the previously-used port 1022. Modified: ofw/inet/dns.fth ofw/inetv6/dns.fth Modified: ofw/inet/dns.fth ============================================================================== --- ofw/inet/dns.fth Tue Sep 27 06:54:19 2011 (r2536) +++ ofw/inet/dns.fth Tue Sep 27 06:59:20 2011 (r2537) @@ -15,7 +15,7 @@ \ QTYPE value for "A" (host name) is 1 \ QCLASS value for "IN" (Internet) is 1 -d# 1022 value fw-port# +d# 53 value fw-port# \ Encode/decode various DNS data types : +dnsw ( w -- ) wbsplit +xb +xb ; Modified: ofw/inetv6/dns.fth ============================================================================== --- ofw/inetv6/dns.fth Tue Sep 27 06:54:19 2011 (r2536) +++ ofw/inetv6/dns.fth Tue Sep 27 06:59:20 2011 (r2537) @@ -16,8 +16,7 @@ \ QTYPE value for "AAAA" (IPv6 hostname) is h# 1c \ QCLASS value for "IN" (Internet) is 1 -\ d# 1022 value fw-port# \ It's been assigned by IANA. -h# 800a constant fw-port# \ It's unassigned as of 8/13/2007. +d# 53 constant fw-port# d# 2000 constant dns-timeout

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[commit] r2536 - cpu/arm/mmp2
by repository service Sept. 27, 2011

Sept. 27, 2011

Author: wmb Date: Tue Sep 27 06:54:19 2011 New Revision: 2536 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2536 Log: OLPC XO-1.75 - version of low-level suspend-resume code that seems to be stable on SKU 198. There is a lot of commented-out stuff that needs cleanup, but I'm checking in this version for reference. Modified: cpu/arm/mmp2/dramrecal.fth Modified: cpu/arm/mmp2/dramrecal.fth ============================================================================== --- cpu/arm/mmp2/dramrecal.fth Sat Sep 24 02:38:55 2011 (r2535) +++ cpu/arm/mmp2/dramrecal.fth Tue Sep 27 06:54:19 2011 (r2536) @@ -59,22 +59,32 @@ here ddr-recal - constant /ddr-recal label ddr-self-refresh ( r0:memctrl-va -- ) - dsb - mcr p15,0,r0,cr8,cr5,0 \ Invalidate TLB -\ mcr p15,0,r0,cr7,cr10,4 \ Write data synchronization barrier +\ dsb +\ mcr p15,0,r0,cr8,cr5,0 \ Invalidate TLB +\ \ mcr p15,0,r0,cr7,cr10,4 \ Write data synchronization barrier mov r1, #0x1 \ Block all data requests str r1, [r0, #0x7e0] \ SDRAM_CTRL14 - ldr r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 - bic r1, r1, #0xc0 \ USER_SR_REQUEST field - orr r1, r1, #0x40 \ Enter Self Refresh value - str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 +\ Latest test +\ ldr r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 +\ bic r1, r1, #0xc0 \ USER_SR_REQUEST field +\ orr r1, r1, #0x40 \ Enter Self Refresh value +\ str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 \ This block was commented-out in the Linux code, and the value is incorrect for OLPC in any case \ mov r1, #0x03000000 \ PAD_TERM_SWITCH_MODE: Termination disabled \ orr r1, r1, #0x000a \ ODT{1,0}_SWITCH_MODE: Termination controlled by Read and Write enables \ str r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 + \ OLPC + ldr r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 + orr r1, r1, #0x03000000 \ PAD_TERM_SWITCH_MODE: Termination disabled + str r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 + +\ mov r1, #0x1000000 \ Chip select 0 +\ orr r1, r1, #0x40 \ Enter Self Refresh value + mov r1, #0x40 \ Enter Self Refresh value + str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 \ Store registers in SRAM so CForth can see them, for debugging set r2, #0xd102.0400 @@ -85,7 +95,7 @@ bic r1,r1,#0x07700000 \ PHY_ADCM_ZPDRV: 0 PHY_ADCM_ZNDRV: 0 (Disable drivers 6:0) str r1, [r0, #0x1e0] \ PHY_CTRL8 - mov r1, #0x80000 str r1, [r0, #0x110] \ MMAP1 - breadcrumb + mov r1, #0x70000 str r1, [r0, #0x110] \ MMAP1 - breadcrumb dsb \ Data Synchronization Barrier wfi \ Wait for interrupt @@ -100,8 +110,8 @@ \ orr r1, r1, #0x000a \ ODT{1,0}_SWITCH_MODE: Termination controlled by Read and Write enables \ str r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 - mov r1, #0x80000000 \ PHY_SYNC_EN - str r1, [r0, #0x240] \ PHY_CTRL14 +\ mov r1, #0x80000000 \ PHY_SYNC_EN \ Wad suggests commenting out... +\ str r1, [r0, #0x240] \ PHY_CTRL14 \ There used to be code to set register 230, but Marvell says it is unnecessary. @@ -111,18 +121,57 @@ mov r1, #0x40000000 \ DLL_UPDATE_EN str r1, [r0, #0x240] \ PHY_CTRL14 - ldr r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 - bic r1, r1, #0xc0 \ USER_SR_REQUEST field - orr r1, r1, #0x80 \ Exit Self Refresh value +\ ldr r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 +\ bic r1, r1, #0xc0 \ USER_SR_REQUEST field +\ orr r1, r1, #0x80 \ Exit Self Refresh value +\ str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 + +\ mov r1, #0x01000000 \ Chip select 0 +\ orr r1, r1, #0x80 \ Exit Self Refresh value + mov r1, #0x80 \ Exit Self Refresh value str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 - ldr r1, [r0, #0x80] \ SDRAM_CTRL1 - orr r1, r1, #0x40 \ DLL_RESET - str r1, [r0, #0x80] \ SDRAM_CTRL1 +\ ldr r1, [r0, #0x80] \ SDRAM_CTRL1 +\ orr r1, r1, #0x40 \ DLL_RESET +\ str r1, [r0, #0x80] \ SDRAM_CTRL1 + +\ mov r1, #0x01000000 \ Chip select 0 +\ orr r1, r1, #0x0100 \ USER_LMR0_REQ - Initiate Mode Register Set +\ str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 + + \ ZQ calibration long takes 512 memory clock cycles after a reset + \ At 400 MHz, that's a little more than 2 us. We spin here to + \ ensure that the recal is complete before we touch the DRAM again. + mov r1, #0x200 \ 512 spins, takes about 4 uS (from SRAM) + begin + decs r1, #1 + 0= until + + ldr r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 + bic r1, r1, #0x02000000 \ PAD_TERM_SWITCH_MODE: Change 3 to 1 to enable termination for Read and Write + str r1, [r0, #0x770] \ SDRAM_CTRL7_SDRAM_ODT_CTRL2 + + \ ZQ calibration long takes 512 memory clock cycles after a reset + \ At 400 MHz, that's a little more than 2 us. We spin here to + \ ensure that the recal is complete before we touch the DRAM again. + mov r1, #0x20 \ 32 spins, takes about 16 uS (from SRAM) + begin + decs r1, #1 + 0= until - mov r1, #0x01000000 \ Chip select 0 - orr r1, r1, #0x0100 \ USER_LMR0_REQ - Initiate Mode Register Set - str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 + +[ifdef] notdef + mov r1, #0x01000000 \ Chip select 0 + orr r1, r1, #0x00001000 \ Initiate ZQ calibration long + str r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 + + \ ZQ calibration long takes 512 memory clock cycles after a reset + \ At 400 MHz, that's a little more than 2 us. We spin here to + \ ensure that the recal is complete before we touch the DRAM again. + mov r1, #0x20 \ 32 spins, takes about 16 uS (from SRAM) + begin + decs r1, #1 + 0= until \ ldr r1, [r0, #0x120] \ USER_INITIATED_COMMAND0 \ bic r1, r1, #0xc0 \ USER_SR_REQUEST field @@ -133,15 +182,26 @@ begin decs r1,#1 0= until +[then] mov r1, #0x0 \ Unblock data requests str r1, [r0, #0x7e0] \ SDRAM_CTRL14 dsb - mcr p15,0,r0,cr8,cr5,0 \ Invalidate TLB +\ mcr p15,0,r0,cr8,cr5,0 \ Invalidate TLB mov r1, #0x80000 str r1, [r0, #0x110] \ MMAP1 - breadcrumb + mov r1, #0x10000 \ 64k spins, takes about 32 mS (from SRAM) + begin + decs r1,#1 + 0= until + + set r2, #0xd102.0440 + stmia r2, {r0-r15} + + mov r1, #0x90000 str r1, [r0, #0x110] \ MMAP1 - breadcrumb + mov pc, lr end-code here ddr-self-refresh - constant /ddr-self-refresh @@ -180,10 +240,12 @@ set r1,`'ddr-self-refresh #` \ Address of ddr-self-refresh routine in SRAM mov r7,sp set sp,`'ddr-self-refresh-sp #` + ldr r2,[r1] \ Force the code translation into the TLB + ldr r3,[r0,#0x110] \ Force the memory controller translation into the TLB mov lr,pc mov pc,r1 - mov r1,#0x90000 str r1,[r0,#0x110] \ MMAP1 - breadcrumb + mov r1,#0xa0000 str r1,[r0,#0x110] \ MMAP1 - breadcrumb mov sp,r7 c; @@ -794,7 +856,6 @@ do-self-refresh ( ) hdd-led-on - h# a0000 breadcrumb restore-run-state \ end mmp2_cpu_do_idle()

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