[coreboot] [VERY IMPORTANT] Announcement regarding Apollo Lake Coreboot building
Zoran Stojsavljevic
zoran.stojsavljevic at gmail.com
Sat Nov 4 07:26:27 CET 2017
> Zoran, and others,
>
> I wanted to build coreboot for APL CRP too. Tried to compile but failed
at last command I think.
First email thread to read ([coreboot] Intel Leaf Hill Coreboot Trouble):
https://mail.coreboot.org/pipermail/coreboot/2017-September/085210.html
Second community thread to read (to get the idea about APL-I IFWI):
https://embedded.communities.intel.com/thread/13129
Please, let us know if these threads are helpful!
Zoran
On Fri, Nov 3, 2017 at 2:14 AM, ahW at n via coreboot <coreboot at coreboot.org>
wrote:
> Zoran,
>
> and others,
>
>
>
> I wanted to build coreboot for APL CRP too.
>
> Tried to compile but failed at last command I think.
>
>
>
> *Image written successfully to build/cbfs/fallback/ifwi.bin.tmp.*
>
> *INFO: Performing operation on 'IFWI' region...*
>
> *E: Image is missing 'IFWI' region*
>
> *E: The image will be left unmodified.*
>
> *src/soc/intel/apollolake/Makefile.inc:128: recipe for target
> 'files_added' failed*
>
> *make: *** [files_added] Error 1*
>
>
>
> Have been searching around for solution and correct steps to do so but
> still no luck...
>
> Have you get your APL coreboot working?
>
>
>
> I tried CONFIG_IFWI_FILE_NAME pointed to an original UEFI BIOS file
> (direct SPI flashable binary, tested).
>
> Also tried use FIT to regenerate new file with changes below:-
>
> Platform Protection/Platform Integrity OOEM Public Key Hash => 00..00
>
> Platform Protection/Boot Guard Configuration/ Boot profile 2 => 0
>
>
>
> I am not sure I have the correct .config
>
> Anyone here can advise what I am doing wrong or am I missing anything?
>
> Thank you.
>
>
>
> user at localhost:~/coreboot$ build/util/cbfstool/cbfstool
> build/coreboot.rom print
>
> Name Offset Type Size Comp
>
> cbfs master header 0x0 cbfs header 32 none
>
> fallback/romstage 0x80 stage 26852 none
>
> cpu_microcode_blob.bin 0x69c0 microcode 0 none
>
> fallback/ramstage 0x6a40 stage 67533 none
>
> vgaroms/seavgabios.bin 0x17280 raw 26624 none
>
> config 0x1db00 raw 424 none
>
> revision 0x1dd00 raw 576 none
>
> fallback/postcar 0x1df80 stage 16464 none
>
> fallback/dsdt.aml 0x22040 raw 99 none
>
> fallback/payload 0x22100 payload 63073 none
>
> payload_config 0x317c0 raw 1632 none
>
> payload_revision 0x31e80 raw 239 none
>
> (empty) 0x31fc0 null 8052440 none
>
> mrc.cache 0x7dfec0 mrc_cache 65536 none
>
> (empty) 0x7eff00 null 32664 none
>
> bootblock 0x7f7ec0 bootblock 32768 none
>
>
>
> user at localhost:~/coreboot$ build/util/cbfstool/ifwitool
> ./build/cbfs/fallback/ifwi.bin.tmp print
>
> Header BPDT
>
> Signature 0x000055aa
>
> Descriptor count 13
>
> BPDT Version 1
>
> XOR checksum 0x0
>
> IFWI Version 0x0
>
> FIT Tool Version 0x472000c00000003
>
> BPDT entries
>
> Entry # Sub-Partition Name
> Type Flags
> Offset Size File Offset
>
> ============================================================
> ============================================================
> ============================================================
> =====================
>
> 1 DLMP CSE_IDLM
> 9 0x00000000 0x0
> 0x0 0x0
>
> 2 IFP_OVERRIDE IFP_OVERRIDE
> 10 0x00000000 0x200
> 0x10 0x200
>
> 3 S_BPDT S-BPDT
> 5 0x00000000 0xe9000
> 0x149000 0xe9000
>
> 4 RBEP CSE_RBE
> 1 0x00000000 0x69000
> 0xa000 0x69000
>
> 5 UFS_PHY UFS Phy
> 12 0x00000000 0x0
> 0x0 0x0
>
> 6 UFS_GPP UFS GPP
> 13 0x00000000
> 0x0 0x0 0x0
>
> 7 UEP UEP
> 17 0x00000000 0x210
> 0x108 0x210
>
> 8 IBBP Bootblock
> 4 0x00000000 0x1000
> 0x64000 0x1000
>
> 9 SMIP SMIP
> 0 0x00000000 0x65000
> 0x4000 0x65000
>
> 10 PMCP PMC firmware
> 14 0x00000000 0x73000
> 0x10000 0x73000
>
> 11 FTPR CSE_BUP
> 2 0x00000000 0x83000
> 0x5c000 0x83000
>
> 12 UCOD Microcode
> 3 0x00000000 0xdf000
> 0x8000 0xdf000
>
> 13 DEBUG_TOKENS Debug Tokens
> 11 0x00000000 0xe7000
> 0x2000 0xe7000
>
> ============================================================
> ============================================================
> ============================================================
> =====================
>
> Header S-BPDT
>
> Signature 0x000055aa
>
> Descriptor count 3
>
> BPDT Version 1
>
> XOR checksum 0x0
>
> IFWI Version 0x0
>
> FIT Tool Version 0x472000c00000003
>
> S-BPDT entries
>
> Entry # Sub-Partition Name
> Type Flags Offset
> Size File Offset
>
> ============================================================
> ============================================================
> ============================================================
> =====================
>
> 1 IUNP
> IUNIT 15 0x00000000
> 0xea000 0x2000 0xea000
>
> 2 NFTP CSE_MAIN
> 7 0x00000000
> 0xec000 0x106000 0xec000
>
> 3 ISHP ISH
> 8 0x00000000 0x1f2000
> 0x40000 0x1f2000
>
> ============================================================
> ============================================================
> ==========================================================
>
> --
> coreboot mailing list: coreboot at coreboot.org
> https://mail.coreboot.org/mailman/listinfo/coreboot
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot/attachments/20171104/25eefc35/attachment.html>
More information about the coreboot
mailing list