<div dir="ltr"><p class="MsoNormal" style="font-family:verdana,sans-serif;font-size:12.8px"><a name="m_7582857460781964176_m_-8943817625643046301_m_-7649476182676248305__olk_signature">> Zoran, </a><span style="font-size:12.8px">and others,</span></p><p class="MsoNormal" style="font-family:verdana,sans-serif;font-size:12.8px">></p><p class="MsoNormal" style="font-family:verdana,sans-serif;font-size:12.8px">> I wanted to build coreboot for APL CRP too. <span style="font-size:12.8px">Tried to compile but failed at last command I think.</span></p><p class="MsoNormal" style="font-family:verdana,sans-serif;font-size:12.8px"><span style="font-size:12.8px"><br></span></p><p class="MsoNormal" style="font-family:verdana,sans-serif;font-size:12.8px"><span style="font-size:12.8px">First email thread to read (</span><font size="2" style="color:rgb(0,0,0);font-family:"Times New Roman"">[coreboot] Intel Leaf Hill Coreboot Trouble):</font></p><p class="MsoNormal"><font face="verdana, sans-serif"><span style="font-size:12.8px"><a href="https://mail.coreboot.org/pipermail/coreboot/2017-September/085210.html" target="_blank">https://mail.coreboot.org/<wbr>pipermail/coreboot/2017-<wbr>September/085210.html</a></span></font><br></p><p class="MsoNormal"><font face="verdana, sans-serif"><span style="font-size:12.8px"><br></span></font></p><p class="MsoNormal"><font face="verdana, sans-serif"><span style="font-size:12.8px">Second community thread to read (to get the idea about APL-I IFWI):</span></font></p><p class="MsoNormal"><font face="verdana, sans-serif"><span style="font-size:12.8px"><a href="https://embedded.communities.intel.com/thread/13129">https://embedded.communities.intel.com/thread/13129</a></span><br></font></p><p class="MsoNormal"><font face="verdana, sans-serif"><span style="font-size:12.8px"><br></span></font></p><p class="MsoNormal"><font face="verdana, sans-serif"><span style="font-size:12.8px">Please, let us know if these threads are helpful!</span></font></p><p class="MsoNormal"><font face="verdana, sans-serif"><span style="font-size:12.8px"><br></span></font></p><p class="MsoNormal"><font face="verdana, sans-serif"><span style="font-size:12.8px">Zoran</span></font></p></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Nov 3, 2017 at 2:14 AM, ahW@n via coreboot <span dir="ltr"><<a href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div class="gmail_default" style="font-family:verdana,sans-serif"><p class="MsoNormal"><a name="m_-844227460816698839__olk_signature">Zoran, <span></span></a></p>

<p class="MsoNormal">and others,<span></span></p>

<p class="MsoNormal"><span> </span></p>

<p class="MsoNormal">I wanted to build
coreboot for APL CRP too.<span></span></p>

<p class="MsoNormal">Tried to compile but
failed at last command I think.<span></span></p>

<p class="MsoNormal"><span> </span></p>

<p class="MsoNormal"><i><span style="font-family:"Courier New"">Image
written successfully to build/cbfs/fallback/ifwi.bin.<wbr>tmp.<span></span></span></i></p>

<p class="MsoNormal"><i><span style="font-family:"Courier New"">INFO:
Performing operation on 'IFWI' region...<span></span></span></i></p>

<p class="MsoNormal"><i><span style="font-family:"Courier New"">E:
Image is missing 'IFWI' region<span></span></span></i></p>

<p class="MsoNormal"><i><span style="font-family:"Courier New"">E:
The image will be left unmodified.<span></span></span></i></p>

<p class="MsoNormal"><i><span style="font-family:"Courier New"">src/soc/intel/apollolake/<wbr>Makefile.inc:128:
recipe for target 'files_added' failed<span></span></span></i></p>

<p class="MsoNormal"><i><span style="font-family:"Courier New"">make:
*** [files_added] Error 1<span></span></span></i></p>

<p class="MsoNormal"><i> </i></p>

<p class="MsoNormal">Have been searching around for solution and correct steps to do so but
still no luck...<span></span></p>

<p class="MsoNormal">Have you get your APL coreboot working?<span></span></p>

<p class="MsoNormal"><span> </span></p>

<p class="MsoNormal">I tried CONFIG_IFWI_FILE_NAME pointed to an original UEFI BIOS file (direct
SPI flashable binary, tested).<span></span></p>

<p class="MsoNormal">Also tried use FIT to regenerate new file with changes below:-<span></span></p>

<p class="MsoNormal">  Platform Protection/Platform
Integrity OOEM Public Key Hash => 00..00<span></span></p>

<p class="MsoNormal">  Platform Protection/Boot Guard
Configuration/ Boot profile 2 => 0<span></span></p>

<p class="MsoNormal"><span> </span></p>

<p class="MsoNormal">I am not sure I have the correct .config<span></span></p>

<p class="MsoNormal">Anyone here can advise  what I am doing wrong or am I missing anything?<span></span></p>

<p class="MsoNormal">Thank you.<span></span></p>

<p class="MsoNormal"><span> </span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">user@localhost:~/coreboot$
build/util/cbfstool/cbfstool build/coreboot.rom print<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">Name                           Offset     Type           Size   Comp<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">cbfs master header             0x0        cbfs header        32 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">fallback/romstage              0x80       stage           26852 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">cpu_microcode_blob.bin         0x69c0     microcode           0 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">fallback/ramstage              0x6a40     stage           67533 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">vgaroms/seavgabios.bin         0x17280    raw             26624 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">config                         0x1db00    raw               424 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">revision                       0x1dd00    raw               576 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">fallback/postcar               0x1df80    stage           16464 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">fallback/dsdt.aml              0x22040    raw                99 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">fallback/payload               0x22100    payload         63073 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">payload_config                 0x317c0    raw              1632 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">payload_revision               0x31e80    raw               239 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">(empty)                        0x31fc0    null          8052440 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">mrc.cache                      0x7dfec0   mrc_cache       65536 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">(empty)                        0x7eff00   null  
         32664 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">bootblock                      0x7f7ec0   bootblock       32768 none<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New""><span> </span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">user@localhost:~/coreboot$
build/util/cbfstool/ifwitool ./build/cbfs/fallback/ifwi.<wbr>bin.tmp print<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">Header                    BPDT<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">Signature                 0x000055aa<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">Descriptor count          13<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">BPDT Version              1<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">XOR checksum              0x0<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">IFWI Version              0x0<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">FIT Tool Version          0x472000c00000003<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">BPDT entries<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">Entry #                  Sub-Partition            Name                     Type                     Flags        <wbr>            Offset                   Size                     File Offset<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">==============================<wbr>==============================<wbr>==============================<wbr>==============================<wbr>==============================<wbr>==============================<wbr>=====================<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">1                        DLMP                     CSE_IDLM                 9                        0x00000000               0x0                      0x0                      0x0<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">2                        IFP_OVERRIDE             IFP_OVERRIDE             10                       0x00000000               0x200                    0x10                     0x200<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">3                        S_BPDT                   S-BPDT                   5                        0x00000000               0xe9000                  0x149000                 0xe9000<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">4                        RBEP                     CSE_RBE                  1                        0x00000000               0x69000                  0xa000                   0x69000<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">5                        UFS_PHY                  UFS Phy                  12                       0x00000000               0x0                      0x0                      0x0<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">6                        UFS_GPP                  UFS GPP                  13                       0x00000000               0x0                      0x0                      0x0<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">7                        UEP                      UEP                      17                       0x00000000               0x210                    0x108                    0x210<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">8                        IBBP                     Bootblock                4                        0x00000000               0x1000                   0x64000                  0x1000<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">9                        SMIP                     SMIP               <wbr>      0                        0x00000000               0x65000                  0x4000                   0x65000<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">10                       PMCP                     PMC firmware             14                       0x00000000               0x73000          <wbr>        0x10000                  0x73000<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">11                       FTPR                     CSE_BUP                  2                        0x00000000               0x83000                  0x5c000                  0x83000<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">12                       UCOD                     Microcode                3                        0x00000000               0xdf000                  0x8000                   0xdf000<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">13                       DEBUG_TOKENS             Debug Tokens             11                       0x00000000               0xe7000                  0x2000                   0xe7000<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">==============================<wbr>==============================<wbr>==============================<wbr>==============================<wbr>==============================<wbr>==============================<wbr>=====================<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">Header                    S-BPDT<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">Signature                 0x000055aa<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">Descriptor count          3<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">BPDT Version              1<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">XOR checksum              0x0<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">IFWI Version              0x0<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">FIT Tool Version          0x472000c00000003<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">S-BPDT entries<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">Entry #                  Sub-Partition            Name                     Type                     Flags                    Offset                   Size              <wbr>       File Offset<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">==============================<wbr>==============================<wbr>==============================<wbr>==============================<wbr>==============================<wbr>==============================<wbr>=====================<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">1                        IUNP      <wbr>               IUNIT                    15                       0x00000000               0xea000                  0x2000                   0xea000<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">2                        NFTP                     CSE_MAIN                 7                        <wbr>0x00000000               0xec000                  0x106000                 0xec000<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">3                        ISHP                     ISH                      8                        0x00000000               0x1f2000                 0x40000                  0x1f2000<span></span></span></p>

<p class="MsoNormal"><span style="font-family:"Courier New"">==============================<wbr>==============================<wbr>==============================<wbr>==============================<wbr>==============================<wbr>============================<span></span></span></p></div></div>
<br>--<br>
coreboot mailing list: <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
<a href="https://mail.coreboot.org/mailman/listinfo/coreboot" rel="noreferrer" target="_blank">https://mail.coreboot.org/<wbr>mailman/listinfo/coreboot</a><br></blockquote></div><br></div>