Author: wmb Date: Tue Jul 19 01:05:05 2011 New Revision: 2390 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2390
Log: OLPC XO-1.75 - Eliminated direct use of l! for I/O device access in favor or rl! and io!; allows virtual != physical addressing of I/O devices.
Modified: cpu/arm/marvell/utmiphy.fth cpu/arm/mmp2/boardgpio.fth cpu/arm/mmp2/clocks-complex.fth cpu/arm/mmp2/clocks.fth cpu/arm/mmp2/clockset.fth cpu/arm/mmp2/devices.fth cpu/arm/mmp2/dsi.fth cpu/arm/mmp2/gpio.fth cpu/arm/mmp2/hash.fth cpu/arm/mmp2/hwaddrs.fth cpu/arm/mmp2/keypad.fth cpu/arm/mmp2/lcd.fth cpu/arm/mmp2/mdma.fth cpu/arm/mmp2/mfpr.fth cpu/arm/mmp2/mmp2.bth cpu/arm/mmp2/rootnode.fth cpu/arm/mmp2/rtc.fth cpu/arm/mmp2/spimaster.fth cpu/arm/mmp2/sspspi.fth cpu/arm/mmp2/thermal.fth cpu/arm/mmp2/timer.fth cpu/arm/mmp2/twsi.fth cpu/arm/mmp2/watchdog.fth cpu/arm/olpc/1.75/addrs.fth cpu/arm/olpc/1.75/bbedi.fth cpu/arm/olpc/1.75/devices.fth cpu/arm/olpc/1.75/fw.bth cpu/arm/olpc/1.75/lcd.fth cpu/arm/olpc/1.75/prefw.bth cpu/arm/olpc/1.75/sdhci.fth cpu/arm/olpc/1.75/sound.fth cpu/arm/olpc/initmmu.fth cpu/arm/olpc/resetvec.bth cpu/arm/olpc/spcmd.fth dev/olpc/kb3700/spicmd.fth dev/olpc/mmp2camera/ccic.fth dev/olpc/mmp2camera/platform.fth
Modified: cpu/arm/marvell/utmiphy.fth ============================================================================== --- cpu/arm/marvell/utmiphy.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/marvell/utmiphy.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -1,19 +1,19 @@ \ See license at end of file purpose: Init UTMI USB Phy in Marvell SoC
-h# d4207004 constant utmi-ctrl -h# d4207008 constant utmi-pll -h# d420700c constant utmi-tx -h# d4207010 constant utmi-rx -h# d4207014 constant utmi-ivref -h# d4207018 constant utmi-t0 +h# 207004 constant utmi-ctrl +h# 207008 constant utmi-pll +h# 20700c constant utmi-tx +h# 207010 constant utmi-rx +h# 207014 constant utmi-ivref +h# 207018 constant utmi-t0
-: regset ( mask adr -- ) tuck l@ or swap l! ; -: regclr ( mask adr -- ) tuck l@ swap invert and swap l! ; +: regset ( mask adr -- ) tuck io@ or swap io! ; +: regclr ( mask adr -- ) tuck io@ swap invert and swap io! ;
: wait-cal ( spins -- ) 0 do - utmi-pll rl@ h# 0080.0000 and if unloop exit then + utmi-pll io@ h# 0080.0000 and if unloop exit then loop ." PLL calibrate timeout" cr ;
Modified: cpu/arm/mmp2/boardgpio.fth ============================================================================== --- cpu/arm/mmp2/boardgpio.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/boardgpio.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -2,20 +2,20 @@
: set-camera-domain-voltage aib-unlock - h# d401e80c l@ 4 or ( n ) \ Set 1.8V selector bit in AIB_GPIO2_IO + h# 01e80c io@ 4 or ( n ) \ Set 1.8V selector bit in AIB_GPIO2_IO aib-unlock - h# d401e80c l! + h# 01e80c io! ;
: set-gpio-directions ( -- ) - 3 h# 38 clock-unit-pa + l! \ Enable clocks in GPIO clock reset register + 3 h# 38 clock-unit-pa + io! \ Enable clocks in GPIO clock reset register
- h# 000e.0000 gpio-base h# 0c + l! \ Bits 19, 18, 17 - h# 0704.2000 gpio-base h# 10 + l! \ Bits 58,57,56,50 and 45 -\ h# 03ec.3e00 gpio-base h# 14 + l! \ Bits 89:85,83,82, and 77:73 - h# 03ec.3200 gpio-base h# 14 + l! \ Bits 89:85,83,82, and 77:76 and 73 (leave 74 and 75 as input) + h# 000e.0000 gpio-base h# 0c + io! \ Bits 19, 18, 17 + h# 0704.2000 gpio-base h# 10 + io! \ Bits 58,57,56,50 and 45 +\ h# 03ec.3e00 gpio-base h# 14 + io! \ Bits 89:85,83,82, and 77:73 + h# 03ec.3200 gpio-base h# 14 + io! \ Bits 89:85,83,82, and 77:76 and 73 (leave 74 and 75 as input)
- h# 0200.3c00 gpio-base h# 20 + l! \ Turn off LEDS (3c00) and turn on 5V (0200.0000) + h# 0200.3c00 gpio-base h# 20 + io! \ Turn off LEDS (3c00) and turn on 5V (0200.0000) ;
create mfpr-table
Modified: cpu/arm/mmp2/clocks-complex.fth ============================================================================== --- cpu/arm/mmp2/clocks-complex.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/clocks-complex.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -144,20 +144,20 @@
\ Beginning of section that accesses the hardware
-: +pmua ( -- adr ) h# d428.2800 + ; -: +pmum ( -- adr ) h# d405.0000 + ; +: +pmua ( -- adr ) h# 28.2800 + ; +: +pmum ( -- adr ) h# 05.0000 + ;
: pmum-pll2cr ( -- adr ) h# 34 +pmum ; : pmum-pll2-ctrl1 ( -- adr ) h# 414 +pmum ; : get-pll2-frequency ( -- mhz ) - pmum-pll2cr l@ ( regval ) \ PMUM_PLL2CR + pmum-pll2cr io@ ( regval ) \ PMUM_PLL2CR dup d# 19 5 bits ( regval refdiv ) swap d# 10 9 bits ( refdiv fbdiv ) 2+ d# 26 * ( refdiv numerator ) swap 2+ / ( mhz ) ; -: reg-set ( mask -- ) >r r@ l@ or r> l! ; -: reg-clr ( mask -- ) >r r@ l@ swap invert and r> l! ; +: reg-set ( mask -- ) >r r@ io@ or r> io! ; +: reg-clr ( mask -- ) >r r@ io@ swap invert and r> io! ;
4 constant refdiv \ 4 is the only reference divisor value that is mentioned in the documentation
@@ -166,18 +166,18 @@ 1 d# 29 lshift pmum-pll2-ctrl1 reg-clr ( fbdiv ) \ make sure pll2 is in reset
- pmum-pll2cr l@ ( fbdiv val ) + pmum-pll2cr io@ ( fbdiv val ) h# 100 invert and ( fbdiv val' ) \ PMUM_PLL2CR_PLL2_SW_EN off - dup pmum-pll2cr l! ( fbdiv val ) + dup pmum-pll2cr io! ( fbdiv val )
h# 0007.fc00 invert and refdiv d# 19 lshift or ( fbdiv val' ) h# 00f8.0000 invert and swap d# 10 lshift or ( val' )
h# 200 or ( val' ) \ PMUM_PLL2CR_CTRL - dup pmum-pll2cr l! ( val ) + dup pmum-pll2cr io! ( val )
h# 100 or ( val ) - pmum-pll2cr l! ( ) \ PMUM_PLL2CR_PLL2_SW_EN on + pmum-pll2cr io! ( ) \ PMUM_PLL2CR_PLL2_SW_EN on
1 d# 29 lshift pmum-pll2-ctrl1 reg-set ( ) \ pll2 out of reset
@@ -199,8 +199,8 @@ 4 lshift h# 8000.0000 or ( table-adr common-bits ) #sram-table 0 do ( table-adr common-bits ) over i 8 * + ( table-adr common-bits table-entry-adr ) - dup l@ h# c20 dmcu! ( table-adr common-bits table-entry-adr ) - la1+ l@ h# c30 dmcu! ( table-adr common-bits ) + dup io@ h# c20 dmcu! ( table-adr common-bits table-entry-adr ) + la1+ io@ h# c30 dmcu! ( table-adr common-bits ) over i or h# c00 dmcu! ( common-bits table-adr ) loop ( table-adr common-bits ) 2drop ( ) @@ -225,8 +225,8 @@ ;
: current-dclk ( -- mhz ) - 8 +pmum l@ d# 23 rshift 7 and fccr>frequency ( source-mhz ) - 4 +pmua l@ d# 12 rshift 7 and 1+ / + 8 +pmum io@ d# 23 rshift 7 and fccr>frequency ( source-mhz ) + 4 +pmua io@ d# 12 rshift 7 and 1+ / ;
: PMUcore2_hw_fc_seq ( -- ) @@ -241,15 +241,15 @@ 1 >bit h# 98 +pmua reg-set \ PMUA_MOH_IMR_MOH_FC_INTR_MASK bit in PMUA_PJ_IMR register
begin - 4 +pmua l@ d# 24 >bit and \ PMUA_DM_CC_MOH_SEA_RD_STATUS bit in DM_CC_MOH register + 4 +pmua io@ d# 24 >bit and \ PMUA_DM_CC_MOH_SEA_RD_STATUS bit in DM_CC_MOH register 0= until
new-reg-values ( pj4-cc sp-cc fccr cgr )
?change-pll2-frequency ( pj4-cc sp-cc fccr cgr )
- h# 1024 +pmum l! ( pj4-cc sp-cc fccr ) - swap 0 +pmua l! ( pj4-cc-reg fccr ) + h# 1024 +pmum io! ( pj4-cc sp-cc fccr ) + swap 0 +pmua io! ( pj4-cc-reg fccr ) dclk do-fcs ( )
[ifdef] notdef
Modified: cpu/arm/mmp2/clocks.fth ============================================================================== --- cpu/arm/mmp2/clocks.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/clocks.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -1,7 +1,7 @@ purpose: Change the clock frequency
-: fccr@ ( -- n ) h# d405.0008 l@ ; -: fccr! ( n -- ) h# d405.0008 l! ; +: fccr@ ( -- n ) h# 05.0008 io@ ; +: fccr! ( n -- ) h# 05.0008 io! ; : pj4-clksel ( n -- ) d# 29 lshift ( field ) fccr@ h# e000.0000 invert and or fccr! ( ) @@ -10,9 +10,9 @@ d# 26 lshift ( field ) fccr@ h# 1c00.0000 invert and or fccr! ( ) ; -: pj4-cc! ( n -- ) h# d428.2804 l! ; +: pj4-cc! ( n -- ) h# 28.2804 io! ;
-: sp-cc! ( n -- ) h# d428.2800 l! ; +: sp-cc! ( n -- ) h# 28.2800 io! ; \ cfraaADXBpP : sp-100mhz ( -- ) 0 sp-clksel o# 37077703303 sp-cc! ; \ A 100, D 400, XP 100, B 100, P 100 : sp-200mhz ( -- ) 0 sp-clksel o# 37077301101 sp-cc! ; \ A 200, D 400, XP 200, B 200, P 200
Modified: cpu/arm/mmp2/clockset.fth ============================================================================== --- cpu/arm/mmp2/clockset.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/clockset.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -1,21 +1,21 @@ : clk-fast - ffffffff d4050024 l! \ PMUM_CGR_SP \ All clocks ON - 00061808 d4282888 l! \ PMUA_DEBUG \ Reserved bits, but supposed to "allow freq" + ffffffff 050024 io! \ PMUM_CGR_SP \ All clocks ON + 00061808 282888 io! \ PMUA_DEBUG \ Reserved bits, but supposed to "allow freq"
- 00000000 d4050008 l! \ Startup operation point - 08fd96d9 d4282800 l! \ PMUA_CC_SP \ speed change voting, ACLK:7, DCLK:5, BACLK1:1, PCLK:0 - 78fd96d9 d4282804 l! \ PMUA_CC_PJ \ + 00000000 050008 io! \ Startup operation point + 08fd96d9 282800 io! \ PMUA_CC_SP \ speed change voting, ACLK:7, DCLK:5, BACLK1:1, PCLK:0 + 78fd96d9 282804 io! \ PMUA_CC_PJ \
\ select PLL2 frequency, 520MHz - 08600322 d4050414 l! \ PMUM_PLL2_CTRL1 \ Bandgap+charge pump+VCO loading+regulator defaults, 486.3-528.55 PLL2 (bits 10:6) - 00FFFE00 d4050034 l! \ PMUM_PLL2_CTRL2 \ refclk divisor and feedback divisors at max, software controls activation - 0021da00 d4050034 l! \ PMUM_PLL2_CTRL1 \ refclk divisor=4, feedback divisor=0x76=118, software controls activation - 0021db00 d4050034 l! \ PMUM_PLL2_CTRL2 \ same plus enable - 28600322 d4050414 l! \ PMUM_PLL2_CTRL1 \ same as above plus release PLL loop filter + 08600322 050414 io! \ PMUM_PLL2_CTRL1 \ Bandgap+charge pump+VCO loading+regulator defaults, 486.3-528.55 PLL2 (bits 10:6) + 00FFFE00 050034 io! \ PMUM_PLL2_CTRL2 \ refclk divisor and feedback divisors at max, software controls activation + 0021da00 050034 io! \ PMUM_PLL2_CTRL1 \ refclk divisor=4, feedback divisor=0x76=118, software controls activation + 0021db00 050034 io! \ PMUM_PLL2_CTRL2 \ same plus enable + 28600322 050414 io! \ PMUM_PLL2_CTRL1 \ same as above plus release PLL loop filter \ select clock source, PJ4-PLL1, SP-PLL1/2, AXI/DDR-PLL1 -\ 20800000 d4050008 l! \ PMUM_FCCR PLL1 > PJ4 (bits 31:29), PLL1/2 > SP (bits 28:26), PLL1 > AXI&DDR (bits 25:23) - 24800000 d4050008 l! \ PMUM_FCCR PLL1 > PJ4 (bits 31:29), PLL1 > SP (bits 28:26), PLL1 > AXI&DDR (bits 25:23) +\ 20800000 050008 io! \ PMUM_FCCR PLL1 > PJ4 (bits 31:29), PLL1/2 > SP (bits 28:26), PLL1 > AXI&DDR (bits 25:23) + 24800000 050008 io! \ PMUM_FCCR PLL1 > PJ4 (bits 31:29), PLL1 > SP (bits 28:26), PLL1 > AXI&DDR (bits 25:23) \ divider setting and frequency change request, core-800, ddr-400, axi-200 - 08fd8248 d4282800 l! \ PMUA_CC_SP \ speed change voting, ACLK:7, DCLK:5, BACLK1:1, PCLK:0 - 78fd8248 d4282804 l! \ PMUA_CC_PJ \ + 08fd8248 282800 io! \ PMUA_CC_SP \ speed change voting, ACLK:7, DCLK:5, BACLK1:1, PCLK:0 + 78fd8248 282804 io! \ PMUA_CC_PJ \ ;
Modified: cpu/arm/mmp2/devices.fth ============================================================================== --- cpu/arm/mmp2/devices.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/devices.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -1,15 +1,15 @@ fload ${BP}/dev/omap/diaguart.fth \ OMAP UART -h# d4018000 to uart-base \ UART# base address on MMP2 +h# 018000 +io to uart-base \ UART# base address on MMP2 d# 26000000 to uart-clock-frequency
: init-clocks - -1 h# d4051024 l! \ PMUM_CGR_PJ - everything on - h# 07 h# d4015064 l! \ APBC_AIB_CLK_RST - reset, functional and APB clock on - h# 03 h# d4015064 l! \ APBC_AIB_CLK_RST - release reset, functional and APB clock on - h# 13 h# d4015034 l! \ APBC_UART3_CLK_RST - VCTCXO, functional and APB clock on (26 mhz) - h# c1 h# d401e120 l! \ GPIO51 = af1 for UART3 RXD - h# c1 h# d401e124 l! \ GPIO52 = af1 for UART3 TXD - h# 1b h# d4282854 l! \ SD0 clocks + -1 h# 051024 io! \ PMUM_CGR_PJ - everything on + h# 07 h# 015064 io! \ APBC_AIB_CLK_RST - reset, functional and APB clock on + h# 03 h# 015064 io! \ APBC_AIB_CLK_RST - release reset, functional and APB clock on + h# 13 h# 015034 io! \ APBC_UART3_CLK_RST - VCTCXO, functional and APB clock on (26 mhz) + h# c1 h# 01e120 io! \ GPIO51 = af1 for UART3 RXD + h# c1 h# 01e124 io! \ GPIO52 = af1 for UART3 TXD + h# 1b h# 282854 io! \ SD0 clocks ;
: inituarts ( -- )
Modified: cpu/arm/mmp2/dsi.fth ============================================================================== --- cpu/arm/mmp2/dsi.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/dsi.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -2,8 +2,8 @@ h# 0110 constant pmua_display2_clk_res_ctrl_offset \ DISPLAY2 Clock/Reset Control Register h# 0050 constant pmua_ccic_clk_res_ctrl_offset \ CCIC Clock/Reset Control Register
-: pmua@ ( offset -- n ) pmua-pa + l@ ; -: pmua! ( n offset -- ) pmua-pa + l! ; +: pmua@ ( offset -- n ) pmua-pa + io@ ; +: pmua! ( n offset -- ) pmua-pa + io! ;
: dsi-twsi! ( l reg# -- ) >r lbsplit swap 2swap swap r> wbsplit 6 twsi-write @@ -14,27 +14,27 @@ : dsi-twsi@ ( reg# -- l ) wbsplit 2 4 twsi-get bljoin ; : dsi-twsi-w@ ( reg# -- w ) wbsplit 2 2 twsi-get bwjoin ;
-: dsi1! ( n offset -- ) dsi1-pa + l! ; -: dsi1@ ( n offset -- ) dsi1-pa + l@ ; -: dsi2! ( n offset -- ) dsi2-pa + l! ; -: dsi2@ ( n offset -- ) dsi2-pa + l@ ; +: dsi1! ( n offset -- ) dsi1-pa + io! ; +: dsi1@ ( n offset -- ) dsi1-pa + io@ ; +: dsi2! ( n offset -- ) dsi2-pa + io! ; +: dsi2@ ( n offset -- ) dsi2-pa + io@ ;
0 value dsi-base -: dsi! ( n offset -- ) dsi-base + l! ; -: dsi@ ( n offset -- ) dsi-base + l@ ; +: dsi! ( n offset -- ) dsi-base + io! ; +: dsi@ ( n offset -- ) dsi-base + io@ ;
-: bitset ( mask reg-adr -- ) tuck l@ or swap l! ; -: bitclr ( mask reg-adr -- ) tuck l@ swap invert and swap l! ; +: bitset ( mask reg-adr -- ) tuck io@ or swap io! ; +: bitclr ( mask reg-adr -- ) tuck io@ swap invert and swap io! ; : init-dsi1 ( -- ) \ Ensure that the pins are set up properly - h# c0 d# 83 gpio>mfpr l! \ Configure GPIO83 for function 0 - GPIO + h# c0 d# 83 gpio>mfpr io! \ Configure GPIO83 for function 0 - GPIO d# 83 gpio-dir-out \ Set the direction control to output
h# d123f h# 4c pmua! \ Send clock to TC358762 MIPI DSI bridge \ Enable the M/N clock output - main-pmu-pa h# 1024 + l@ h# 200 or main-pmu-pa h# 1024 + l! \ Set (GPC) G_CLK_OUT ena in clock gating register + main-pmu-pa h# 1024 + io@ h# 200 or main-pmu-pa h# 1024 + io! \ Set (GPC) G_CLK_OUT ena in clock gating register \ Set the M/N value and re-enable the clock gate register - h# 20001 main-pmu-pa h# 30 + l! \ Set M/N divider values in PMUM_GPCR register + h# 20001 main-pmu-pa h# 30 + io! \ Set M/N divider values in PMUM_GPCR register h# 4000 mfpr-base h# 160 + bitset \ pull-up
\ Disable DSI
Modified: cpu/arm/mmp2/gpio.fth ============================================================================== --- cpu/arm/mmp2/gpio.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/gpio.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -7,36 +7,36 @@ 1 swap lshift ( gpio# mask ) swap 5 rshift gpio-offsets swap na+ @ gpio-base + ( mask pa ) ; -: gpio-pin@ ( gpio# -- flag ) >gpio-pin l@ and 0<> ; +: gpio-pin@ ( gpio# -- flag ) >gpio-pin io@ and 0<> ;
: >gpio-dir ( gpio# -- mask pa ) >gpio-pin h# 0c + ; -: gpio-out? ( gpio# -- out? ) >gpio-dir l@ and 0<> ; +: gpio-out? ( gpio# -- out? ) >gpio-dir io@ and 0<> ;
-: gpio-set ( gpio# -- ) >gpio-pin h# 18 + l! ; -: gpio-clr ( gpio# -- ) >gpio-pin h# 24 + l! ; +: gpio-set ( gpio# -- ) >gpio-pin h# 18 + io! ; +: gpio-clr ( gpio# -- ) >gpio-pin h# 24 + io! ;
: >gpio-rer ( gpio# -- mask pa ) >gpio-pin h# 30 + ; -: gpio-rise@ ( gpio# -- flag ) >gpio-rer l@ and 0<> ; +: gpio-rise@ ( gpio# -- flag ) >gpio-rer io@ and 0<> ;
: >gpio-fer ( gpio# -- mask pa ) >gpio-pin h# 3c + ; -: gpio-fall@ ( gpio# -- flag ) >gpio-fer l@ and 0<> ; +: gpio-fall@ ( gpio# -- flag ) >gpio-fer io@ and 0<> ;
: >gpio-edr ( gpio# -- mask pa ) >gpio-pin h# 48 + ; -: gpio-edge@ ( gpio# -- flag ) >gpio-edr l@ and 0<> ; -: gpio-clr-edge ( gpio# -- ) >gpio-edr l! ; +: gpio-edge@ ( gpio# -- flag ) >gpio-edr io@ and 0<> ; +: gpio-clr-edge ( gpio# -- ) >gpio-edr io! ;
-: gpio-dir-out ( gpio# -- ) >gpio-pin h# 54 + l! ; -: gpio-dir-in ( gpio# -- ) >gpio-pin h# 60 + l! ; -: gpio-set-rer ( gpio# -- ) >gpio-pin h# 6c + l! ; -: gpio-clr-rer ( gpio# -- ) >gpio-pin h# 78 + l! ; -: gpio-set-fer ( gpio# -- ) >gpio-pin h# 84 + l! ; -: gpio-clr-fer ( gpio# -- ) >gpio-pin h# 90 + l! ; +: gpio-dir-out ( gpio# -- ) >gpio-pin h# 54 + io! ; +: gpio-dir-in ( gpio# -- ) >gpio-pin h# 60 + io! ; +: gpio-set-rer ( gpio# -- ) >gpio-pin h# 6c + io! ; +: gpio-clr-rer ( gpio# -- ) >gpio-pin h# 78 + io! ; +: gpio-set-fer ( gpio# -- ) >gpio-pin h# 84 + io! ; +: gpio-clr-fer ( gpio# -- ) >gpio-pin h# 90 + io! ;
: >gpio-mask ( gpio# -- mask pa ) >gpio-pin h# 9c + ; -: gpio-set-mask ( gpio# -- ) >gpio-mask l! ; +: gpio-set-mask ( gpio# -- ) >gpio-mask io! ;
: >gpio-xmsk ( gpio# -- mask pa ) >gpio-pin h# a8 + ; -: gpio-set-xmsk ( gpio# -- ) >gpio-xmsk l! ; +: gpio-set-xmsk ( gpio# -- ) >gpio-xmsk io! ;
Modified: cpu/arm/mmp2/hash.fth ============================================================================== --- cpu/arm/mmp2/hash.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/hash.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -3,18 +3,18 @@
h# 8101 constant dval : dma>hash ( adr len -- ) - 4 round-up 2 rshift h# d429080c l! ( adr ) - h# d4290808 l! ( ) - dval h# d4290800 l! ( ) -\ begin h# d4290814 l@ 1 and until -; -: dma-stop h# d4290800 l@ 1 invert and h# d4290800 l! ; -: swap-axi-bytes ( -- ) h# 5 h# d4290838 l! ; \ Byte swap input and output -: in-fifo-remain ( -- n ) h# d429083c l@ ; -\ : in-fifo@ ( -- n ) h# d4290880 l@ ; -\ : in-fifo! ( n -- ) h# d4290880 l! ; -\ : out-fifo@ ( -- n ) h# d4290900 l@ ; -\ : out-fifo! ( n -- ) h# d4290900 l! ; + 4 round-up 2 rshift h# 29080c io! ( adr ) + h# 290808 io! ( ) + dval h# 290800 io! ( ) +\ begin h# 290814 io@ 1 and until +; +: dma-stop h# 290800 io@ 1 invert and h# 290800 io! ; +: swap-axi-bytes ( -- ) h# 5 h# 290838 io! ; \ Byte swap input and output +: in-fifo-remain ( -- n ) h# 29083c io@ ; +\ : in-fifo@ ( -- n ) h# 290880 io@ ; +\ : in-fifo! ( n -- ) h# 290880 io! ; +\ : out-fifo@ ( -- n ) h# 290900 io@ ; +\ : out-fifo! ( n -- ) h# 290900 io! ;
h# 40 value /hash-block d# 20 value /hash-digest @@ -23,23 +23,23 @@ 0 value #hash-buf 0 value #hashed
-: use-sha1 ( -- ) 0 h# d4291800 l! d# 20 to /hash-digest ; -: use-sha256 ( -- ) 1 h# d4291800 l! d# 32 to /hash-digest ; -: use-sha224 ( -- ) 2 h# d4291800 l! d# 28 to /hash-digest ; -: use-md5 ( -- ) 3 h# d4291800 l! d# 16 to /hash-digest ; +: use-sha1 ( -- ) 0 h# 291800 io! d# 20 to /hash-digest ; +: use-sha256 ( -- ) 1 h# 291800 io! d# 32 to /hash-digest ; +: use-sha224 ( -- ) 2 h# 291800 io! d# 28 to /hash-digest ; +: use-md5 ( -- ) 3 h# 291800 io! d# 16 to /hash-digest ;
-: hash-control! ( n -- ) h# d4291804 l! ; +: hash-control! ( n -- ) h# 291804 io! ; : hash-go ( -- ) - 1 h# d4291808 l! - begin h# d429180c l@ 1 and until - 1 h# d429180c l! + 1 h# 291808 io! + begin h# 29180c io@ 1 and until + 1 h# 29180c io! ; : set-msg-size ( n -- ) - 0 h# d429181c l! \ High word of total size - h# d4291818 l! \ Low word of total size + 0 h# 29181c io! \ High word of total size + h# 291818 io! \ Low word of total size ; : hash-init ( -- ) - 1 h# d4290c00 l! \ Select hash (0) for Accelerator A, crossing to direct DMA to it + 1 h# 290c00 io! \ Select hash (0) for Accelerator A, crossing to direct DMA to it dma-stop 8 hash-control! \ Reset 0 hash-control! \ Unreset @@ -51,7 +51,7 @@
: hash-update-step ( -- ) hash-buf /hash-block dma>hash ( ) - /hash-block h# d4291810 l! ( ) + /hash-block h# 291810 io! ( ) 2 hash-control! \ Update digest ( ) hash-go ( ) dma-stop @@ -76,14 +76,14 @@ ; : hash-final ( -- ) #hashed set-msg-size ( ) - #hash-buf h# d4291810 l! ( ) + #hash-buf h# 291810 io! ( ) #hash-buf if hash-buf #hash-buf dma>hash ( ) then 7 hash-control! \ Final, with hardware padding hash-go dma-stop - h# d4291820 /hash-digest + h# 291820 /hash-digest ; : hash1 ( adr len -- ) hash-init ( adr len ) @@ -116,8 +116,8 @@ : sha1-update hash-update ; : sha1-final hash-final drop to sha1-digest ;
-: ebg-set ( n -- ) h# d4292c00 l@ or h# d4292c00 l! ; -: ebg-clr ( n -- ) invert h# d4292c00 l@ and h# d4292c00 l! ; +: ebg-set ( n -- ) h# 292c00 io@ or h# 292c00 io! ; +: ebg-clr ( n -- ) invert h# 292c00 io@ and h# 292c00 io! ;
0 [if] \ This is the procedure recommended by the datasheet, but it doesn't work @@ -138,12 +138,12 @@ [else] \ This procedure works : init-entropy ( -- ) \ Using digital method - h# 21117c0 h# d4292c00 l! + h# 21117c0 h# 292c00 io! ; [then]
: random-short ( -- w ) - begin h# d4292c04 l@ dup 0>= while drop repeat + begin h# 292c04 io@ dup 0>= while drop repeat h# ffff and ; : random-byte ( -- b ) random-short 2/ h# ff and ;
Modified: cpu/arm/mmp2/hwaddrs.fth ============================================================================== --- cpu/arm/mmp2/hwaddrs.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/hwaddrs.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -1,11 +1,11 @@ \ Defined by MMP2 hardware -h# d401.9000 constant gpio-base -h# d405.1024 constant acgr-pa -h# d401.5000 constant clock-unit-pa -h# d405.0000 constant main-pmu-pa -h# d428.2800 constant pmua-pa \ Application processor PMU register base -h# d420.b800 constant dsi1-pa \ 4-lane controller -h# d420.ba00 constant dsi2-pa \ 3-lane controller -h# d420.b000 constant lcd-pa -h# d401.4000 constant timer-pa +h# 01.9000 constant gpio-base +h# 05.1024 constant acgr-pa +h# 01.5000 constant clock-unit-pa +h# 05.0000 constant main-pmu-pa +h# 28.2800 constant pmua-pa \ Application processor PMU register base +h# 20.b800 constant dsi1-pa \ 4-lane controller +h# 20.ba00 constant dsi2-pa \ 3-lane controller +h# 20.b000 constant lcd-pa +h# 01.4000 constant timer-pa
Modified: cpu/arm/mmp2/keypad.fth ============================================================================== --- cpu/arm/mmp2/keypad.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/keypad.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -2,11 +2,12 @@ purpose: Driver for Armada 610/MMP2 keypad controller
: keypad-on ( -- ) - 5 h# d4015018 l! \ Clock on with reset asserted - 1 h# d4015018 l! \ Clock on, release reset + 5 h# 015018 io! \ Clock on with reset asserted + 1 h# 015018 io! \ Clock on, release reset + 1 ms ; -: kp! ( n offset -- ) h# d4012000 + l! ; -: kp@ ( offset -- n ) h# d4012000 + l@ ; +: kp! ( n offset -- ) h# 012000 + io! ; +: kp@ ( offset -- n ) h# 012000 + io@ ; : keypad-direct-mode ( #keys -- ) 1- 6 lshift h# 202 or 0 kp! ;
Modified: cpu/arm/mmp2/lcd.fth ============================================================================== --- cpu/arm/mmp2/lcd.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/lcd.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -1,6 +1,6 @@
-: lcd@ ( offset -- l ) lcd-pa + l@ ; -: lcd! ( l offset -- ) lcd-pa + l! ; +: lcd@ ( offset -- l ) lcd-pa + io@ ; +: lcd! ( l offset -- ) lcd-pa + io! ;
: spi-clr-irq ( -- ) h# 1c4 lcd@ h# 00040000 invert and h# 1c4 lcd! \ Clear SPI_IRQ bit
Modified: cpu/arm/mmp2/mdma.fth ============================================================================== --- cpu/arm/mmp2/mdma.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/mdma.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -6,10 +6,8 @@ \ Read from cache (address constant) 4.2 GB/sec \ Read from memory (advancing address) 390 MB/sec
-h# d42a.0a00 value mdma0-base - -: mdma! ( n offset -- ) mdma0-base + l! ; -: mdma@ ( offset -- n ) mdma0-base + l@ ; +: mdma! ( n offset -- ) h# 2a0a00 + io! ; +: mdma@ ( offset -- n ) h# 2a0a00 + io@ ;
h# 0010.0000 constant mdma-ram h# ffc0 constant /mdma-buf @@ -64,7 +62,7 @@ mdma-desc0 h# 30 mdma! \ Link to first descriptor ; : start-test-ring ( -- ) -\ 8 h# d428.2864 l! \ Enable DMA clock +\ 8 h# 28.2864 io! \ Enable DMA clock 1 h# 80 mdma! \ Enable DMA completion interrupts h# 0000.3d80 h# 40 mdma! \ fetch next, enable, chain, 32 bytes, inc dest, inc src ;
Modified: cpu/arm/mmp2/mfpr.fth ============================================================================== --- cpu/arm/mmp2/mfpr.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/mfpr.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -1,11 +1,11 @@ purpose: Pin multiplexing for ARMADA 610 chip (no board details)
: aib-unlock - h# baba h# d4015068 l! \ Unlock sequence - h# eb10 h# d401506c l! + h# baba h# 015068 io! \ Unlock sequence + h# eb10 h# 01506c io! ; : acgr-clocks-on ( -- ) - h# 0818.F33C acgr-pa l! \ Turn on all clocks + h# 0818.F33C acgr-pa io! \ Turn on all clocks ;
hex @@ -33,21 +33,20 @@ 250 w, 210 w, 20C w, 208 w, 204 w, 1EC w, 1E8 w, 1E4 w, \ 160->167 1E0 w, \ 168
-h# d401.e000 constant mfpr-base : gpio>mfpr ( gpio# -- mfpr-pa ) mfpr-offsets swap wa+ w@ - mfpr-base + + h# 01.e000 + ;
: dump-mfprs ( -- ) base @ - d# 169 0 do decimal i 3 u.r space i gpio>mfpr l@ 4 hex u.r cr loop + d# 169 0 do decimal i 3 u.r space i gpio>mfpr io@ 4 hex u.r cr loop base ! ;
: no-update, ( -- ) 8 w, ; \ 8 is a reserved bit; the code skips these -: af@ ( gpio# -- function# ) gpio>mfpr l@ ; -: af! ( function# gpio# -- ) gpio>mfpr l! ; +: af@ ( gpio# -- function# ) gpio>mfpr io@ ; +: af! ( function# gpio# -- ) gpio>mfpr io! ; : af, ( n -- ) h# c0 + w, ; : +fast ( n -- n' ) h# 1800 or ; : pull-up, ( n -- ) h# c0c0 + w, ;
Modified: cpu/arm/mmp2/mmp2.bth ============================================================================== --- cpu/arm/mmp2/mmp2.bth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/mmp2.bth Tue Jul 19 01:05:05 2011 (r2390) @@ -17,7 +17,7 @@ ' (initial-heap) to initial-heap
fload ${BP}/dev/omap/diaguart.fth \ OMAP UART -h# d4018000 to uart-base \ UART# base address on MMP2 +h# 018000 +io to uart-base \ UART# base address on MMP2
fload ${BP}/forth/lib/sysuart.fth \ Set console I/O vectors to UART
Modified: cpu/arm/mmp2/rootnode.fth ============================================================================== --- cpu/arm/mmp2/rootnode.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/rootnode.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -25,7 +25,7 @@ : close ( -- ) ;
: map-in ( phys size -- virt ) - drop + drop io-pa - io-va + ; : map-out ( virtual size -- ) 2drop
Modified: cpu/arm/mmp2/rtc.fth ============================================================================== --- cpu/arm/mmp2/rtc.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/rtc.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -5,12 +5,12 @@ \ It is not currently used by anything, and should it \ ever be needed, it should be put in a device node.
-: int5-mask! ( value -- ) h# d428.216c l! ; -: int5-mask@ ( -- value ) h# d428.216c l@ ; -: int5-status@ ( -- value ) h# d428.2154 l@ ; -: enable-rtc ( -- ) h# 81 h# d401.5000 l! ; -: soc-rtc@ ( offset -- value ) h# d401.0000 + l@ ; -: soc-rtc! ( value offset -- value ) h# d401.0000 + l! ; +: int5-mask! ( value -- ) h# 28.216c io! ; +: int5-mask@ ( -- value ) h# 28.216c io@ ; +: int5-status@ ( -- value ) h# 28.2154 io@ ; +: enable-rtc ( -- ) h# 81 h# 01.5000 io! ; +: soc-rtc@ ( offset -- value ) h# 01.0000 + io@ ; +: soc-rtc! ( value offset -- value ) h# 01.0000 + io! ; : take-alarm ( -- ) ." Alarm fired" cr 0 8 soc-rtc!
Modified: cpu/arm/mmp2/spimaster.fth ============================================================================== --- cpu/arm/mmp2/spimaster.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/spimaster.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -39,10 +39,10 @@ enable ;
-: ssp1-clk-on 7 h# d4015050 l! 3 h# d4015050 l! ; -\ : ssp2-clk-on 7 h# d4015054 l! 3 h# d4015052 l! ; -\ : ssp3-clk-on 7 h# d4015058 l! 3 h# d4015058 l! ; -\ : ssp4-clk-on 7 h# d401505c l! 3 h# d401505c l! ; +: ssp1-clk-on 7 h# 015050 io! 3 h# 015050 io! ; +\ : ssp2-clk-on 7 h# 015054 io! 3 h# 015052 io! ; +\ : ssp3-clk-on 7 h# 015058 io! 3 h# 015058 io! ; +\ : ssp4-clk-on 7 h# 01505c io! 3 h# 01505c io! ;
: wb ( byte -- ) ssp-ssdr rl! ; : rb ( -- byte ) ssp-ssdr rl@ . ;
Modified: cpu/arm/mmp2/sspspi.fth ============================================================================== --- cpu/arm/mmp2/sspspi.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/sspspi.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -6,7 +6,7 @@ \ Every spicmd! clocks out 8 bits. To read, you have to do a dummy \ write of the value 0, then you can read the data from the spidata register.
-h# d4035000 value ssp-base \ SSP1 +h# 035000 value ssp-base \ SSP1 : ssp-sscr0 ( -- adr ) ssp-base ; : ssp-sscr1 ( -- adr ) ssp-base la1+ ; : ssp-sssr ( -- adr ) ssp-base 2 la+ ; @@ -14,9 +14,9 @@
: ssp-spi-start ( -- ) - h# 07 ssp-sscr0 l! - 0 ssp-sscr1 l! - h# 87 ssp-sscr0 l! + h# 07 ssp-sscr0 io! + 0 ssp-sscr1 io! + h# 87 ssp-sscr0 io! d# 46 gpio-set d# 46 gpio-dir-out h# c0 d# 46 af! @@ -25,7 +25,7 @@ : ssp-spi-cs-off ( -- ) d# 46 gpio-set ;
code ssp-spi-out-in ( bo -- bi ) - set r0,`ssp-base #` + set r0,`ssp-base +io #` begin ldr r1,[r0,#8] ands r1,r1,#4 @@ -39,14 +39,14 @@ c; 0 [if] : ssp-spi-out-in ( bo -- bi ) - begin ssp-sssr l@ 4 and until \ Tx not full - ssp-ssdr l! - begin ssp-sssr l@ 8 and until \ Rx not empty - ssp-ssdr l@ + begin ssp-sssr io@ 4 and until \ Tx not full + ssp-ssdr io! + begin ssp-sssr io@ 8 and until \ Rx not empty + ssp-ssdr io@ ; [then] code ssp-spi-in16 ( adr -- adr' ) - set r0,`ssp-base #` + set r0,`ssp-base +io #` set r2,#0xf04 set r3,#0xf008 mov r4,#0
Modified: cpu/arm/mmp2/thermal.fth ============================================================================== --- cpu/arm/mmp2/thermal.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/thermal.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -1,17 +1,17 @@ \ See license at end of file purpose: Driver for the MMP2 thermal sensor
-h# d4013200 value thermal-base +h# 013200 value thermal-base : init-thermal-sensor ( -- ) - thermal-base l@ h# 400 and if exit then - 3 h# d4015090 l! \ Enable clocks to thermal sensor - h# 10000 thermal-base l! \ Enable sensing + thermal-base io@ h# 400 and if exit then + 3 h# 015090 io! \ Enable clocks to thermal sensor + h# 10000 thermal-base io! \ Enable sensing ;
: cpu-temperature ( -- celcius ) 0 ( acc ) d# 100 0 do ( acc ) \ Accumulate 100 samples - thermal-base l@ ( acc reg ) + thermal-base io@ ( acc reg ) h# 3ff and ( acc val ) + ( acc' ) loop ( acc )
Modified: cpu/arm/mmp2/timer.fth ============================================================================== --- cpu/arm/mmp2/timer.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/timer.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -1,9 +1,9 @@ -: +!@ ( value offset base -- ) + tuck l! l@ drop ; +: +!@ ( value offset base -- ) + tuck io! io@ drop ; : timer! ( value offset -- ) timer-pa +!@ ; : init-timers ( -- ) - h# 13 h# 24 clock-unit-pa + l! - 0 h# 84 timer-pa + l! \ TMR_CER - count enable - begin h# 84 timer-pa + l@ 7 and 0= until + h# 13 h# 24 clock-unit-pa + io! + 0 h# 84 timer-pa + io! \ TMR_CER - count enable + begin h# 84 timer-pa + io@ 7 and 0= until h# 24 h# 00 timer-pa +!@ \ TMR_CCR - clock control h# 200 0 do loop 0 h# 88 timer! \ count mode - periodic @@ -24,7 +24,7 @@ [ifdef] arm-assembler code timer0@ ( -- n ) \ 6.5 MHz psh tos,sp - set r1,0xD4014000 + set r1,`h# 014000 +io #` mov r0,#1 str r0,[r1,#0xa4] mov r0,r0 @@ -33,7 +33,7 @@
code timer1@ ( -- n ) \ 32.768 kHz psh tos,sp - set r1,0xD4014000 + set r1,`h# 014000 +io #` mov r0,#1 str r0,[r1,#0xa8] mov r0,r0 @@ -42,45 +42,45 @@
code timer2@ ( -- n ) \ 1 kHz psh tos,sp - set r1,0xD4014000 + set r1,`h# 014000 +io #` mov r0,#1 str r0,[r1,#0xac] mov r0,r0 ldr tos,[r1,#0x30] c; [else] -: timer0@ ( -- n ) 1 h# d40140a4 l! h# d4014028 l@ ; -: timer1@ ( -- n ) 1 h# d40140a8 l! h# d401402c l@ ; -: timer2@ ( -- n ) 1 h# d40140ac l! h# d4014030 l@ ; +: timer0@ ( -- n ) 1 h# 0140a4 io! h# 014028 io@ ; +: timer1@ ( -- n ) 1 h# 0140a8 io! h# 01402c io@ ; +: timer2@ ( -- n ) 1 h# 0140ac io! h# 014030 io@ ; [then]
-: timer0-status@ ( -- n ) h# d4014034 l@ ; -: timer1-status@ ( -- n ) h# d4014038 l@ ; -: timer2-status@ ( -- n ) h# d401403c l@ ; - -: timer0-ier@ ( -- n ) h# d4014040 l@ ; -: timer1-ier@ ( -- n ) h# d4014044 l@ ; -: timer2-ier@ ( -- n ) h# d4014048 l@ ; - -: timer0-icr! ( n -- ) h# d4014074 l! ; -: timer1-icr! ( n -- ) h# d4014078 l! ; -: timer2-icr! ( n -- ) h# d401407c l! ; - -: timer0-ier! ( n -- ) h# d4014040 l! ; -: timer1-ier! ( n -- ) h# d4014044 l! ; -: timer2-ier! ( n -- ) h# d4014048 l! ; - -: timer0-match0! ( n -- ) h# d4014004 l! ; : timer0-match0@ ( -- n ) h# d4014004 l@ ; -: timer0-match1! ( n -- ) h# d4014008 l! ; : timer0-match1@ ( -- n ) h# d4014008 l@ ; -: timer0-match2! ( n -- ) h# d401400c l! ; : timer0-match2@ ( -- n ) h# d401400c l@ ; - -: timer1-match0! ( n -- ) h# d4014010 l! ; : timer1-match0@ ( -- n ) h# d4014010 l@ ; -: timer1-match1! ( n -- ) h# d4014014 l! ; : timer1-match1@ ( -- n ) h# d4014014 l@ ; -: timer1-match2! ( n -- ) h# d4014018 l! ; : timer1-match2@ ( -- n ) h# d4014018 l@ ; - -: timer2-match0! ( n -- ) h# d401401c l! ; : timer2-match0@ ( -- n ) h# d401401c l@ ; -: timer2-match1! ( n -- ) h# d4014020 l! ; : timer2-match1@ ( -- n ) h# d4014020 l@ ; -: timer2-match2! ( n -- ) h# d4014024 l! ; : timer2-match2@ ( -- n ) h# d4014024 l@ ; +: timer0-status@ ( -- n ) h# 014034 io@ ; +: timer1-status@ ( -- n ) h# 014038 io@ ; +: timer2-status@ ( -- n ) h# 01403c io@ ; + +: timer0-ier@ ( -- n ) h# 014040 io@ ; +: timer1-ier@ ( -- n ) h# 014044 io@ ; +: timer2-ier@ ( -- n ) h# 014048 io@ ; + +: timer0-icr! ( n -- ) h# 014074 io! ; +: timer1-icr! ( n -- ) h# 014078 io! ; +: timer2-icr! ( n -- ) h# 01407c io! ; + +: timer0-ier! ( n -- ) h# 014040 io! ; +: timer1-ier! ( n -- ) h# 014044 io! ; +: timer2-ier! ( n -- ) h# 014048 io! ; + +: timer0-match0! ( n -- ) h# 014004 io! ; : timer0-match0@ ( -- n ) h# 014004 io@ ; +: timer0-match1! ( n -- ) h# 014008 io! ; : timer0-match1@ ( -- n ) h# 014008 io@ ; +: timer0-match2! ( n -- ) h# 01400c io! ; : timer0-match2@ ( -- n ) h# 01400c io@ ; + +: timer1-match0! ( n -- ) h# 014010 io! ; : timer1-match0@ ( -- n ) h# 014010 io@ ; +: timer1-match1! ( n -- ) h# 014014 io! ; : timer1-match1@ ( -- n ) h# 014014 io@ ; +: timer1-match2! ( n -- ) h# 014018 io! ; : timer1-match2@ ( -- n ) h# 014018 io@ ; + +: timer2-match0! ( n -- ) h# 01401c io! ; : timer2-match0@ ( -- n ) h# 01401c io@ ; +: timer2-match1! ( n -- ) h# 014020 io! ; : timer2-match1@ ( -- n ) h# 014020 io@ ; +: timer2-match2! ( n -- ) h# 014024 io! ; : timer2-match2@ ( -- n ) h# 014024 io@ ;
' timer2@ to get-msecs : (ms) ( delay-ms -- )
Modified: cpu/arm/mmp2/twsi.fth ============================================================================== --- cpu/arm/mmp2/twsi.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/twsi.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -3,30 +3,30 @@ \ 0 0 " d4011000" " /" begin-package
[ifdef] unaligned-mmap -h# d4050000 unaligned-mmap constant clock-unit-pa +h# 050000 unaligned-mmap constant clock-unit-pa [then]
0 value twsi-chip 0 value clock-reg 0 value slave-address
-: dbr@ ( -- n ) twsi-chip h# 08 + l@ ; -: cr@ ( -- n ) twsi-chip h# 10 + l@ ; -: sr@ ( -- n ) twsi-chip h# 18 + l@ ; -: sar@ ( -- n ) twsi-chip h# 20 + l@ ; -: lcr@ ( -- n ) twsi-chip h# 28 + l@ ; -: dbr! ( n -- ) twsi-chip h# 08 + l! ; -: cr! ( n -- ) twsi-chip h# 10 + l! ; -: sr! ( n -- ) twsi-chip h# 18 + l! ; -: sar! ( n -- ) twsi-chip h# 20 + l! ; -: lcr! ( n -- ) twsi-chip h# 28 + l! ; +: dbr@ ( -- n ) twsi-chip h# 08 + io@ ; +: cr@ ( -- n ) twsi-chip h# 10 + io@ ; +: sr@ ( -- n ) twsi-chip h# 18 + io@ ; +: sar@ ( -- n ) twsi-chip h# 20 + io@ ; +: lcr@ ( -- n ) twsi-chip h# 28 + io@ ; +: dbr! ( n -- ) twsi-chip h# 08 + io! ; +: cr! ( n -- ) twsi-chip h# 10 + io! ; +: sr! ( n -- ) twsi-chip h# 18 + io! ; +: sar! ( n -- ) twsi-chip h# 20 + io! ; +: lcr! ( n -- ) twsi-chip h# 28 + io! ;
create channel-bases -h# D4011000 , h# D4031000 , h# D4032000 , h# D4033000 , h# D4033800 , h# D4034000 , +h# 011000 , h# 031000 , h# 032000 , h# 033000 , h# 033800 , h# 034000 ,
[ifdef] unaligned-mmap 6 0 do - channel-bases i la+ l@ unaligned-mmap channel-bases i la+ l! + channel-bases i la+ io@ unaligned-mmap channel-bases i la+ io! loop [then]
@@ -61,7 +61,7 @@ bbu_ICR_IUE bbu_ICR_SCLE or constant iue+scle : init-twsi-channel ( channel# -- ) set-twsi-channel - 7 clock-reg l! 3 clock-reg l! \ Set then clear reset bit + 7 clock-reg io! 3 clock-reg io! \ Set then clear reset bit 1 us iue+scle bbu_ICR_UR or cr! \ Reset the unit iue+scle cr! \ Release the reset
Modified: cpu/arm/mmp2/watchdog.fth ============================================================================== --- cpu/arm/mmp2/watchdog.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/mmp2/watchdog.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -2,18 +2,18 @@ purpose: System reset using the watchdog timer
: enable-wdt-clock - main-pmu-pa h# 1020 + dup l@ h# 10 or swap l! \ enable wdt 2 clock PMUM_PRR_PJ - 7 main-pmu-pa h# 200 + l! - 3 main-pmu-pa h# 200 + l! + main-pmu-pa h# 1020 + dup io@ h# 10 or swap io! \ enable wdt 2 clock PMUM_PRR_PJ + 7 main-pmu-pa h# 200 + io! + 3 main-pmu-pa h# 200 + io! ;
-h# d4080000 value wdt-pa -: (wdt!) ( value offset -- ) wdt-pa + l! ; +h# 080000 value wdt-pa +: (wdt!) ( value offset -- ) wdt-pa + io! ; : wdt! ( value offset -- ) h# baba h# 9c (wdt!) h# eb10 h# a0 (wdt!) ( value offset ) (wdt!) ; -: wdt@ ( offset -- value ) wdt-pa + l@ ; +: wdt@ ( offset -- value ) wdt-pa + io@ ; : wdt-reset ( -- ) enable-wdt-clock 2 h# 68 wdt! \ set match register
Modified: cpu/arm/olpc/1.75/addrs.fth ============================================================================== --- cpu/arm/olpc/1.75/addrs.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/olpc/1.75/addrs.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -24,6 +24,7 @@ : (memory?) ( phys -- flag ) total-ram-size u< ;
\ OFW implementation choices +h# d400.0000 constant io-pa h# 1fa0.0000 constant fw-pa
h# 1f00.0000 constant dma-base @@ -32,12 +33,19 @@ h# 1f80.0000 constant extra-mem-pa h# 20.0000 constant /extra-mem
+h# ef00.0000 constant dma-va +h# ef80.0000 constant extra-mem-va +h# efa0.0000 constant fw-va +h# efc0.0000 constant fb-va +h# fe00.0000 constant io-va + [ifdef] virtual-mode h# f700.0000 constant fw-virt-base h# 0100.0000 constant fw-virt-size \ 16 megs of mapping space [else] -fw-pa value fw-virt-base -0 value fw-virt-size +\ fw-pa value fw-virt-base +fw-va value fw-virt-base +h# 20.0000 value fw-virt-size [then]
h# 0020.0000 constant /fw-ram
Modified: cpu/arm/olpc/1.75/bbedi.fth ============================================================================== --- cpu/arm/olpc/1.75/bbedi.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/olpc/1.75/bbedi.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -48,7 +48,7 @@
code edi-bit! ( flag -- ) mov r0,#0x200 - set r1,#0xd4019100 + set r1,`h# 19100 +io #` cmp tos,#0 streq r0,[r1,#0x24] \ Clr MOSI if flag is 0 strne r0,[r1,#0x18] \ Set MOSI if flag is non0 @@ -71,13 +71,13 @@ [ifndef] edi-bit! : edi-bit! ( flag -- ) if - [ edi-mosi-gpio# >gpio-pin h# 18 + ] dliteral l! \ Fast gpio-set + [ edi-mosi-gpio# >gpio-pin h# 18 + ] dliteral io! \ Fast gpio-set else - [ edi-mosi-gpio# >gpio-pin h# 24 + ] dliteral l! \ Fast gpio-clr + [ edi-mosi-gpio# >gpio-pin h# 24 + ] dliteral io! \ Fast gpio-clr then - [ edi-clk-gpio# >gpio-pin h# 18 + ] dliteral l! \ Fast gpio-set + [ edi-clk-gpio# >gpio-pin h# 18 + ] dliteral io! \ Fast gpio-set \ edi-dly - [ edi-clk-gpio# >gpio-pin h# 24 + ] dliteral l! \ Fast gpio-set + [ edi-clk-gpio# >gpio-pin h# 24 + ] dliteral io! \ Fast gpio-set \ edi-dly ; [then] @@ -105,9 +105,9 @@ [else] code edi-out0 ( byte -- ) mov r2,#8 - mov r0,#0x200 \ MOSI mask - set r1,#0xd4019100 \ GPIO register address - mov r4,#0x400 \ CLK mask + mov r0,#0x200 \ MOSI mask + set r1,`h# 19100 +io #` \ GPIO register address + mov r4,#0x400 \ CLK mask begin ands r3,tos,#0x80 \ Test bit
@@ -125,10 +125,10 @@ c; code edi-out ( byte -- ) mov r2,#8 - mov r0,#0x200 \ MOSI mask - set r1,#0xd4019100 \ GPIO register address - mov r4,#0x400 \ CLK mask - mov r5,#0x600 \ CLK and MOSI mask + mov r0,#0x200 \ MOSI mask + set r1,`h# 19100 +io #` \ GPIO register address + mov r4,#0x400 \ CLK mask + mov r5,#0x600 \ CLK and MOSI mask begin ands r3,tos,#0x80 \ Test bit
@@ -146,11 +146,11 @@ c; code edi-in ( -- byte ) psh tos,sp - mov tos,#0 \ Initial byte value + mov tos,#0 \ Initial byte value mov r2,#8 mov r3,#0x100 - set r1,#0xd4019100 \ GPIO register address - mov r4,#0x400 \ CLK mask + set r1,`h# 19100 +io #` \ GPIO register address + mov r4,#0x400 \ CLK mask begin add tos,tos,tos \ Left shift byte
Modified: cpu/arm/olpc/1.75/devices.fth ============================================================================== --- cpu/arm/olpc/1.75/devices.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/olpc/1.75/devices.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -1,18 +1,19 @@ fload ${BP}/dev/omap/diaguart.fth \ OMAP UART -h# d4018000 to uart-base \ UART3 base address on MMP2 -\ h# d4030000 to uart-base \ UART1 base address on MMP2 + +h# 18000 +io to uart-base \ UART3 base address on MMP2 +\ h# 30000 +io to uart-base \ UART1 base address on MMP2 d# 26000000 to uart-clock-frequency
: init-clocks - -1 h# d4051024 l! \ PMUM_CGR_PJ - everything on - h# 07 h# d4015064 l! \ APBC_AIB_CLK_RST - reset, functional and APB clock on - h# 03 h# d4015064 l! \ APBC_AIB_CLK_RST - release reset, functional and APB clock on - h# 13 h# d401502c l! \ APBC_UART1_CLK_RST - VCTCXO, functional and APB clock on (26 mhz) - h# 13 h# d4015034 l! \ APBC_UART3_CLK_RST - VCTCXO, functional and APB clock on (26 mhz) - h# c1 h# d401e0c8 l! \ GPIO29 = af1 for UART1 RXD - h# c1 h# d401e0cc l! \ GPIO30 = af1 for UART1 TXD - h# c4 h# d401e260 l! \ GPIO115 = af4 for UART3 RXD - h# c4 h# d401e264 l! \ GPIO116 = af4 for UART3 TXD + -1 h# 51024 io! \ PMUM_CGR_PJ - everything on + h# 07 h# 15064 io! \ APBC_AIB_CLK_RST - reset, functional and APB clock on + h# 03 h# 15064 io! \ APBC_AIB_CLK_RST - release reset, functional and APB clock on + h# 13 h# 1502c io! \ APBC_UART1_CLK_RST - VCTCXO, functional and APB clock on (26 mhz) + h# 13 h# 15034 io! \ APBC_UART3_CLK_RST - VCTCXO, functional and APB clock on (26 mhz) + h# c1 h# 1e0c8 io! \ GPIO29 = af1 for UART1 RXD + h# c1 h# 1e0cc io! \ GPIO30 = af1 for UART1 TXD + h# c4 h# 1e260 io! \ GPIO115 = af4 for UART3 RXD + h# c4 h# 1e264 io! \ GPIO116 = af4 for UART3 TXD ;
: inituarts ( -- ) @@ -334,7 +335,7 @@ fload ${BP}/cpu/arm/marvell/utmiphy.fth
: init-usb ( -- ) - h# 9 h# d428285c l! \ Enable clock to USB block + h# 9 h# 28285c io! \ Enable clock to USB block reset-usb-hub init-usb-phy ;
Modified: cpu/arm/olpc/1.75/fw.bth ============================================================================== --- cpu/arm/olpc/1.75/fw.bth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/olpc/1.75/fw.bth Tue Jul 19 01:05:05 2011 (r2390) @@ -61,8 +61,8 @@ h# 41000501 tag-l, \ ATAG_MEM cif-handler tag-l, \ Client interface handler callback address page-table@ tag-l, \ OFW's top-level page tables - extra-mem-pa d# 20 >> tag-l, \ First section entry number - fw-pa /fw-ram + extra-mem-pa - d# 20 >> tag-l, \ Number of section entries + extra-mem-va d# 20 >> tag-l, \ First section entry number + fw-virt-base /fw-ram + extra-mem-va - d# 20 >> tag-l, \ Number of section entries ; ' (ofw-tag,) to ofw-tag,
Modified: cpu/arm/olpc/1.75/lcd.fth ============================================================================== --- cpu/arm/olpc/1.75/lcd.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/olpc/1.75/lcd.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -1,13 +1,13 @@
-: lcd@ ( offset -- l ) lcd-pa + l@ ; -: lcd! ( l offset -- ) lcd-pa + l! ; +: lcd@ ( offset -- l ) lcd-pa + io@ ; +: lcd! ( l offset -- ) lcd-pa + io! ;
: init-lcd ( -- ) \ Turn on clocks - h# 08 pmua-disp-clk-sel + h# d428284c l! - h# 09 pmua-disp-clk-sel + h# d428284c l! - h# 19 pmua-disp-clk-sel + h# d428284c l! - h# 1b pmua-disp-clk-sel + h# d428284c l! + h# 08 pmua-disp-clk-sel + h# 28284c io! + h# 09 pmua-disp-clk-sel + h# 28284c io! + h# 19 pmua-disp-clk-sel + h# 28284c io! + h# 1b pmua-disp-clk-sel + h# 28284c io!
0 h# 190 lcd! \ Disable LCD DMA controller fb-pa h# f4 lcd! \ Frame buffer area 0 @@ -148,9 +148,8 @@ 0 value cursor-w 0 value cursor-h
-: enable-cursor-writes ( -- ) - h# 8000 h# 1a4 lcd-set \ allow writes to cursor SRAM -; +\ allow writes to cursor SRAM +: enable-cursor-writes ( -- ) h# 8000 h# 1a4 lcd-set ;
0 value #cursor-bits 0 value cursor-bits
Modified: cpu/arm/olpc/1.75/prefw.bth ============================================================================== --- cpu/arm/olpc/1.75/prefw.bth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/olpc/1.75/prefw.bth Tue Jul 19 01:05:05 2011 (r2390) @@ -21,17 +21,9 @@ : \Tags [compile] \ ; immediate : \NotTags [compile] \ ; immediate
-: RAMbase ( -- adr ) fw-virt-base ; -: RAMtop ( -- adr ) RAMbase /fw-ram + ; - def-load-base ' load-base set-config-int-default
-\ use-movable-vector-base \ Marvell CPU core has a movable vector base - true ' fcode-debug? set-config-int-default -\ false ' auto-boot? set-config-int-default - -
[ifdef] serial-console " com1" ' output-device set-config-string-default @@ -60,10 +52,12 @@ fload ${BP}/ofw/core/clntmem1.fth \ client services for memory [else] fload ${BP}/ofw/core/clntphy1.fth \ client services for memory +defer section-table : >physical ( va -- pa ) - dup fw-virt-base - fw-virt-size u< if ( va ) - fw-virt-base - fw-pa + - then + dup d# 20 rshift ( va section-index ) + section-table swap la+ l@ ( va pte ) + h# fffff invert and ( va pa-base ) + swap h# fffff and or ( pa ) ; [then]
@@ -85,6 +79,7 @@ fload ${BP}/arch/arm/loadarea.fth \ Allocate and map program load area [else] fload ${BP}/cpu/arm/mmp2/mmuon.fth +' page-table@ to section-table [then]
\ XXX should be elsewhere @@ -168,6 +163,11 @@
fload ${BP}/forth/lib/selstr.fth
+\ : +io ( offset -- va ) io-va + ; +: +io ( offset -- va ) dup h# 0040.0000 >= if debug-me then io-va + ; +: io! ( value offset -- ) +io l! ; +: io@ ( offset -- value ) +io l@ ; + fload ${BP}/cpu/arm/mmp2/hash.fth \ Hashes - SHA1, SHA-256, MD5 fload ${BP}/cpu/x86/pc/olpc/crypto.fth \ Cryptographic image validation fload ${BP}/cpu/x86/pc/olpc/lzip.fth \ Access zip images from memory
Modified: cpu/arm/olpc/1.75/sdhci.fth ============================================================================== --- cpu/arm/olpc/1.75/sdhci.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/olpc/1.75/sdhci.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -43,9 +43,9 @@ end-package
stand-init: SDHC clocks - h# 41b h# d4282854 l! \ SD0 (external SD) clocks, plus set master clock divisor - h# 1b h# d4282858 l! \ SD1 (WLAN) clocks - h# 1b h# d42828e8 l! \ SD2 (internal microSD) clocks - h# 70a h# d4200104 l! \ Clock gating - h# 70a h# d4201104 l! \ Clock gating + h# 41b h# 282854 io! \ SD0 (external SD) clocks, plus set master clock divisor + h# 1b h# 282858 io! \ SD1 (WLAN) clocks + h# 1b h# 2828e8 io! \ SD2 (internal microSD) clocks + h# 70a h# 200104 io! \ Clock gating + h# 70a h# 201104 io! \ Clock gating ;
Modified: cpu/arm/olpc/1.75/sound.fth ============================================================================== --- cpu/arm/olpc/1.75/sound.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/olpc/1.75/sound.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -2,19 +2,18 @@ " audio" name my-space h# 800 reg
-0 value sspa-base \ E.g. h# d42a.0c00 -0 value adma-base \ E.g. h# d42a.0800 -: sspa! ( n offset -- ) sspa-base + l! ; \ Write a register in SSPA1 -: sspa@ ( offset -- n ) sspa-base + l@ ; \ Read a register in SSPA1 -: adma! ( n offset -- ) adma-base + l! ; -: adma@ ( offset -- n ) adma-base + l@ ; +0 value sspa-base \ E.g. h# 2a.0c00 +io +0 value adma-base \ E.g. h# 2a.0800 +io +: sspa! ( n offset -- ) sspa-base + rl! ; \ Write a register in SSPA1 +: sspa@ ( offset -- n ) sspa-base + rl@ ; \ Read a register in SSPA1 +: adma! ( n offset -- ) adma-base + rl! ; +: adma@ ( offset -- n ) adma-base + rl@ ;
: audio-clock-on ( -- ) - h# 600 h# d428.290c l! d# 10 us \ Enable - h# 610 h# d428.290c l! d# 10 us \ Release reset - h# 710 h# d428.290c l! d# 10 us \ Enable - h# 712 h# d428.290c l! d# 10 us \ Release reset - + h# 600 h# 28.290c io! d# 10 us \ Enable + h# 610 h# 28.290c io! d# 10 us \ Release reset + h# 710 h# 28.290c io! d# 10 us \ Enable + h# 712 h# 28.290c io! d# 10 us \ Release reset
[ifdef] 24mhz \ * 10 / 27 gives about 147.456 @@ -22,17 +21,17 @@ \ But the M/N divisors always have an implicit /2 (section 7.3.7 in datasheet), \ so the input frequency is 99.67 with respect to NOM (sic) and DENOM. \ we want 24.576 MHz SYSCLK. 99.67 * 18 / 73 = 24.575 so 50 ppm error. - d# 18 d# 15 lshift d# 73 or h# d000.0000 or h# d4050040 l! + d# 18 d# 15 lshift d# 73 or h# d000.0000 or h# 050040 io! [else] \ * 10 / 27 gives about 147.456 \ The M/N divisor gets 199.33 MHz (Figure 283 - clock tree - in Datasheet) \ But the M/N divisors always have an implicit /2 (section 7.3.7 in datasheet), \ so the input frequency is 99.67 with respect to NOM (sic) and DENOM. \ we want 12.288 MHz SYSCLK. 99.67 * 9 / 73 = 12.2876 so 50 ppm error. - d# 9 d# 15 lshift d# 73 or h# d000.0000 or h# d4050040 l! + d# 9 d# 15 lshift d# 73 or h# d000.0000 or h# 050040 io! [then]
- h# d405.0024 l@ h# 20 or h# d405.0024 l! \ Enable 12S clock out to SSPA1 + h# 05.0024 io@ h# 20 or h# 05.0024 io! \ Enable 12S clock out to SSPA1
h# 10800 h# 38 sspa!
Modified: cpu/arm/olpc/initmmu.fth ============================================================================== --- cpu/arm/olpc/initmmu.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/olpc/initmmu.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -175,6 +175,21 @@ mov pc, lr end-code
+\ Map sections within the given address range, using +\ the given protection/cacheability mode. pt-adr is the page table base address. +label map-sections ( r0: pt-adr, r1: padr, r2: len, r3: mode r4: vadr -- ) + add r1, r1, r3 \ PA+mode + begin + str r1, [r0, r4, lsr #18] + + inc r1, #0x100000 + inc r4, #0x100000 + decs r2, #0x100000 + 0<= until + + mov pc, lr +end-code + \ Map sections virtual=physical within the given address range, using \ the given protection/cacheability mode. pt-adr is the page table base address. label map-sections-v=p ( r0: pt-adr, r1: adr, r2: len, r3: mode -- ) @@ -245,6 +260,30 @@ set r3,#0xc02 \ No caching or write buffering bl `map-sections-v=p`
+ set r1,`dma-base #` \ Address of DMA area + set r2,`dma-size #` \ Size of DMA area + set r3,#0xc02 \ No caching or write buffering + set r4,`dma-va #` \ Virtual address + bl `map-sections` + + set r1,`extra-mem-pa #` \ Address of additional allocatable memory + set r2,`/extra-mem #` \ Size of additional allocatable memory + set r3,#0xc0e \ Write bufferable + set r4,`extra-mem-va #' \ Virtual address + bl `map-sections` + + set r1,`fw-pa #` \ Address of Firmware region + set r2,`/fw-ram #` \ Size of firmware region + set r3,#0xc0e \ Write bufferable + set r4,`fw-va #` \ Virtual address + bl `map-sections` + + set r1,#0xd4000000 \ Address of I/O + set r2,#0x00400000 \ Size of I/O region + set r3,#0xc02 \ No caching or write buffering + set r4,`io-va #` \ Virtual address + bl `map-sections` + \ The cache is not on yet \ set r1,#0x4000 \ Size of section table \ bl `clean-dcache-range`
Modified: cpu/arm/olpc/resetvec.bth ============================================================================== --- cpu/arm/olpc/resetvec.bth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/olpc/resetvec.bth Tue Jul 19 01:05:05 2011 (r2390) @@ -147,7 +147,7 @@
\ Setup the page (section) table and turn on the MMU and caches \ set r0,`page-table-pa #` - set r0,`fw-virt-base page-table-offset + #` + set r0,`fw-pa page-table-offset + #` bl `init-map` \ Setup the initial virtual address map bl `enable-mmu` \ Turn on the MMU bl `caches-on` \ Turn on the caches
Modified: cpu/arm/olpc/spcmd.fth ============================================================================== --- cpu/arm/olpc/spcmd.fth Mon Jul 18 12:56:15 2011 (r2389) +++ cpu/arm/olpc/spcmd.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -89,8 +89,8 @@ ;
0 value reg-base -: reg@ ( offset -- l ) reg-base + l@ ; -: reg! ( l offset -- ) reg-base + l! ; +: reg@ ( offset -- l ) reg-base + rl@ ; +: reg! ( l offset -- ) reg-base + rl! ;
: data? ( -- flag ) h# c8 reg@ 1 and ; : send-rdy ( -- ) h# ff00 h# 40 reg! ;
Modified: dev/olpc/kb3700/spicmd.fth ============================================================================== --- dev/olpc/kb3700/spicmd.fth Mon Jul 18 12:56:15 2011 (r2389) +++ dev/olpc/kb3700/spicmd.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -114,10 +114,10 @@ enable ;
-\ : ssp1-clk-on 7 h# d4015050 l! 3 h# d4015050 l! ; -\ : ssp2-clk-on 7 h# d4015054 l! 3 h# d4015052 l! ; -: ssp3-clk-on 7 h# d4015058 l! 3 h# d4015058 l! ; -\ : ssp4-clk-on 7 h# d401505c l! 3 h# d401505c l! ; +\ : ssp1-clk-on 7 h# 015050 io! 3 h# 015050 io! ; +\ : ssp2-clk-on 7 h# 015054 io! 3 h# 015052 io! ; +: ssp3-clk-on 7 h# 015058 io! 3 h# 015058 io! ; +\ : ssp4-clk-on 7 h# 01505c io! 3 h# 01505c io! ;
: wb ( byte -- ) ssp-ssdr rl! ; \ Debugging tool : rb ( -- byte ) ssp-ssdr rl@ . ; \ Debugging tool @@ -147,10 +147,10 @@ then ; : prime-fifo ( -- ) - ssp-rx-threshold 0 ?do 0 ssp-ssdr l! loop + ssp-rx-threshold 0 ?do 0 ssp-ssdr rl! loop ; : rxflush ( -- ) - begin ssp-sssr rl@ 8 and while ssp-ssdr l@ drop repeat + begin ssp-sssr rl@ 8 and while ssp-ssdr rl@ drop repeat ; : ssp-ready? ( -- flag ) rxavail ssp-rx-threshold >= ;
Modified: dev/olpc/mmp2camera/ccic.fth ============================================================================== --- dev/olpc/mmp2camera/ccic.fth Mon Jul 18 12:56:15 2011 (r2389) +++ dev/olpc/mmp2camera/ccic.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -74,8 +74,8 @@
: power-on ( -- ) \ Enable clocks - h# 3f h# d4282828 l! \ Clock gating - AHB, Internal PIXCLK, AXI clock always on - h# 0003.805b h# d4282850 l! \ PMUA clock config for CCIC - /1, PLL1/16, AXI arb, AXI, perip on + h# 3f h# 282828 io! \ Clock gating - AHB, Internal PIXCLK, AXI clock always on + h# 0003.805b h# 282850 io! \ PMUA clock config for CCIC - /1, PLL1/16, AXI arb, AXI, perip on
\ h# 0000.0002 h# 88 cl! \ Clock select - PIXMCLK, 797/2 (PLL1/16) / 2 -> 24.9 MHz \ h# 4000.0002 h# 88 cl! \ Clock select - AXI, 797/2 (PLL1/16) / 2 -> 24.9 MHz @@ -158,6 +158,7 @@ interrupts-off power-off free-dma-bufs + camera-base h# 1000 " map-out" $call-parent ;
@@ -251,6 +252,7 @@
: selftest ( -- error? ) open 0= if true exit then + my-address my-space h# 1000 " map-in" $call-parent to camera-base d# 300 ms start-display unmirrored shoot-still ?dup if close exit then ( error? )
Modified: dev/olpc/mmp2camera/platform.fth ============================================================================== --- dev/olpc/mmp2camera/platform.fth Mon Jul 18 12:56:15 2011 (r2389) +++ dev/olpc/mmp2camera/platform.fth Tue Jul 19 01:05:05 2011 (r2390) @@ -27,6 +27,6 @@ \ PIXMCLK on GPIO69, PIXCLK on GPIO70, PIXDATA[7:0] on GPIO[59:66] \ CAM_SCL on GPIO108, CAM_SDA on GPIO109 (bitbang)
-: cl! ( l adr -- ) h# d420a000 + rl! ; -: cl@ ( adr -- l ) h# d420a000 + rl@ ; - +0 value camera-base +: cl! ( l adr -- ) camera-base + rl! ; +: cl@ ( adr -- l ) camera-base + rl@ ;