Author: wmb Date: 2009-11-06 07:34:27 +0000 (Fri, 06 Nov 2009) New Revision: 1460
Modified: cpu/x86/pc/olpc/via/demodram.fth cpu/x86/pc/olpc/via/dramtiming.fth cpu/x86/pc/olpc/via/dumpvia.fth cpu/x86/pc/olpc/via/fw.bth cpu/x86/pc/olpc/via/ioinit.fth cpu/x86/pc/olpc/via/pcinode.fth cpu/x86/pc/olpc/via/romreset.bth cpu/x86/pc/olpc/via/startcominit.fth cpu/x86/pc/olpc/via/startgfxinit.fth cpu/x86/pc/olpc/via/startgtlinit.fth cpu/x86/pc/olpc/via/starthostctl.fth Log: Via - big mess o' tweaks to PCI config register values to make the settings match the Phoenix values as closely as possible. Trying to sort out why the screen tears on graphics accelerator operations in X, so minimizing differences from non-tearing case.
Modified: cpu/x86/pc/olpc/via/demodram.fth =================================================================== --- cpu/x86/pc/olpc/via/demodram.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/demodram.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -19,7 +19,8 @@ [then] [ifdef] xo-board \ 0 3 devfunc 90 07 03 mreg end-table d# 20 wait-us \ 200 MHz ATEST - 0 3 devfunc 90 e7 03 mreg end-table d# 20 wait-us \ 200 MHz ATEST +\ 0 3 devfunc 90 e7 03 mreg end-table d# 20 wait-us \ 200 MHz ATEST + 0 3 devfunc 90 ff c3 mreg end-table d# 20 wait-us \ 200 MHz ATEST [then] 0 3 devfunc 6b d0 c0 mreg end-table d# 20 wait-us \ PLL Off 0 3 devfunc 6b 00 10 mreg end-table d# 20 wait-us \ PLL On @@ -207,10 +208,12 @@ \ DQSInputCaptureCtrl 77 bf 9b mreg \ DQS Input Delay - Manual, value from VIA's BIOS 78 3f 01 mreg \ 533: 3 667: 7 800: d DQS Input Capture Range Control A - 79 ff 83 mreg \ 533: 87 667: 89 800: 89 +\ 79 ff 83 mreg \ 533: 87 667: 89 800: 89 + 79 ff 80 mreg \ Reserved, perhaps for the snapshot RAM ? Phoenix value 7a ff 00 mreg \ Reserved 7b ff 10 mreg \ 533: 20 667: 34 800: 34 Read Data Phase Control - 8b ff 10 mreg \ 533: 20 667: 34 800: 34 +\ 8b ff 10 mreg \ 533: 20 667: 34 800: 34 + 8b ff 02 mreg \ Phoenix value [then]
\ DCLKPhsCtrl - depends on which clock outputs are used @@ -218,7 +221,7 @@ 99 1e 12 mreg \ MCLKOA[3,2,1,0] outputs [then] [ifdef] xo-board - 99 1e 1e mreg \ MCLKOA[1,0] outputs + 99 1e 06 mreg \ MCLKOA[1,0] outputs [then] end-table
@@ -368,11 +371,12 @@
forth #ranks 3 < assembler [if] 55 ff 00 mreg \ Rank map A 2/3 2 & 3 off -[then] -forth #ranks 3 = assembler [if] +[else] + forth #ranks 3 = assembler [if] 55 ff a0 mreg \ Rank map A 2/3 2 on 3 off -[else] + [else] 55 ff ab mreg \ Rank map A 2/3 2 & 3 on + [then] [then]
56 ff 00 mreg \ Rank map B ? @@ -402,6 +406,12 @@
h# 15 port80
+ 0 3 devfunc + 52 77 11 mreg \ BA1 is A14, BA0 is A13 + 53 30 10 mreg \ BA2 is A15 + 69 20 20 mreg \ Bank address scramble + end-table + 0 [if] \ Very simple memtest long-offsets on ax ax xor @@ -463,6 +473,7 @@ [then] [ifdef] xo-board 96 0f 01 mreg \ Enable self-refresh for rank 0 + b1 ff aa mreg \ Reserved - Phoenix value [then]
end-table
Modified: cpu/x86/pc/olpc/via/dramtiming.fth =================================================================== --- cpu/x86/pc/olpc/via/dramtiming.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/dramtiming.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -32,7 +32,8 @@ \ DDR-400 timings for HY5PS1G4831C d# 5.00 to Tck
-d# 127.50 constant Trfc +\ d# 127.50 constant Trfc +d# 125.00 constant Trfc \ Fudged to get same setting as Phoenix d# 7.50 constant Trrd \ d# 10.00 constant Trrd d# 3 constant TCL @@ -86,7 +87,8 @@ rank-size #ranks * constant total-size [then]
-h# 400.0000 constant /fbmem +\ h# 400.0000 constant /fbmem +h# 1000.0000 constant /fbmem : >fbmem-base ( size/64M -- low high ) d# 26 lshift ( memsize-in-bytes ) /fbmem - ( memsize-less-framebuf-size )
Modified: cpu/x86/pc/olpc/via/dumpvia.fth =================================================================== --- cpu/x86/pc/olpc/via/dumpvia.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/dumpvia.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -12,41 +12,47 @@ : seq@ ( index -- value ) h# 3c4 pc! h# 3c5 pc@ ; : grf@ ( index -- value ) h# 3ce pc! h# 3cf pc@ ; : crt@ ( index -- value ) h# 3d4 pc! h# 3d5 pc@ ; -: seq. ( adr len -- ) bounds ?do i c@ seq@ 3 u.r loop ; +: .byte ( n -- ) push-hex 2 0.r space pop-base ; +: seq. ( adr len -- ) bounds ?do i c@ seq@ .byte loop ; : .regular - ." ATR " h# 15 0 do i attr@ 3 u.r loop cr + ." == VGA Registers - A=Attribute G=Graphics C=CRT S=Sequencer" cr + ." 0 1 2 3 4 5 6 7 8 9 a b c d e f" cr + ." MSC: " h# 3cc pc@ .byte cr + ." A00: " h# 10 0 do i attr@ .byte loop cr + ." A10: " h# 15 h# 10 do i attr@ .byte loop cr h# 20 video-mode! - ." SEQ " 5 0 do i seq@ 3 u.r loop cr - ." GRF " 9 0 do i grf@ 3 u.r loop cr -." 0 1 2 3 4 5 6 7 8 9 a b c d e f" cr - ." C00 " h# 10 0 do i crt@ 3 u.r loop cr - ." C10 " h# 19 h# 10 do i crt@ 3 u.r loop cr + ." G00: " 9 0 do i grf@ .byte loop cr + ." G20: " h# 23 h# 20 do i grf@ .byte loop cr ; -: .sextended - ." S10 " h# 1f h# 10 do i seq@ 3 u.r loop cr - ." S20 " " "(20 21 22 26 2a 2b 2c 2d 2e)" seq. cr - ." S30 " " "(31 35 36 3c 3d 3e 3f)" seq. cr - ." S40 " h# 50 h# 40 do i seq@ 3 u.r loop cr - ." S50 " h# 60 h# 50 do i seq@ 3 u.r loop cr - ." S60 " h# 70 h# 60 do i seq@ 3 u.r loop cr - ." S70 " h# 80 h# 70 do i seq@ 3 u.r loop cr - ." SA8 " h# b0 h# a8 do i seq@ 3 u.r loop cr - ." G20 " h# 23 h# 20 do i grf@ 3 u.r loop cr +: .seq + ." S00: " h# 10 0 do i seq@ .byte loop cr + ." S10: " h# 20 h# 10 do i seq@ .byte loop cr +\ ." S20 " " "(20 21 22 26 2a 2b 2c 2d 2e)" seq. cr +\ ." S30 " " "(31 35 36 3c 3d 3e 3f)" seq. cr + ." S20: " h# 30 h# 20 do i seq@ .byte loop cr + ." S30: " h# 40 h# 30 do i seq@ .byte loop cr + ." S40: " h# 50 h# 40 do i seq@ .byte loop cr + ." S50: " h# 60 h# 50 do i seq@ .byte loop cr + ." S60: " h# 70 h# 60 do i seq@ .byte loop cr + ." S70: " h# 80 h# 70 do i seq@ .byte loop cr + ." SA0: " h# b0 h# a0 do i seq@ .byte loop cr ; -: .cextended - ." C30 " h# 40 h# 30 do i crt@ 3 u.r loop cr - ." C40 " h# 49 h# 40 do i crt@ 3 u.r loop cr - ." C50 " h# 60 h# 50 do i crt@ 3 u.r loop cr - ." C60 " h# 70 h# 60 do i crt@ 3 u.r loop cr - ." C70 " h# 80 h# 70 do i crt@ 3 u.r loop cr - ." C80 " h# 90 h# 80 do i crt@ 3 u.r loop cr - ." C90 " h# a0 h# 90 do i crt@ 3 u.r loop cr - ." CA0 " h# b0 h# a0 do i crt@ 3 u.r loop cr - ." CD0 " h# e0 h# d0 do i crt@ 3 u.r loop cr - ." CE0 " h# f0 h# e0 do i crt@ 3 u.r loop cr - ." CF0 " h# fd h# f0 do i crt@ 3 u.r loop cr +: .crt + ." C00: " h# 10 0 do i crt@ .byte loop cr + ." C10: " h# 20 h# 10 do i crt@ .byte loop cr + ." C30: " h# 40 h# 30 do i crt@ .byte loop cr + ." C40: " h# 50 h# 40 do i crt@ .byte loop cr + ." C50: " h# 60 h# 50 do i crt@ .byte loop cr + ." C60: " h# 70 h# 60 do i crt@ .byte loop cr + ." C70: " h# 80 h# 70 do i crt@ .byte loop cr + ." C80: " h# 90 h# 80 do i crt@ .byte loop cr + ." C90: " h# a0 h# 90 do i crt@ .byte loop cr + ." CA0: " h# b0 h# a0 do i crt@ .byte loop cr + ." CD0: " h# e0 h# d0 do i crt@ .byte loop cr + ." CE0: " h# f0 h# e0 do i crt@ .byte loop cr + ." CF0: " h# fd h# f0 do i crt@ .byte loop cr ; -: .dpy .regular .cextended .sextended ; +: .dpy .regular .crt .seq ;
\ b0 8b0 config-b@ -> 1 ( VGA in S.L.) \ b2 8b2 config-b@ -> 40 ( 256 MB memory base 0) @@ -58,6 +64,49 @@ : cw. dup (.2) type ." : " config-base + config-w@ (.4) type cr ; : cb. dup (.2) type ." : " config-base + config-b@ (.2) type cr ; : ch. config-base h# 40 bounds do i config-l@ u. 4 +loop cr ; +: .devfunc ( device function -- ) + ." == Device " swap .x ." Function " .x cr +; +: disabled? ( device function -- true | cfgaddr false ) + 2dup .devfunc ( device function ) + h# 100 * swap h# 800 * + ( base ) + dup config-l@ h# ffffffff = if ." Disabled" cr drop true exit then ( cfgaddr ) + false +; +defer dump-devfunc ( device function -- ) +: 0.r.upc + >r (u.) r> over - 0 max 0 ?do + 30 emit + loop 2dup upper type +; + +: dump-devfunc-via ( device function -- ) + disabled? if exit then ( cfgaddr ) + h# 100 0 do + i 8 bounds do + i 2 0.r.upc ." =" dup i + config-b@ 2 0.r.upc + i h# f and h# f <> if space then + loop + cr + h# 8 +loop + drop +; +: dump-devfunc-lspci ( device function -- ) + disabled? if exit then ( cfgaddr ) + h# 100 0 do + i 2 0.r ." : " + i h# 10 bounds do + dup i + config-b@ 2 0.r + i h# f and h# f <> if space then + loop + cr + h# 10 +loop + drop +; +: via-dump-mode ['] dump-devfunc-via to dump-devfunc ; +: lspci-dump-mode ['] dump-devfunc-lspci to dump-devfunc ; +via-dump-mode + : dump-d0f0 0 to config-base ." == D0F0 Host Control ==" cr @@ -706,7 +755,7 @@ cr ;
-: dump-config-regs +: dump-config-regs-old dump-d0f0 dump-d0f1 dump-d0f2 @@ -726,6 +775,21 @@ dump-d20f0 ;
+: dump-config-regs ( -- ) + 8 0 do 0 i dump-devfunc cr loop + d# 1 d# 0 dump-devfunc cr + d# 12 d# 0 dump-devfunc cr + d# 15 d# 0 dump-devfunc cr + d# 16 d# 0 dump-devfunc cr + d# 16 d# 1 dump-devfunc cr + d# 16 d# 2 dump-devfunc cr + d# 16 d# 4 dump-devfunc cr + d# 17 d# 0 dump-devfunc cr + d# 17 d# 7 dump-devfunc cr + d# 19 d# 0 dump-devfunc cr + d# 20 d# 0 dump-devfunc cr +; + [ifdef] apic-ih : ap. ( index -- ) dup (.4) type ." : " ( index ) @@ -791,4 +855,5 @@ dump-apic dump-io-apic [then] + .dpy ;
Modified: cpu/x86/pc/olpc/via/fw.bth =================================================================== --- cpu/x86/pc/olpc/via/fw.bth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/fw.bth 2009-11-06 07:34:27 UTC (rev 1460) @@ -629,6 +629,11 @@ ; [then]
+: pci-fixup ( -- ) + h# 43 h# 8804 config-b! \ Enable parity checking on D17F0 + h# 0800 h# 8f0c config-w! \ Override pcibus.fth latency timer setting for North/South Module +; + : startup ( -- ) standalone? 0= if exit then
@@ -654,6 +659,8 @@ " probe-" do-drop-in
probe-pci + pci-fixup + show-child install-alarm sound
Modified: cpu/x86/pc/olpc/via/ioinit.fth =================================================================== --- cpu/x86/pc/olpc/via/ioinit.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/ioinit.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -10,6 +10,24 @@ 0833152d 062c config-wl 0833152d 072c config-wl
+\ Cache line size (low byte) / latency timer (high byte) registers +2008 000c config-ww +0008 010c config-ww +0008 020c config-ww +0008 040c config-ww +0008 050c config-ww +0008 060c config-ww +0008 070c config-ww +2000 080c config-ww +2000 780c config-ww +2008 800c config-ww +2008 810c config-ww +2008 820c config-ww +2008 830c config-ww +2010 840c config-ww +0800 8f0c config-ww +0008 a00c config-ww + 0 4 devfunc \ PM_table a0 80 80 mreg \ Enable dynamic power management (coreboot for vx800 uses f0; 70 bits are reserved on vx855) a1 e0 e0 mreg \ Dynamic power management for DRAM @@ -62,7 +80,19 @@ 90 ff ff mreg \ Gate clocks 91 ff ff mreg \ Gate clocks 92 cc cc mreg \ Dynamic buffer control, power down comparators + 95 ff 01 mreg \ Reserved - Phoenix value + a5 ff 00 mreg \ Reserved - Phoenix value a8 20 20 mreg \ Central traffic controller dynamic clock stop + d1 ff 01 mreg \ BIOS scratch - Phoenix value + d2 ff 02 mreg \ BIOS scratch - Phoenix value + d3 ff 03 mreg \ BIOS scratch - Phoenix value + d4 ff 10 mreg \ BIOS scratch - Phoenix value + d8 ff 10 mreg \ BIOS scratch - Phoenix value + e4 ff 2a mreg \ BIOS scratch - Phoenix value + e8 ff 10 mreg \ BIOS scratch - Phoenix value + e9 ff fa mreg \ BIOS scratch - Phoenix value + eb ff 01 mreg \ BIOS scratch - Phoenix value + f6 ff 01 mreg \ Reserved - Phoenix value end-table
\ Bus tuning @@ -72,13 +102,20 @@ 59 0f 02 mreg \ IGFX Promote Timer value 2 5f 0f 06 mreg \ IPI Promote Timer value 6 64 20 00 mreg \ Upstream MSI doesn't flush queued P2C Write Data + 72 ff 09 mreg \ Reserved - Phoenix value 80 0b 08 mreg \ Upstream Request 1T earlier + 81 ff 9a mreg \ Reserved - Phoenix value 83 ff 81 mreg \ P2PW down arb timer timer 8, P2PR down arb timer timer 1 84 7f 28 mreg \ Downstream arbitration Timeout timer for C2P 85 c0 c0 mreg \ Abort P2P cycle to PCI1, CPU to PCI1 cycle blocks next C2P cycle a3 01 01 mreg \ 01 res be like Phx end-table
+ 0 7 devfunc + e5 ff 40 mreg \ Reserved - Phoenix value + e6 ff 29 mreg \ Reserved - Phoenix value + end-table + 0 [if] d# 11 0 devfunc \ USB device 41 18 18 mreg \ Enable backdoor @@ -91,6 +128,7 @@ [then]
d# 12 0 devfunc \ SDIO tuning + 04 10 10 mreg \ Enable Memory Write and Invalidate 44 01 01 mreg \ Enable backdoor 2c ff 2d mreg \ Subsystem ID backdoor 2d ff 15 mreg \ Subsystem ID backdoor @@ -105,6 +143,7 @@ 99 ff f9 mreg \ Two slots [then] [ifdef] xo-board +\ 98 ff 20 mreg \ Set Reserved bit - Phoenix value - No, SD fails to start the clock if this bit is set 99 ff fa mreg \ Three slots [then] end-table @@ -142,6 +181,7 @@
\ USB Tuning d# 16 0 devfunc \ UHCI Ports 0,1 + 04 10 10 mreg \ Enable Memory Write and Invalidate 42 10 10 mreg \ Enable backdoor 2c ff 2d mreg \ Subsystem ID backdoor 2d ff 15 mreg \ Subsystem ID backdoor @@ -154,6 +194,7 @@ end-table
d# 16 1 devfunc \ UHCI Ports 2,3 + 04 10 10 mreg \ Enable Memory Write and Invalidate 42 10 10 mreg \ Enable backdoor 2c ff 2d mreg \ Subsystem ID backdoor 2d ff 15 mreg \ Subsystem ID backdoor @@ -167,6 +208,7 @@
[ifndef] xo-board d# 16 2 devfunc \ UHCI Ports 4,5 + 04 10 10 mreg \ Enable Memory Write and Invalidate 42 10 10 mreg \ Enable backdoor 2c ff 2d mreg \ Subsystem ID backdoor 2d ff 15 mreg \ Subsystem ID backdoor @@ -181,6 +223,7 @@
d# 16 4 devfunc \ EHCI + 04 10 10 mreg \ Enable Memory Write and Invalidate 42 10 10 mreg \ Enable backdoor 2c ff 2d mreg \ Subsystem ID backdoor 2d ff 15 mreg \ Subsystem ID backdoor @@ -191,20 +234,22 @@ 42 40 40 mreg \ Enable Check PRESOF of ITDOUT Transaction during Fetching Data from DRAM 43 c0 c0 mreg \ Enable Dynamic Clock Scheme - 66MHz (80) & 33MHz (40) 48 20 00 mreg \ Disable DMA bursts + 4b 60 60 mreg \ EHCI sleep timeout to match Via settings +\ 4b 60 00 mreg \ Via setting of 60 doesn't work with USB LAN device 4c 03 03 mreg \ Squelch detector fine tune - 01 is 112.5 mV 4d 10 10 mreg \ 10 res be like Phx 4e 03 03 mreg \ reserved bit - setting is appropriate for vx800 03 res be like Phx 4f 10 10 mreg \ Enable Clear RUN Bit when EHCI_IDLE 50 80 80 mreg \ Fetch one more QH before de-asserting Doorbell 52 ff 11 mreg \ be like Phx - 53 ff 3f mreg \ be like Phx + 53 ff bf mreg \ Via settings, different from old Phx 55 ff ff mreg \ Disconnect level fine tune - 575 mV for ports 0-3 56 0f 0f mreg \ Disconnect level fine tune - 575 mV for ports 4-5 5a ff cc mreg \ HS termination resistor fine tune - 45 ohm, 48 ohm for ports 0,1 5b ff cc mreg \ HS termination resistor fine tune - 45 ohm, 48 ohm for ports 2,3 5c 0f 00 mreg \ DPLL Track Speed 2, DPLL Lock Speed 2 5d ff cc mreg \ HS termination resistor fine tune - 45 ohm, 48 ohm for ports 4,5 - 64 05 05 mreg \ Bump NULL-SOF valid time to 8 micro frames (04), Inhibit C4 state on USB 1.1 ISO activity (01) + 64 07 03 mreg \ High bit of NULL-SOF valid time (04=00), HS ISO actitivy (02) and USB 1.1 ISO activity (01) inhibit C4 end-table
[ifdef] xo-board @@ -217,6 +262,7 @@ [then]
d# 17 0 devfunc \ Bus control and power management + 04 40 40 mreg \ Check parity 40 44 44 mreg \ Enable I/O Recovery time (40), Enable ports 4d0/4d1 for edge/level setting (04) [ifdef] xo-board 41 40 40 mreg \ Enable fff0.0000-fff7.ffff ROM on LPC bus @@ -230,7 +276,8 @@ 50 40 40 mreg \ Disable USB device mode [then] [ifdef] xo-board - 50 4c 4c mreg \ Disable USB device mode, unused USB 1.1 ports 4,5, and EIDE device +\ 50 4c 4c mreg \ Disable USB device mode, unused USB 1.1 ports 4,5, and EIDE device + 50 cc cc mreg \ Disable USB device mode, unused USB 1.1 ports 4,5, and EIDE device (set rsvd 80 bit to Phoenix value) 51 9f 88 mreg \ Enable SDIO and internal RTC, disable card reader, int mouse & kbd [then]
@@ -315,7 +362,7 @@
b0 08 00 mreg \ The BIOS Porting Note says to clear this bit. Phoenix and coreboot agree. b4 80 00 mreg \ No positive decoding for UART1 ??? - b7 40 40 mreg \ 40 res be like Phx +\ b7 40 40 mreg \ 40 res be like Phx (Phoenix now uses 00) uart-dma-io-base wbsplit swap ( bits15:8 bits7:0 ) b8 fc rot mreg \ UART DMA Control Registers Base low (port is 4080) b9 ff rot mreg \ UART DMA Control Registers Base high @@ -330,7 +377,8 @@ d0 f0 rot mreg \ SMBUS IO Base Address low (port is 0500) d1 ff rot mreg \ SMBUS IO Base Address high d2 0f 01 mreg \ Enable SMBUS and set other characteristics - e2 80 80 mreg \ Inhibit C4 during USB isochronous transaction +\ e2 80 80 mreg \ Inhibit C4 during USB isochronous transaction + e2 ff e9 mreg \ Inhibit C4 during USB isochronous transaction, other bits reserved - Phoenix value [ifdef] demo-board e4 ff a0 mreg \ Enable short C3/C4 (80), select various multi-function pins [then] @@ -350,6 +398,7 @@ end-table
d# 17 7 devfunc \ South-North Module Interface Control + 4e ff 80 mreg \ Reserved - Phoenix value 50 df 08 mreg \ SM priorities - HDAC high priority, others low 51 80 80 mreg \ Enable subtractive decode for P2P cycle 54 7b 02 mreg \ CCA REQ timing - synchronize USB REQ but not others @@ -372,17 +421,27 @@ 80 07 07 mreg \ PCI1 and HDAC upstream read does not pass write, APCI blocks upstream write \ 82 3e 20 mreg \ Monitor CCA and SDIO2 82 3f 21 mreg \ Monitor CCA and SDIO2 - 01 res be like Phx + 88 ff 02 mreg \ Reserved - Phoenix value \ e0 e0 80 mreg \ Dynamic CCA clock e0 f3 93 mreg \ Dynamic CCA clock - 13 res be like Phx + e1 ff 08 mreg \ Reserved - Phoenix value \ e2 1e 00 mreg \ Use dynamic clocks for Downstream Interface, PCI1, Downstream HDAC, Downstream SM Internal PCI device e2 1f 00 mreg \ Use dynamic clocks for Downstream Interface, PCI1, Downstream HDAC, Downstream SM Internal PCI device 01 res be like Phx e3 ff 5e mreg \ PCI1 dynamic clock, PCI clock on when GRANT# asserted, Enable P2CR data timeout at 7*8 PCI clocks \ e6 1f 1f mreg \ Split APIC decoding, Snoop FEEx.xxxx, Enable top SMM, High SMM, Compat SMM (20 bit is reserved) - e6 1f 19 mreg \ Split APIC decoding, Snoop FEEx.xxxx, Enable top SMM, High SMM, Compat SMM (20 bit is reserved) + e6 3f 39 mreg \ Split APIC decoding, Snoop FEEx.xxxx, Enable top SMM, High SMM, Compat SMM (20 bit is reserved) \ fc 40 40 mreg \ Enable CCA Read Clock When MTXCTL state machine is not idle fc 48 48 mreg \ Enable CCA Read Clock When MTXCTL state machine is not idle - 08 res be like Phx end-table
+ d# 19 0 devfunc \ P2P Bridge + 04 ff 07 mreg \ Mem, IO, Bus Master Enable + 05 ff 01 mreg \ SERR# enable + 19 ff 01 mreg \ Secondary bus number + 1a ff 01 mreg \ Subordinate bus number + 3e ff 04 mreg \ ISA Enable + end-table + d# 20 0 devfunc 41 01 01 mreg \ Dynamic clock for HDAC 40 01 01 mreg \ Enable backdoor
Modified: cpu/x86/pc/olpc/via/pcinode.fth =================================================================== --- cpu/x86/pc/olpc/via/pcinode.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/pcinode.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -1,6 +1,8 @@ \ See license at end of file purpose: PCI bus package
+d# 33,333,333 " clock-frequency" integer-property + : preassigned-pci-slot? ( my-space -- flag ) h# f.f800 and dup h# 800 = if drop true exit then @@ -115,6 +117,7 @@ \ Wouldn't it be nice if you could get the argument to pirq@ from \ the interrupt pin register (offset 3d)? But that doesn't work, \ because some devices say pin A but use PIRQB. + h# 0800 of d# 10 set-level-trigger true exit endof \ Display h# 5800 of 1 pirq@ set-level-trigger true exit endof \ USB device - PIRQB h# 6000 of 0 pirq@ set-level-trigger true exit endof \ SDIO - PIRQA h# 6800 of 0 pirq@ set-level-trigger true exit endof \ SDC - PIRQA
Modified: cpu/x86/pc/olpc/via/romreset.bth =================================================================== --- cpu/x86/pc/olpc/via/romreset.bth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/romreset.bth 2009-11-06 07:34:27 UTC (rev 1460) @@ -116,16 +116,21 @@ \ This is a device ID backdoor to fake out the ID so Ubuntu will install \ 8879 config-rb h# 40 # al or al dx out \ I don't know what this is, but coreboot does it
- fload ${BP}/cpu/x86/pc/olpc/via/starthostctl.fth - acpi-io-base 1 + 8888 config-ww \ Set ACPI base address acpi-io-base wbsplit 0292 config-wb 0293 config-wb \ ACPI base address for C-states, big-endian
[ifdef] debug-startup cominit #) call [then] + char + report
- char + report + fload ${BP}/cpu/x86/pc/olpc/via/starthostctl.fth + +[ifdef] debug-startup +\ cominit #) call +[then] + +\ char + report long-offsets on
acpi-io-base 4 + port-rw \ Get APCI Status register @@ -144,8 +149,10 @@ \ This must be done in both the power-up and resume-from-S3 cases, \ since the registers in D17F7 lose state during S3.
- 0385 config-rb ax bx mov 8fe5 config-setup bx ax mov al dx out \ Copy Low Top from reg 85 to SB Low Top e5 - 0385 config-rb ax bx mov 8f60 config-setup bx ax mov al dx out \ Copy Low Top from reg 85 to SB Bank 7 end 60 + 80 8fe5 config-wb \ Phoenix value + 80 8f60 config-wb \ Phoenix value +\ 0385 config-rb ax bx mov 8fe5 config-setup bx ax mov al dx out \ Copy Low Top from reg 85 to SB Low Top e5 +\ 0385 config-rb ax bx mov 8f60 config-setup bx ax mov al dx out \ Copy Low Top from reg 85 to SB Bank 7 end 60
\ d# 17 7 devfunc \ e6 ff 07 mreg \ Enable Top, High, and Compatible SMM @@ -251,7 +258,7 @@ char o report h# 1e port80
-\ fload ${BP}/cpu/x86/pc/olpc/via/startgtlinit.fth + fload ${BP}/cpu/x86/pc/olpc/via/startgtlinit.fth
\ Enable the keyboard controller
Modified: cpu/x86/pc/olpc/via/startcominit.fth =================================================================== --- cpu/x86/pc/olpc/via/startcominit.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/startcominit.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -34,7 +34,8 @@ d# 17 0 devfunc 40 44 44 mreg \ Enable I/O Recovery time (40), Enable ports 4d0/4d1 for edge/level setting (04) 43 0f 0b mreg \ Enable PCI delayed transactions (08), Write transaction timer (02), Read transaction timer (01) - 4c c0 40 mreg \ Set I/O recovery time to 2 bus clocks +\ 4c c0 40 mreg \ Set I/O recovery time to 2 bus clocks + 4c c0 00 mreg \ Set I/O recovery time to 1 bus clock 59 ff 1c mreg \ Keyboard (ports 60,64) and ports 62,66 on LPC bus (EC) 5c ff 68 mreg \ High byte (68) of PCS0 5d ff 00 mreg \ High byte (00) of PCS0
Modified: cpu/x86/pc/olpc/via/startgfxinit.fth =================================================================== --- cpu/x86/pc/olpc/via/startgfxinit.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/startgfxinit.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -33,7 +33,8 @@ end-table
1 0 devfunc - b0 07 03 mreg \ VGA memory selection (coreboot uses 03, Phoenix 01. I think 03 is correct) +\ b0 07 03 mreg \ VGA memory selection (coreboot uses 03, Phoenix 01. I think 03 is correct) + b0 07 01 mreg \ VGA memory selection (coreboot uses 03, Phoenix 01. I think 03 is correct) end-table
01 3c3 port-wb \ Graphics chip IO port access on @@ -44,8 +45,13 @@ 68 3c4 port-wb ( size ) 3c5 port-wb \ Size of System Local Frame Buffer - Value depends on frame buffer size \ 00:512MB 80:256MB c0:128MB e0:64MB f0:32MB f8:16MB fc:8MB fe:4MB ff:2MB
- \ These 2 are scratch registers that communicate with the VGA BIOS - 3d 3d4 port-wb 74 3d5 port-wb \ Value depends on DIMM frequency - used by VGA BIOS + \ These are scratch registers that communicate from the VGA BIOS to the OS driver + 3b 3d4 port-wb 02 3d5 port-wb \ TV standard + 3c 3d4 port-wb 08 3d5 port-wb \ Don't know what this is + 3d 3d4 port-wb 64 3d5 port-wb \ Value depends on DIMM frequency - 6 in high nibble is DDR-400 + 3e 3d4 port-wb 20 3d5 port-wb \ Active device + 3f 3d4 port-wb 0b 3d5 port-wb \ Panel size + 39 3c4 port-wb /fbmem d# 22 rshift 3c5 port-wb \ BIOS Reserved Register 0 - FBsize_MiB/4 - VGA BIOS
5a 3c4 port-wb 01 3c5 port-wb \ Point to secondary registers
Modified: cpu/x86/pc/olpc/via/startgtlinit.fth =================================================================== --- cpu/x86/pc/olpc/via/startgtlinit.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/startgtlinit.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -1,5 +1,9 @@ \ After-the-fact tweaks to ROMSIP values 0 2 devfunc + c0 ff 75 mreg + c5 ff 20 mreg + c8 ff 04 mreg +0 [if] 70 ff 55 mreg 71 ff aa mreg 72 ff 66 mreg @@ -56,4 +60,5 @@ c9 00 00 mreg ca b7 10 mreg cb b7 04 mreg +[then] end-table
Modified: cpu/x86/pc/olpc/via/starthostctl.fth =================================================================== --- cpu/x86/pc/olpc/via/starthostctl.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/starthostctl.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -1,7 +1,7 @@ \ enable_mainboard_devices() \ 41 8f4f config-wb \ Enable P2P Bridge Header for External PCI Bus (coreboot value) -\ 43 8f4f config-wb \ As above, plus support extended PCIe config space - 1 8f4f config-wb \ Disable P2P bridge + 43 8f4f config-wb \ As above, plus support extended PCIe config space +\ 1 8f4f config-wb \ Disable P2P bridge
\ 4f6 config-rb \ Get Northbridge revision ... don't need it because the \ init table contains no revision-specific entries @@ -11,7 +11,8 @@ \ Enable extended config space for PCIe 0 5 devfunc \ NB_APIC 61 ff 0e mreg \ Set Exxxxxxx as PCIe MMIO config range - 60 f4 13 mreg \ Support extended cfg address of PCIe (preserve 28 bits) (coreboot used vx800 bit resv in vx855) +\ 60 f4 13 mreg \ Support extended cfg address of PCIe (preserve 28 bits) (coreboot used vx800 bit resv in vx855) + 60 fc 13 mreg \ Support extended cfg address of PCIe (preserve 28 bits) (coreboot used vx800 bit resv in vx855), Phoenix value end-table
0 2 devfunc \ HOST CPU CTL @@ -23,7 +24,7 @@ 53 ff 44 mreg \ Arbitration: Host/Master Occupancy timer = 4*4 HCLK 54 1e 1c mreg \ Misc Ctrl: Enable 8QW burst Mem Access
- 55 06 04 mreg \ Miscellaneous Control 2 + 55 06 04 mreg \ Miscellaneous Control 2 - Several T faster read cycle 56 f7 63 mreg \ Write Policy 1 57 01 01 mreg \ Enable fast TRDY by detecting HREQa[5]# de-assertion 5d ff a2 mreg \ Write Policy @@ -55,6 +56,7 @@ 51 80 80 mreg \ Last step - enable DRDY timing [then] [ifdef] xo-board +.( HELLO) cr 60 ff 2a mreg \ DRDY Timing Control 1 for Read Line 61 ff 00 mreg \ DRDY Timing Control 2 for Read Line 62 ff 00 mreg \ Reserved, probably channel B