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[commit] r3093 - in cpu/arm/olpc: . 1.75 cl4
by repository service 30 Jul '12

30 Jul '12

Author: pgf Date: Mon Jul 30 09:12:55 2012 New Revision: 3093 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3093 Log: config ec-flags-offset on a per laptop basis Modified: cpu/arm/olpc/1.75/config.fth cpu/arm/olpc/cl4/config.fth cpu/arm/olpc/edi.fth Modified: cpu/arm/olpc/1.75/config.fth ============================================================================== --- cpu/arm/olpc/1.75/config.fth Mon Jul 30 09:12:43 2012 (r3092) +++ cpu/arm/olpc/1.75/config.fth Mon Jul 30 09:12:55 2012 (r3093) @@ -29,7 +29,8 @@ d# 9999 constant machine-type \ Backwards compatibility with non-device-tree kernel char 4 constant expected-ec-version -h# 8000 value /ec-flash +h# 8000 constant /ec-flash +h# 7e80 constant ec-flags-offset \ don't program or verify this page \ These constants are correct for XO-1.75 and XO-CL4; they might \ need to be changed for different hardware. See setup-gpios-hack Modified: cpu/arm/olpc/cl4/config.fth ============================================================================== --- cpu/arm/olpc/cl4/config.fth Mon Jul 30 09:12:43 2012 (r3092) +++ cpu/arm/olpc/cl4/config.fth Mon Jul 30 09:12:55 2012 (r3093) @@ -25,7 +25,8 @@ d# 10001 constant machine-type \ Backwards compatibility with non-device-tree kernel char 5 constant expected-ec-version -h# 10000 value /ec-flash +h# ec00 constant /ec-flash +h# eb80 constant ec-flags-offset \ don't program or verify this page fload ${BP}/cpu/arm/mmp3/soc-config.fth Modified: cpu/arm/olpc/edi.fth ============================================================================== --- cpu/arm/olpc/edi.fth Mon Jul 30 09:12:43 2012 (r3092) +++ cpu/arm/olpc/edi.fth Mon Jul 30 09:12:55 2012 (r3093) @@ -191,7 +191,7 @@ h# 70 flash-cmd ( ) \ Program page command wait-flash-busy ( ) ; -h# 7e80 constant ec-flags-offset + : edi-program-flash ( adr len offset -- ) cr ( adr len offset ) swap 0 ?do ( adr offset )

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[commit] r3092 - cpu/arm/olpc
by repository service 30 Jul '12

30 Jul '12

Author: pgf Date: Mon Jul 30 09:12:43 2012 New Revision: 3092 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3092 Log: fixes for kb9010 edi programming Modified: cpu/arm/olpc/edi.fth Modified: cpu/arm/olpc/edi.fth ============================================================================== --- cpu/arm/olpc/edi.fth Mon Jul 30 09:12:40 2012 (r3091) +++ cpu/arm/olpc/edi.fth Mon Jul 30 09:12:43 2012 (r3092) @@ -16,10 +16,10 @@ 0 value edi-chip-id : kb9010? ( -- flag ) edi-chip-id 4 = ; -: efcfg ( -- reg# ) kb9010? if h# fea0 else h# fead then ; -: efcmd ( -- reg# ) kb9010? if h# fea7 else h# feac then ; -: efdat ( -- reg# ) kb9010? if h# feaa else h# feab then ; -: rst8051 ( -- reg# ) kb9010? if h# f010 else h# ff14 then ; +: efcfg ( -- reg# ) kb9010? if h# fead else h# fea0 then ; +: efcmd ( -- reg# ) kb9010? if h# feac else h# fea7 then ; +: efdat ( -- reg# ) kb9010? if h# feab else h# feaa then ; +: rst8051 ( -- reg# ) kb9010? if h# ff14 else h# f010 then ; \ Issues with .py code \ A14:A8 should be A15:A8 several places @@ -124,7 +124,7 @@ ; : edi-read-id ( -- id ) - spi-cs-on h# 3e spi-out 0 spi-out spi-in spi-cs-off + spi-cs-on h# 3e spi-out spi-in spi-cs-off ; : probe-rdid ( -- found? ) \ Verify that the EC is the one we think it is

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[commit] r3091 - cpu/arm/olpc/cl4
by repository service 30 Jul '12

30 Jul '12

Author: wmb Date: Mon Jul 30 09:12:40 2012 New Revision: 3091 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3091 Log: OLPC CL4 - Working version of TIM header. Modified: cpu/arm/olpc/cl4/olpc.bth Modified: cpu/arm/olpc/cl4/olpc.bth ============================================================================== --- cpu/arm/olpc/cl4/olpc.bth Mon Jul 30 09:11:20 2012 (r3090) +++ cpu/arm/olpc/cl4/olpc.bth Mon Jul 30 09:12:40 2012 (r3091) @@ -41,20 +41,18 @@ fload ${BP}/cpu/arm/marvell/tim.fth -\ Marvel Trusted Image Module image creation script for -\ XO-CL4 platform. +\ Marvell Non-Trusted Image Module image creation script for XO-CL4 platform. -tim: 00030400 0 OLPC PXA212x -flash: SPI'10 -timh: TIMH 0 d101f000 -\ Main Processor code loaded into DRAM -image: OBMI 800 d101c000 ${BP}/cpu/arm/olpc/dummy.img -\ Secure Processor code loaded into SRAM -image: WTMI 1000 d1018000 shim.img -image: CFTH 2000 d1000000 cforth.img -reserved: - term: -end-reserved +tim: 00030400 0 THS'01 PXA212x + flash: SPI'10 + timh: TIMH 0 d101f000 + image: OBMI 2000 d1000000 cforth.img + reserved: + \ Disable USB download/init by enabling the FFUART for download + \ This works around a PHY init erratum for the B0 chip + uart: 00004646 1 + term: + end-reserved end-tim h# 20.0000 to reserved-start

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[commit] r3090 - cpu/arm/marvell
by repository service 30 Jul '12

30 Jul '12

Author: wmb Date: Mon Jul 30 09:11:20 2012 New Revision: 3090 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3090 Log: OLPC ARM - Marvell TIM compiler enhancements for version 4 of the TIM header. Modified: cpu/arm/marvell/tim.fth Modified: cpu/arm/marvell/tim.fth ============================================================================== --- cpu/arm/marvell/tim.fth Mon Jul 30 09:08:16 2012 (r3089) +++ cpu/arm/marvell/tim.fth Mon Jul 30 09:11:20 2012 (r3090) @@ -1,11 +1,17 @@ : >hex ( n -- n' ) d# 10 /mod h# 10 * + ; + +0 value tim-version +: tim-v3? ( -- flag ) tim-version h# 00ffff00 and h# 00030400 = ; + : today>hex ( -- n ) today ( day month year ) d# 100 /mod ( day month yr century ) rot >hex >r ( day yr century r: hex-month ) rot >hex >r ( yr century r: hex-month hex-day ) >hex >r ( yr r: hex-month hex-day hex-century ) - >hex r> r> r> bljoin ( n ) + >hex r> r> r> + tim-v3? if 2swap then + bljoin ( n ) ; 0 value image-size @@ -71,26 +77,29 @@ ofd @ fclose image-adr image-size free-mem ; +: id, ( -- ) + get-word ( adr len ) + \ Convert trailing number to binary byte value - e.g. NAN'6 -> NAN(06) + 2dup [char] ' left-parse-string 2drop ( adr len tail$ ) + push-decimal $number pop-base abort" Bad number" ( adr len n ) + nip over 3 + c! 4 ( adr 4 ) + 4c, +; : tim: \ version trusted ID Processor 0 to last-image-adr here to tim-adr - hex, + get-hex dup l, to tim-version " TIMH" 4c, hex, \ Trusted \ hex, \ Date today>hex l, - get-word -4c, \ OEM ID + id, \ OEM ID get-word 2drop \ Processor ; : flash: \ id (e.g. NAN6) 5 0 do -1 l, loop - get-word ( adr len ) - \ Convert trailing number to binary byte value - e.g. NAN'6 -> NAN(06) - 2dup [char] ' left-parse-string 2drop ( adr len tail$ ) - push-decimal $number pop-base abort" Bad number" ( adr len n ) - nip over 3 + c! 4 ( adr 4 ) - 4c, + id, here to #images-adr 0 l, here to #keys-adr 0 l, @@ -112,12 +121,18 @@ ifd @ fgets ( size read-size ) over <> abort" Read failed" ( size ) ifd @ fclose ( size ) -\ h# 1000 round-up - h# 800 round-up -\ 4 round-up + \ Older BOOTROMs seem to want the size to be strongly aligned + tim-v3? if 4 else h# 800 then round-up ( size' ) ; : place-hash \ XXX need to implement non-null hash info - d# 10 0 do 0 l, loop + tim-v3? if + 0 l, \ Size to hash (should be -1 but 0 is in the examples) + d# 20 l, \ HashAlgorithmID - SHA-160 + d# 16 0 do 0 l, loop \ Hash + 0 l, \ Partition number + else + d# 10 0 do 0 l, loop \ Hash + then ; : +#images ( -- ) #images-adr l@ 1+ #images-adr l! ; : start-image ( adr len -- ) @@ -168,6 +183,8 @@ my-timh-adr if here tim-adr - my-timh-adr 4 la+ l! tim-adr image-adr my-timh-adr 2 la+ l@ + here tim-adr - move + else + tim-adr image-adr here tim-adr - move then ; : tbrx: \ xferloc @@ -198,4 +215,16 @@ : cmcc: \ " CMCC" start-package ; +: usb: \ Port# Enabled? + " "(00)USB" start-package hex, hex, end-package +; +: uart: \ Port# Enabled? + " "UART" start-package hex, hex, end-package +; +: cmon: \ + " CMON" start-package end-package +; +: core: \ number mapping + " CORE" start-package hex, hex, end-package +; : term: " Term" start-package end-package ;

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[commit] r3089 - in cpu/arm/olpc: . 1.75 3.0 cl4
by repository service 30 Jul '12

30 Jul '12

Author: wmb Date: Mon Jul 30 09:08:16 2012 New Revision: 3089 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3089 Log: OLPC CL4 - Changed names of EDI GPIO pins to match new naming schema. Modified: cpu/arm/olpc/1.75/gpiopins.fth cpu/arm/olpc/3.0/gpiopins.fth cpu/arm/olpc/bbedi.fth cpu/arm/olpc/cl4/gpiopins.fth Modified: cpu/arm/olpc/1.75/gpiopins.fth ============================================================================== --- cpu/arm/olpc/1.75/gpiopins.fth Mon Jul 30 01:16:14 2012 (r3088) +++ cpu/arm/olpc/1.75/gpiopins.fth Mon Jul 30 09:08:16 2012 (r3089) @@ -30,6 +30,7 @@ d# 53 constant rtc-scl-gpio# d# 54 constant rtc-sda-gpio# +d# 103 constant ec-edi-miso-gpio# d# 104 constant ec-edi-cs-gpio# d# 105 constant ec-edi-mosi-gpio# d# 106 constant ec-edi-clk-gpio# Modified: cpu/arm/olpc/3.0/gpiopins.fth ============================================================================== --- cpu/arm/olpc/3.0/gpiopins.fth Mon Jul 30 01:16:14 2012 (r3088) +++ cpu/arm/olpc/3.0/gpiopins.fth Mon Jul 30 09:08:16 2012 (r3089) @@ -27,6 +27,7 @@ d# 53 constant rtc-scl-gpio# d# 54 constant rtc-sda-gpio# +d# 103 constant ec-edi-miso-gpio# d# 104 constant ec-edi-cs-gpio# d# 105 constant ec-edi-mosi-gpio# d# 106 constant ec-edi-clk-gpio# Modified: cpu/arm/olpc/bbedi.fth ============================================================================== --- cpu/arm/olpc/bbedi.fth Mon Jul 30 01:16:14 2012 (r3088) +++ cpu/arm/olpc/bbedi.fth Mon Jul 30 09:08:16 2012 (r3089) @@ -1,16 +1,11 @@ \ See license at end of file purpose: Bit-banged SPI bus driver for KB3731 EC "EDI" interface -d# 103 constant edi-miso-gpio# -d# 104 constant edi-cs-gpio# -d# 105 constant edi-mosi-gpio# -d# 106 constant edi-clk-gpio# +: edi-cs-on ( -- ) ec-edi-cs-gpio# gpio-clr ; +: edi-cs-off ( -- ) ec-edi-cs-gpio# gpio-set ; -: edi-cs-on ( -- ) edi-cs-gpio# gpio-clr ; -: edi-cs-off ( -- ) edi-cs-gpio# gpio-set ; - -: edi-clk-lo ( -- ) edi-clk-gpio# gpio-clr ; -: edi-clk-hi ( -- ) edi-clk-gpio# gpio-set ; +: edi-clk-lo ( -- ) ec-edi-clk-gpio# gpio-clr ; +: edi-clk-hi ( -- ) ec-edi-clk-gpio# gpio-set ; 0 [if] \ All this timing stuff is pointless because the GPIOs are so slow @@ -60,7 +55,7 @@ [ifndef] edi-bit! : edi-bit! ( flag -- ) - edi-mosi-gpio# swap if gpio-set else gpio-clr then + ec-edi-mosi-gpio# swap if gpio-set else gpio-clr then edi-clk-hi edi-dly edi-clk-lo @@ -71,13 +66,13 @@ [ifndef] edi-bit! : edi-bit! ( flag -- ) if - [ edi-mosi-gpio# >gpio-pin h# 18 + ] dliteral io! \ Fast gpio-set + [ ec-edi-mosi-gpio# >gpio-pin h# 18 + ] dliteral io! \ Fast gpio-set else - [ edi-mosi-gpio# >gpio-pin h# 24 + ] dliteral io! \ Fast gpio-clr + [ ec-edi-mosi-gpio# >gpio-pin h# 24 + ] dliteral io! \ Fast gpio-clr then - [ edi-clk-gpio# >gpio-pin h# 18 + ] dliteral io! \ Fast gpio-set + [ ec-edi-clk-gpio# >gpio-pin h# 18 + ] dliteral io! \ Fast gpio-set \ edi-dly - [ edi-clk-gpio# >gpio-pin h# 24 + ] dliteral io! \ Fast gpio-set + [ ec-edi-clk-gpio# >gpio-pin h# 24 + ] dliteral io! \ Fast gpio-set \ edi-dly ; [then] @@ -92,7 +87,7 @@ : edi-bit@ ( -- flag ) edi-clk-hi edi-dly - edi-miso-gpio# gpio-pin@ + ec-edi-miso-gpio# gpio-pin@ edi-clk-lo edi-dly ; Modified: cpu/arm/olpc/cl4/gpiopins.fth ============================================================================== --- cpu/arm/olpc/cl4/gpiopins.fth Mon Jul 30 01:16:14 2012 (r3088) +++ cpu/arm/olpc/cl4/gpiopins.fth Mon Jul 30 09:08:16 2012 (r3089) @@ -31,6 +31,7 @@ d# 53 constant rtc-scl-gpio# d# 54 constant rtc-sda-gpio# +d# 103 constant ec-edi-miso-gpio# d# 104 constant ec-edi-cs-gpio# d# 105 constant ec-edi-mosi-gpio# d# 106 constant ec-edi-clk-gpio#

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[commit] r3088 - cpu/arm/mmp2
by repository service 29 Jul '12

29 Jul '12

Author: wmb Date: Mon Jul 30 01:16:14 2012 New Revision: 3088 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3088 Log: OLPC MMP GPIO driver - omit pxa-gpio entry from compatible property. Modified: cpu/arm/mmp2/gpio.fth Modified: cpu/arm/mmp2/gpio.fth ============================================================================== --- cpu/arm/mmp2/gpio.fth Fri Jul 27 04:57:48 2012 (r3087) +++ cpu/arm/mmp2/gpio.fth Mon Jul 30 01:16:14 2012 (r3088) @@ -44,8 +44,7 @@ 0 0 " d4019000" " /" begin-package " gpio" name - " mrvl,mmp-gpio" encode-string - " mrvl,pxa-gpio" encode-string encode+ " compatible" property + " mrvl,mmp-gpio" encode-string +compatible my-address my-space h# 1000 reg

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[commit] r3087 - cpu/arm/olpc
by repository service 27 Jul '12

27 Jul '12

Author: wmb Date: Fri Jul 27 04:57:48 2012 New Revision: 3087 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3087 Log: OLPC ARM - this goes with svn 3084 - moving the UART assignment out to version-specific fw.bth Modified: cpu/arm/olpc/build-fw.fth Modified: cpu/arm/olpc/build-fw.fth ============================================================================== --- cpu/arm/olpc/build-fw.fth Fri Jul 27 04:55:18 2012 (r3086) +++ cpu/arm/olpc/build-fw.fth Fri Jul 27 04:57:48 2012 (r3087) @@ -31,8 +31,6 @@ fload ${BP}/dev/omap/diaguart.fth \ OMAP UART -h# 18000 +io to uart-base \ UART3 base address on MMP2 -\ h# 30000 +io to uart-base \ UART1 base address on MMP2 d# 26000000 to uart-clock-frequency \ CForth has already set up the serial port @@ -105,8 +103,14 @@ fload ${BP}/cpu/arm/mmp2/uart.fth " /apbc" encode-phandle d# 12 encode-int encode+ " clocks" property d# 24 " interrupts" integer-property - 1 " linux,unit#" integer-property end-package + +0 0 " d4017000" " /" begin-package \ UART2 + fload ${BP}/cpu/arm/mmp2/uart.fth + " /apbc" encode-phandle d# 11 encode-int encode+ " clocks" property + d# 28 " interrupts" integer-property +end-package + devalias com1 /uart : com1 " com1" ; ' com1 is fallback-device @@ -115,10 +119,13 @@ fload ${BP}/cpu/arm/mmp2/uart.fth d# 27 " interrupts" integer-property " /apbc" encode-phandle d# 10 encode-int encode+ " clocks" property - 0 " linux,unit#" integer-property end-package -devalias com2 /uart -: com2 " com2" ; + +0 0 " d4016000" " /" begin-package \ UART4 + fload ${BP}/cpu/arm/mmp2/uart.fth + " /apbc" encode-phandle d# 32 encode-int encode+ " clocks" property + d# 46 " interrupts" integer-property +end-package \needs md5init fload ${BP}/ofw/ppp/md5.fth \ MD5 hash @@ -342,7 +349,9 @@ fload ${BP}/cpu/arm/mmp2/thermal.fth fload ${BP}/cpu/arm/mmp2/fuse.fth +[ifdef] bsl-uart-base fload ${BP}/cpu/arm/olpc/bsl.fth +[then] [ifndef] virtual-mode warning off

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[commit] r3086 - dev/olpc/spiflash
by repository service 27 Jul '12

27 Jul '12

Author: wmb Date: Fri Jul 27 04:55:18 2012 New Revision: 3086 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3086 Log: OLPC SPIFLASH driver - handle 2 MB parts. Modified: dev/olpc/spiflash/spiflash.fth Modified: dev/olpc/spiflash/spiflash.fth ============================================================================== --- dev/olpc/spiflash/spiflash.fth Fri Jul 27 04:54:42 2012 (r3085) +++ dev/olpc/spiflash/spiflash.fth Fri Jul 27 04:55:18 2012 (r3086) @@ -199,6 +199,8 @@ 3drop ; +: null-write ( adr len offset -- ) 3drop ; + \ This version is for SST parts, which use an auto-increment \ address command for fast writing. The SST part does not \ require you to stop at 256-byte page boundaries. The @@ -306,12 +308,16 @@ h# 13 of ['] common-write endof h# 34 of ['] common-write endof h# bf of ['] sst-write endof - h# 14 of - ." The SPI FLASH ID reads as 14. This is due to an infrequent hardware problem." cr - ." If you power cycle and try again, it will probably work the next time." cr - abort - endof - ( default ) true abort" Unsupported SPI FLASH ID" + h# 14 of ['] common-write endof +\ On some old board the ID would read as 14 when it should have been something else. +\ On CL4, 14 is the expected ID. +\ ." The SPI FLASH ID reads as 14. This is due to an infrequent hardware problem." cr +\ ." If you power cycle and try again, it will probably work the next time." cr +\ abort +\ endof + +\ ( default ) true abort" Unsupported SPI FLASH ID" + ( default ) ." Bad SPI FLASH ID " dup . cr ['] null-write swap endcase to write-spi-flash spi-unprotect @@ -326,6 +332,7 @@ else spi-id# case h# 13 of ." type 13 - Spansion, Winbond, or ST" endof + h# 14 of ." type 14 - 2 MB" endof h# 34 of ." type 34 - Macronyx" endof endcase then

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[commit] r3085 - cpu/arm/olpc
by repository service 27 Jul '12

27 Jul '12

Author: wmb Date: Fri Jul 27 04:54:42 2012 New Revision: 3085 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3085 Log: OLPC EDI driver - handle differences between KB3731 and the new KB9010 Modified: cpu/arm/olpc/edi.fth Modified: cpu/arm/olpc/edi.fth ============================================================================== --- cpu/arm/olpc/edi.fth Fri Jul 27 04:49:02 2012 (r3084) +++ cpu/arm/olpc/edi.fth Fri Jul 27 04:54:42 2012 (r3085) @@ -13,6 +13,41 @@ \ spi-out ( byte -- ) - Send byte \ spi-in ( -- byte ) - Receive byte +0 value edi-chip-id +: kb9010? ( -- flag ) edi-chip-id 4 = ; + +: efcfg ( -- reg# ) kb9010? if h# fea0 else h# fead then ; +: efcmd ( -- reg# ) kb9010? if h# fea7 else h# feac then ; +: efdat ( -- reg# ) kb9010? if h# feaa else h# feab then ; +: rst8051 ( -- reg# ) kb9010? if h# f010 else h# ff14 then ; + +\ Issues with .py code +\ A14:A8 should be A15:A8 several places +\ inconsistent use of handle vs gd.handle in edi_erase_chip + +\ KB9010 stuff... +d# 59 d# 1024 * constant /kb9010-flash +h# fe80 constant wdtcfg +h# fe81 constant wdtpf +h# fe82 constant wdt +h# fea2 constant shccfg +\ h# fea5 constant xbicfg \ Unused +h# fea6 constant xbics +\ h# feae constant efdatr \ Unused +\ h# feaf constant emfburw +h# feb2 constant xbiwp +\ h# feb6 constant xbipump +\ h# feb7 constant xbifm +\ h# feb8 constant sbivr +h# feb9 constant xbis +h# ff0d constant clkcfg +h# ff0f constant pllcfg +h# ff1d constant ecsts +h# ff1f constant pllcfg2 +h# ff14 constant pxcfg + +\ end KB9010 stuff... + d# 128 constant /flash-page defer edi-progress ' drop to edi-progress ( n -- ) @@ -73,19 +108,25 @@ ; [then] : reset-8051 ( -- ) \ Reset 8-5 - h# f010 edi-b@ 1 or h# f010 edi-b! + rst8051 edi-b@ 1 or rst8051 edi-b! ; : unreset-8051 ( -- ) \ Reset 8-5 - h# f010 edi-b@ 1 invert and h# f010 edi-b! + rst8051 edi-b@ 1 invert and rst8051 edi-b! d# 2000 ms ; \ 0 in bit 0 selects masked ROM as code source for 8051, 1 selects FLASH \ The 8051 should be in reset mode when changing that bit. + : select-flash ( -- ) \ Setup for access to FLASH inside the EC + kb9010? if exit then h# f011 edi-b@ 1 or h# f011 edi-b! ; +: edi-read-id ( -- id ) + spi-cs-on h# 3e spi-out 0 spi-out spi-in spi-cs-off +; + : probe-rdid ( -- found? ) \ Verify that the EC is the one we think it is select-flash h# f01c ['] edi-w@ catch if ( x ) @@ -95,12 +136,15 @@ 1 invert and h# 3730 = ; +: finished? ( b -- flag ) + kb9010? if 2 and 0= else h# 80 = then +; : wait-flash-busy ( -- ) \ Wait for an erase/programming operation to complete get-msecs h# 1000 + ( limit ) begin ( limit ) - h# fea0 edi-b@ ( limit b ) - h# 80 and if ( limit ) - drop exit + efcfg edi-b@ ( limit b ) + finished? if ( limit ) + drop exit ( -- ) then ( limit ) dup get-msecs - 0<= ( limit timeout? ) until ( limit ) @@ -108,11 +152,12 @@ true abort" EDI FLASH busy timeout" ; -: flash-cmd ( b -- ) h# fea7 edi-b! ; +: flash-cmd ( b -- ) efcmd edi-b! ; : set-offset ( offset -- ) - wbsplit ( offset-low offset-hi ) - h# fea9 edi-b! h# fea8 edi-b! ( ) + lbsplit drop ( offset-low mid hi ) + kb9010? if h# feaa edi-b! else drop then ( offset-low mid ) + h# fea9 edi-b! h# fea8 edi-b! ( ) ; : erase-page ( offset -- ) @@ -121,14 +166,19 @@ h# 20 flash-cmd ( ) ; -: erase-chip ( -- ) wait-flash-busy h# 60 flash-cmd wait-flash-busy ; +: erase-chip ( -- ) + 0 set-offset \ New code does this (and does not wait-flash-busy) + wait-flash-busy h# 60 flash-cmd wait-flash-busy +; -: send-byte ( b offset -- ) set-offset h# feaa edi-b! 2 flash-cmd ; +: send-byte ( b offset -- ) set-offset efdat edi-b! 2 flash-cmd ; : edi-program-page ( adr offset -- ) \ Clear HVPL wait-flash-busy h# 80 flash-cmd ( adr offset ) + wait-flash-busy ( adr offset ) \ Necessary? + \ Fill the page buffer swap /flash-page bounds do ( offset ) i c@ over send-byte ( offset ) @@ -138,7 +188,7 @@ \ Commit the buffer to the FLASH memory wait-flash-busy ( ) \ Redundant wait? - h# 70 flash-cmd ( ) + h# 70 flash-cmd ( ) \ Program page command wait-flash-busy ( ) ; h# 7e80 constant ec-flags-offset @@ -162,11 +212,12 @@ edi-next-b@ i c! ( ) loop ( ) ; + : trim@ ( offset -- b ) set-offset h# 90 flash-cmd wait-flash-busy - h# feab edi-b@ + efdat edi-b@ \ reg: efdat ; : trim-tune ( -- ) \ firmware-id 0= if @@ -226,13 +277,76 @@ then \ then ; +: set-chip-id ( -- ) + ['] edi-read-id catch if ( ) + edi-read-id ( id ) + then ( id ) + to edi-chip-id +; +: kb9010-init ( -- ) + h# 00 xbics edi-b! + h# 00 xbiwp edi-b! \ Clear XBI write protection + h# ff wdt edi-b! \ Disable WDT + h# 00 wdtcfg edi-b! + h# 00 wdtpf edi-b! + h# 00 shccfg edi-b! \ Disable SHC + h# 0c clkcfg edi-b! \ Set the 8051 to 32Mhz + h# 08 efcfg edi-b! \ Enable the embedded flash cmd mode +; +base @ hex +create special-row 1f0 w, 1f1 w, 1f2 w, 1f4 w, 1f5 w, 1f6 w, 1f3 w, +create dest-regs feb9 w, feb6 w, feb6 w, feb7 w, feb8 w, feb8 w, feb7 w, +create source-bits 1f c, 0f c, 0f c, 0f c, 07 c, 1f c, 0f c, +create dest-bits 1f c, f0 c, 0f c, 0f c, e0 c, 1f c, f0 c, +create shift-cnt 0 c, 4 c, 0 c, 0 c, 5 c, 0 c, 4 c, +base ! +: kb9010-trimtune ( -- ) + h# 1ff trim@ 0<> if + 7 0 do + special-row i wa+ w@ edi-b@ ( data ) + source-bits i ca+ c@ or ( field ) + shift-cnt i ca+ c@ lshift ( field' ) + dest-regs i wa+ w@ edi-b@ ( field dest ) + dest-bits i ca+ c@ invert and or ( dest' ) + dest-regs i wa+ w@ edi-b! ( ) + loop + wait-flash-busy + then + h# 80 trim@ h# 5a = if + ecsts edi-b@ ( old-ecsts ) + dup 4 or ecsts edi-b! ( old-ecsts ) \ chipid is now pllcfg2 + + xbis edi-b@ h# 3f and ( old-ecsts xbis-bits ) + h# 81 edi-b@ 3 and 6 lshift or ( old-ecsts xbis-value ) + xbis edi-b! ( old-ecsts ) + + h# 82 edi-b@ h# f and 4 lshift ( old-ecsts pll-high ) + h# 83 edi-b@ h# f0 and 4 rshift or ( old-ecsts pll-value ) + pllcfg edi-b! ( old-ecsts ) + + pllcfg2 edi-b@ h# 3f and ( old-ecsts pll2-bits ) + h# 82 edi-b@ h# 30 and 2 lshift or ( old-ecsts pll2-value ) + pllcfg2 edi-b! ( old-ecsts ) + + ecsts edi-b! ( ) + then +; : edi-open ( -- ) \ slow-edi-clock \ Target speed between 1 and 2 MHz spi-start + + set-chip-id + \ The first operation often fails so retry it ['] select-flash catch if select-flash then reset-8051 - trim-tune + + kb9010? if + kb9010-init + kb9010-trimtune + else + trim-tune + then \ fast-edi-clock \ Target speed up to 16 MHz \ reset ;

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[commit] r3084 - in cpu/arm/olpc: . 1.75 3.0 cl4
by repository service 27 Jul '12

27 Jul '12

Author: wmb Date: Fri Jul 27 04:49:02 2012 New Revision: 3084 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3084 Log: OLPC CL4 - handle different UART assignments between CL4 and 1.75. Modified: cpu/arm/olpc/1.75/config.fth cpu/arm/olpc/1.75/fw.bth cpu/arm/olpc/1.75/gpiopins.fth cpu/arm/olpc/3.0/config.fth cpu/arm/olpc/3.0/fw.bth cpu/arm/olpc/bsl.fth cpu/arm/olpc/cl4/fw.bth cpu/arm/olpc/cl4/gpiopins.fth Modified: cpu/arm/olpc/1.75/config.fth ============================================================================== --- cpu/arm/olpc/1.75/config.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/1.75/config.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -31,6 +31,9 @@ char 4 constant expected-ec-version h# 8000 value /ec-flash -h# 10000 constant l2-#sets +\ These constants are correct for XO-1.75 and XO-CL4; they might +\ need to be changed for different hardware. See setup-gpios-hack + +fload ${BP}/cpu/arm/mmp2/soc-config.fth fload ${BP}/cpu/arm/olpc/1.75/gpiopins.fth Modified: cpu/arm/olpc/1.75/fw.bth ============================================================================== --- cpu/arm/olpc/1.75/fw.bth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/1.75/fw.bth Fri Jul 27 04:49:02 2012 (r3084) @@ -7,6 +7,9 @@ " fw.tag" r/w create-file drop tag-file ! +h# 17000 +io constant bsl-uart-base \ UART2 +h# 30 constant bsl-uart-clock-offset \ APBC_UART2_CLK_RST + fload ${BP}/cpu/arm/olpc/build-fw.fth \ The internal SD card shares the host controller circuitry with @@ -20,6 +23,26 @@ fload ${BP}/cpu/arm/olpc/emmc.fth +\ Setup UART configuration +h# d4018000 to uart-base \ UART3 +devalias com1 /uart@d4018000 + +dev /uart@d4030000 \ UART1 + 0 " linux,unit#" integer-property +device-end + +dev /uart@d4017000 \ UART2 + " disabled" " status" string-property +device-end + +dev /uart@d4018000 \ UART3 + 1 " linux,unit#" integer-property +device-end + +dev /uart@d4016000 \ UART4 + " disabled" " status" string-property +device-end + \ Device node for internal microSD dev /sd new-device Modified: cpu/arm/olpc/1.75/gpiopins.fth ============================================================================== --- cpu/arm/olpc/1.75/gpiopins.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/1.75/gpiopins.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -60,3 +60,7 @@ d# 15 constant rotate-gpio# d# 17 constant check-gpio# + +d# 14 constant touch-hd-gpio# +d# 139 constant touch-tck-gpio# +d# 98 constant touch-rst-gpio# Modified: cpu/arm/olpc/3.0/config.fth ============================================================================== --- cpu/arm/olpc/3.0/config.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/3.0/config.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -30,6 +30,8 @@ char 4 constant expected-ec-version h# 8000 value /ec-flash +h# 18000 constant console-uart-base + fload ${BP}/cpu/arm/mmp2/soc-config.fth fload ${BP}/cpu/arm/olpc/3.0/gpiopins.fth Modified: cpu/arm/olpc/3.0/fw.bth ============================================================================== --- cpu/arm/olpc/3.0/fw.bth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/3.0/fw.bth Fri Jul 27 04:49:02 2012 (r3084) @@ -9,6 +9,26 @@ fload ${BP}/cpu/arm/olpc/build-fw.fth +\ Setup UART configuration +h# d4018000 to uart-base \ UART3 +devalias com1 /uart@d4018000 + +dev /uart@d4030000 \ UART1 + 0 " linux,unit#" integer-property +device-end + +dev /uart@d4017000 \ UART2 + " disabled" " status" string-property +device-end + +dev /uart@d4018000 \ UART3 + 1 " linux,unit#" integer-property +device-end + +dev /uart@d4016000 \ UART4 + " disabled" " status" string-property +device-end + fload ${BP}/cpu/arm/olpc/emmc.fth devalias int /sd/disk@3 Modified: cpu/arm/olpc/bsl.fth ============================================================================== --- cpu/arm/olpc/bsl.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/bsl.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -4,20 +4,13 @@ \ devalias bsl /uart@NNNN:9600,8,e,1//bsl-protocol -\ These constants are correct for XO-1.75 and XO-CL4; they might -\ need to be changed for different hardware. See setup-gpios-hack - -h# 17000 +io constant bsl-uart-base \ UART2 - -d# 98 constant bsl-test-gpio# \ GPIO98 is alternate function 0 (the default) -d# 152 constant bsl-rst-gpio# \ SM_BELn, with GPIO152 as alternate function 1 - \ This is platform-dependent : setup-gpios ( -- ) - 3 d# 55 af! 3 d# 56 af! \ Setup pins for UART2 - 0 bsl-test-gpio# af! \ Set to GPIO function - 1 bsl-rst-gpio# af! \ Set to GPIO function (AF0 is SM_BELn for this pin) +\ The pin setup should be done in CForth, but it's complicated by the fact that the touch-enabled CL2 uses GPIO 56 differently from the ordinary one +[ifdef] olpc-cl2 3 d# 55 af! 3 d# 56 af! [then] \ Setup pins for UART2 + 0 touch-tck-gpio# af! \ Set to GPIO function + 1 touch-rst-gpio# af! \ Set to GPIO function (AF0 is SM_BELn for this pin) ; 0 [if] @@ -33,8 +26,8 @@ d# 115 to test-gpio# \ Normally UART3 TXD, but repurposed as a GPIO d# 116 to rst-gpio# \ Normally UART3 RXD, but repurposed as a GPIO - 0 bsl-test-gpio# af! \ Set to GPIO function instead of UART3 - 0 bsl-rst-gpio# af! \ Set to GPIO function instead of UART3 + 0 touch-tck-gpio# af! \ Set to GPIO function instead of UART3 + 0 touch-rst-gpio# af! \ Set to GPIO function instead of UART3 ; [then] @@ -43,8 +36,8 @@ : bsl-baud ( baud-rate -- ) \ 9600,8,e,1 uart-base >r ( baud-rate r: uart-base ) bsl-uart-base to uart-base - h# 13 h# 30 apbc! \ enable the uart2 clocks - h# 40 1 uart! \ uart unit enable + h# 13 bsl-uart-clock-offset apbc! \ enable the uart2 clocks + h# 40 1 uart! \ uart unit enable baud h# 1b 3 uart! ( r: uart-base ) r> to uart-base ( ) ; @@ -63,35 +56,35 @@ : bsl-open ( -- ) setup-gpios - bsl-rst-gpio# gpio-clr - bsl-test-gpio# gpio-clr - bsl-rst-gpio# gpio-dir-out - bsl-test-gpio# gpio-dir-out + touch-rst-gpio# gpio-clr + touch-tck-gpio# gpio-clr + touch-rst-gpio# gpio-dir-out + touch-tck-gpio# gpio-dir-out d# 9600 bsl-baud ; : bsl-close ( -- ) - bsl-rst-gpio# gpio-dir-in - bsl-test-gpio# gpio-dir-in + touch-rst-gpio# gpio-dir-in + touch-tck-gpio# gpio-dir-in ; : msp430-off ( -- ) - bsl-rst-gpio# gpio-clr - bsl-test-gpio# gpio-clr + touch-rst-gpio# gpio-clr + touch-tck-gpio# gpio-clr ; : dly ( -- ) d# 10 ms ; : start-bsl ( -- ) bsl-open d# 250 ms - bsl-test-gpio# gpio-set + touch-tck-gpio# gpio-set dly - bsl-test-gpio# gpio-clr + touch-tck-gpio# gpio-clr dly - bsl-test-gpio# gpio-set + touch-tck-gpio# gpio-set dly - bsl-rst-gpio# gpio-set + touch-rst-gpio# gpio-set dly - bsl-test-gpio# gpio-clr + touch-tck-gpio# gpio-clr ; : flush-bsl Modified: cpu/arm/olpc/cl4/fw.bth ============================================================================== --- cpu/arm/olpc/cl4/fw.bth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/cl4/fw.bth Fri Jul 27 04:49:02 2012 (r3084) @@ -7,8 +7,33 @@ " fw.tag" r/w create-file drop tag-file ! +h# 16000 +io constant bsl-uart-base \ UART4 +h# 88 constant bsl-uart-clock-offset \ APBC_UART4_CLK_RST + fload ${BP}/cpu/arm/olpc/build-fw.fth +true to stand-init-debug? + +\ Setup UART configuration +h# d4017000 to uart-base \ UART2 +devalias com1 /uart@d4017000 + +dev /uart@d4030000 \ UART1 + 0 " linux,unit#" integer-property +device-end + +dev /uart@d4017000 \ UART2 + 1 " linux,unit#" integer-property +device-end + +dev /uart@d4018000 \ UART3 + " disabled" " status" string-property +device-end + +dev /uart@d4016000 \ UART4 + " disabled" " status" string-property \ Used for touchscreen BSL +device-end + dev /sd new-device 4 encode-int " reg" property Modified: cpu/arm/olpc/cl4/gpiopins.fth ============================================================================== --- cpu/arm/olpc/cl4/gpiopins.fth Sun Jul 22 16:48:28 2012 (r3083) +++ cpu/arm/olpc/cl4/gpiopins.fth Fri Jul 27 04:49:02 2012 (r3084) @@ -11,8 +11,8 @@ d# 155 constant ec-spi-cmd-gpio# d# 113 constant ec-spi-ack-gpio# -d# 167 constant dcon-scl-gpio# -d# 168 constant dcon-sda-gpio# +d# 168 constant dcon-scl-gpio# +d# 167 constant dcon-sda-gpio# d# 126 constant dcon-irq-gpio# d# 142 constant dcon-load-gpio#

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