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[commit] r3113 - cpu/arm/olpc/cl4
by repository service 01 Aug '12

01 Aug '12

Author: wmb Date: Wed Aug 1 10:26:59 2012 New Revision: 3113 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3113 Log: OLPC CL4 - Bump minor version number to q6a03 Modified: cpu/arm/olpc/cl4/fw-version.fth Modified: cpu/arm/olpc/cl4/fw-version.fth ============================================================================== --- cpu/arm/olpc/cl4/fw-version.fth Wed Aug 1 10:26:00 2012 (r3112) +++ cpu/arm/olpc/cl4/fw-version.fth Wed Aug 1 10:26:59 2012 (r3113) @@ -1,7 +1,7 @@ \ The overall firmware revision macro: FW_PREFIX Q6 macro: FW_MAJOR A -macro: FW_MINOR 00 +macro: FW_MINOR 03 \ Create a 2-character build/fw-suffix file to personalize your test builds " fw-suffix" $file-exists? [if]

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[commit] r3112 - cpu/arm/olpc
by repository service 01 Aug '12

01 Aug '12

Author: wmb Date: Wed Aug 1 10:26:00 2012 New Revision: 3112 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3112 Log: OLPC CL4 - Use different value for LCD clock divisor because the clock source select field moved. Modified: cpu/arm/olpc/lcd.fth Modified: cpu/arm/olpc/lcd.fth ============================================================================== --- cpu/arm/olpc/lcd.fth Wed Aug 1 10:23:34 2012 (r3111) +++ cpu/arm/olpc/lcd.fth Wed Aug 1 10:26:00 2012 (r3112) @@ -8,7 +8,15 @@ " /pmua" encode-phandle 1 encode-int encode+ " clocks" property d# 41 " interrupts" integer-property +[ifdef] olpc-cl4 +\ This value has the same effect as the value below. The +\ difference is that the SCLK_SOURCE_SELECT field added a +\ low-order bit (bit 29), so the high nibble changed from +\ 2 to 4 even though the field value is still 1. +h# 20001102 value clkdiv \ Display Clock 1 / 2 -> 56.93 MHz +[else] h# 40001102 value clkdiv \ Display Clock 1 / 2 -> 56.93 MHz +[then] h# 00000700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz d# 8 value hsync \ Sync width

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[commit] r3111 - cpu/arm/olpc cpu/arm/olpc/cl4 dev/mmc/sdhci
by repository service 01 Aug '12

01 Aug '12

Author: wmb Date: Wed Aug 1 10:23:34 2012 New Revision: 3111 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3111 Log: OLPC CL4 - Various fixes for SD. eMMC is now working. Modified: cpu/arm/olpc/cl4/fw.bth cpu/arm/olpc/sdhci.fth dev/mmc/sdhci/sdhci.fth Modified: cpu/arm/olpc/cl4/fw.bth ============================================================================== --- cpu/arm/olpc/cl4/fw.bth Wed Aug 1 10:22:27 2012 (r3110) +++ cpu/arm/olpc/cl4/fw.bth Wed Aug 1 10:23:34 2012 (r3111) @@ -36,17 +36,19 @@ dev /sd new-device - 4 encode-int " reg" property + 1 encode-int " reg" property fload ${BP}/dev/mmc/sdhci/sdmmc.fth fload ${BP}/dev/mmc/sdhci/selftest.fth - " internal" " slot-name" string-property + " external" " slot-name" string-property finish-device device-end +devalias ext /sd/disk@1 +\ 2 is WLAN devalias int /sd/disk@3 -devalias ext /sd/disk@2 +devalias emmc /sd/disk@3 +\ Nothing on channel 4 devalias int-sd /sd/disk@5 -devalias emmc /sd/disk@5 stand-init: boot-dev-sel-gpio# gpio-pin@ 0= if Modified: cpu/arm/olpc/sdhci.fth ============================================================================== --- cpu/arm/olpc/sdhci.fth Wed Aug 1 10:22:27 2012 (r3110) +++ cpu/arm/olpc/sdhci.fth Wed Aug 1 10:23:34 2012 (r3111) @@ -17,12 +17,22 @@ \ Slot:power_GPIO - 1:35, 2:34, 3:33 : gpio-power-on ( -- ) sdhci-card-power-on +[ifdef] en-emmc-pwr-gpio# + slot 3 = if en-emmc-pwr-gpio# gpio-clr then +[then] +[ifdef] en-wlan-pwr-gpio# slot 2 = if en-wlan-pwr-gpio# gpio-set then +[then] ; ' gpio-power-on to card-power-on : gpio-power-off ( -- ) +[ifdef] en-emmc-pwr-gpio# + slot 3 = if en-emmc-pwr-gpio# gpio-set then +[then] +[ifdef] en-wlan-pwr-gpio# slot 2 = if en-wlan-pwr-gpio# gpio-clr then +[then] sdhci-card-power-off ; ' gpio-power-off to card-power-off Modified: dev/mmc/sdhci/sdhci.fth ============================================================================== --- dev/mmc/sdhci/sdhci.fth Wed Aug 1 10:22:27 2012 (r3110) +++ dev/mmc/sdhci/sdhci.fth Wed Aug 1 10:23:34 2012 (r3111) @@ -760,9 +760,9 @@ \ Ideally, the width selection would be done by using CMD19 to test the bus hc-supports-8-bit? if - mmc-8-bit 8-bit + mmc-8-bit 1 ms 8-bit else - mmc-4-bit 4-bit + mmc-4-bit 1 ms 4-bit then \ Ideally, we should set the speed class/power consumption - but the devices

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[commit] r3110 - cpu/arm/olpc/cl4
by repository service 01 Aug '12

01 Aug '12

Author: wmb Date: Wed Aug 1 10:22:27 2012 New Revision: 3110 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3110 Log: OLPC CL4 - Use 'OLPC' as the NTIM OEM name. Modified: cpu/arm/olpc/cl4/olpc.bth Modified: cpu/arm/olpc/cl4/olpc.bth ============================================================================== --- cpu/arm/olpc/cl4/olpc.bth Wed Aug 1 10:21:55 2012 (r3109) +++ cpu/arm/olpc/cl4/olpc.bth Wed Aug 1 10:22:27 2012 (r3110) @@ -43,7 +43,7 @@ \ Marvell Non-Trusted Image Module image creation script for XO-CL4 platform. -tim: 00030400 0 THS'01 PXA212x +tim: 00030400 0 OLPC PXA212x flash: SPI'10 timh: TIMH 0 d101f000 image: OBMI 2000 d1000000 cforth.img

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[commit] r3109 - cpu/arm/olpc/cl4
by repository service 01 Aug '12

01 Aug '12

Author: wmb Date: Wed Aug 1 10:21:55 2012 New Revision: 3109 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3109 Log: OLPC CL4 - EC version 7_0_1_08 Modified: cpu/arm/olpc/cl4/ec-version.fth Modified: cpu/arm/olpc/cl4/ec-version.fth ============================================================================== --- cpu/arm/olpc/cl4/ec-version.fth Wed Aug 1 06:42:05 2012 (r3108) +++ cpu/arm/olpc/cl4/ec-version.fth Wed Aug 1 10:21:55 2012 (r3109) @@ -1,6 +1,6 @@ \ The EC microcode macro: EC_PLATFORM cl4 -macro: EC_VERSION 6_0_0_00 +macro: EC_VERSION 7_0_1_08 \ Alternate command for getting EC microcode, for testing new versions. \ Temporarily uncomment the line and modify the path as necessary

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[commit] r3108 - cpu/arm/olpc
by repository service 01 Aug '12

01 Aug '12

Author: wmb Date: Wed Aug 1 06:42:05 2012 New Revision: 3108 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3108 Log: OLPC ARM - MMP2/3 SDHCI driver - Support slot 5's address. Modified: cpu/arm/olpc/sdregs.fth Modified: cpu/arm/olpc/sdregs.fth ============================================================================== --- cpu/arm/olpc/sdregs.fth Wed Aug 1 06:39:11 2012 (r3107) +++ cpu/arm/olpc/sdregs.fth Wed Aug 1 06:42:05 2012 (r3108) @@ -8,7 +8,12 @@ : map-regs ( -- ) chip if exit then - slot 1- h# 800 * my-space + /regs " map-in" $call-parent + slot 5 = if + h# d421.7000 + else + slot 1- h# 800 * my-space + + then + /regs " map-in" $call-parent to chip ; : unmap-regs ( -- )

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[commit] r3107 - cpu/arm/marvell
by repository service 01 Aug '12

01 Aug '12

Author: wmb Date: Wed Aug 1 06:39:11 2012 New Revision: 3107 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3107 Log: ## Lines starting with '## ' will be removed from the log message. ## File(s) to commit recursively: ## cpu/arm/marvell/tim.fth Marvell TIM compiler - fixed misleading name. Modified: cpu/arm/marvell/tim.fth Modified: cpu/arm/marvell/tim.fth ============================================================================== --- cpu/arm/marvell/tim.fth Wed Aug 1 06:34:49 2012 (r3106) +++ cpu/arm/marvell/tim.fth Wed Aug 1 06:39:11 2012 (r3107) @@ -1,7 +1,7 @@ : >hex ( n -- n' ) d# 10 /mod h# 10 * + ; 0 value tim-version -: tim-v3? ( -- flag ) tim-version h# 00ffff00 and h# 00030400 = ; +: tim-v4? ( -- flag ) tim-version h# 00ffff00 and h# 00030400 = ; : today>hex ( -- n ) today ( day month year ) @@ -10,7 +10,7 @@ rot >hex >r ( yr century r: hex-month hex-day ) >hex >r ( yr r: hex-month hex-day hex-century ) >hex r> r> r> - tim-v3? if 2swap then + tim-v4? if 2swap then bljoin ( n ) ; @@ -129,10 +129,10 @@ over <> abort" Read failed" ( size ) ifd @ fclose ( size ) \ Older BOOTROMs seem to want the size to be strongly aligned - tim-v3? if 4 else h# 800 then round-up ( size' ) + tim-v4? if 4 else h# 800 then round-up ( size' ) ; : place-hash \ XXX need to implement non-null hash info - tim-v3? if + tim-v4? if 0 l, \ Size to hash (should be -1 but 0 is in the examples) d# 20 l, \ HashAlgorithmID - SHA-160 d# 16 0 do 0 l, loop \ Hash

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[commit] r3106 - cpu/arm/marvell
by repository service 01 Aug '12

01 Aug '12

Author: wmb Date: Wed Aug 1 06:34:49 2012 New Revision: 3106 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3106 Log: Marvell TIM compiler - accept either 4 ASCII or 3 ASCII plus decimal for ID values. Modified: cpu/arm/marvell/tim.fth Modified: cpu/arm/marvell/tim.fth ============================================================================== --- cpu/arm/marvell/tim.fth Wed Aug 1 00:41:17 2012 (r3105) +++ cpu/arm/marvell/tim.fth Wed Aug 1 06:34:49 2012 (r3106) @@ -78,11 +78,18 @@ image-adr image-size free-mem ; : id, ( -- ) - get-word ( adr len ) - \ Convert trailing number to binary byte value - e.g. NAN'6 -> NAN(06) - 2dup [char] ' left-parse-string 2drop ( adr len tail$ ) - push-decimal $number pop-base abort" Bad number" ( adr len n ) - nip over 3 + c! 4 ( adr 4 ) + get-word ( adr len ) + \ The ID can either be a 4 bytes of ASCII, e.g. OLPC, + \ or 3 ASCII plus a decimal number, e.g. SPI'10 + 2dup [char] ' left-parse-string ( adr len tail$ head$ ) + nip 4 = if ( adr len tail$ ) + \ No ' character in string; use verbatim + 2drop + else ( adr len tail$ ) + \ Convert trailing number to binary byte value - e.g. NAN'6 -> NAN(06) + push-decimal $number pop-base abort" Bad number" ( adr len n ) + nip over 3 + c! 4 ( adr 4 ) + then 4c, ; : tim: \ version trusted ID Processor

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[commit] r3105 - in cpu/arm: mmp3 olpc
by repository service 31 Jul '12

31 Jul '12

Author: wmb Date: Wed Aug 1 00:41:17 2012 New Revision: 3105 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3105 Log: OLPC CL4 - fix USB2 PHY init and reinstate USB probing. Modified: cpu/arm/mmp3/usb2phy.fth cpu/arm/olpc/build-fw.fth cpu/arm/olpc/usb.fth Modified: cpu/arm/mmp3/usb2phy.fth ============================================================================== --- cpu/arm/mmp3/usb2phy.fth Tue Jul 31 11:05:47 2012 (r3104) +++ cpu/arm/mmp3/usb2phy.fth Wed Aug 1 00:41:17 2012 (r3105) @@ -3,16 +3,16 @@ : +usb2 ( offset -- offset' ) h# 20.7000 + ; -h# 04 +usb2 constant pll-reg0 -h# 08 +usb2 constant pll-reg1 -h# 10 +usb2 constant tx-reg0 -h# 14 +usb2 constant tx-reg1 -h# 18 +usb2 constant tx-reg2 -h# 20 +usb2 constant rx-reg0 -h# 24 +usb2 constant rx-reg1 -h# 28 +usb2 constant rx-reg2 + h# 04 +usb2 constant pll-reg0 + h# 08 +usb2 constant pll-reg1 + h# 10 +usb2 constant tx-reg0 + h# 14 +usb2 constant tx-reg1 + h# 18 +usb2 constant tx-reg2 + h# 20 +usb2 constant rx-reg0 + h# 24 +usb2 constant rx-reg1 + h# 28 +usb2 constant rx-reg2 \ h# 30 +usb2 constant ana-reg0 -\ h# 34 +usb2 constant ana-reg1 + h# 34 +usb2 constant ana-reg1 \ h# 38 +usb2 constant ana-reg2 \ h# 3c +usb2 constant dig-reg0 \ h# 40 +usb2 constant dig-reg1 @@ -22,9 +22,9 @@ \ h# 50 +usb2 constant test-reg1 \ h# 54 +usb2 constant test-reg2 \ h# 58 +usb2 constant charger-reg0 -\ h# 5c +usb2 constant otg-reg0 + h# 5c +usb2 constant otg-reg0 \ h# 60 +usb2 constant phy-mono -\ h# 64 +usb2 constant resetve-reg0 + h# 64 +usb2 constant reserve-reg0 \ h# 78 +usb2 constant icid-reg0 \ h# 7c +usb2 constant icid-reg1 @@ -38,28 +38,43 @@ : init-usb-phy ( -- ) h# f00 h# 100 +pmua io-clr -\ h# d00 h# 100 +pmua io-set \ Select 26 MHz VCXO clock - h# 200 h# 100 +pmua io-set \ Select crystal +\ h# d00 h# 100 +pmua io-set \ Select 26 MHz VCXO clock + h# 000 h# 100 +pmua io-set \ Select crystal - h# 3fff pll-reg0 io-clr \ REFDIV_MASK_B0 3e00, FBDIV_MASK_B0 01ff - h# 1af0 pll-reg0 io-set \ 0xd << 9 , 0xf0 << 0 +\ h# 3fff pll-reg0 io-clr \ REFDIV_MASK_B0 3e00, FBDIV_MASK_B0 01ff +\ h# 1af0 pll-reg0 io-set \ 0xd << 9 , 0xf0 << 0 +\ h# ca60 is the value to use for a 25 MHz crystal + h# daf0 pll-reg0 io-set \ 0xd << 9 , 0xf0 << 0 - h# 2773 pll-reg1 io-clr \ PU_PLL_MASK 2000, (LOCK_BYPASS) 1000, ICP_MASK 700, KVCO_MASK 70, CALI12_MASK 3 - h# 3333 pll-reg1 io-set \ 1 1 3 3 3 + h# 3000 reserve-reg0 io! \ Program PLLVDD12 per Marvell email - h# 0700 tx-reg0 io-clr \ TX_IMPCAL_VTH_MASK 0700 - h# 0200 tx-reg0 io-set \ 2 +\ h# 2773 pll-reg1 io-clr \ PU_PLL_MASK 2000, (LOCK_BYPASS) 1000, ICP_MASK 700, KVCO_MASK 70, CALI12_MASK 3 +\ h# 3333 pll-reg1 io-set \ 1 1 3 3 3 - h# 037f tx-reg1 io-clr \ TX_VDD12_MASK 300 , TX_AMP_MASK 70, TX_CK60_PHSEL_MASK f - h# 0344 tx-reg1 io-set \ 3 4 4 + h# 1433 pll-reg1 io! + d# 100 ms + h# 3433 pll-reg1 io! - h# 0c00 tx-reg2 io-clr \ TX_DRV_SLEWRATE_MASK c00 - h# 0800 tx-reg2 io-set \ 2 << 10 +\ h# 0700 tx-reg0 io-clr \ TX_IMPCAL_VTH_MASK 0700 +\ h# 0200 tx-reg0 io-set \ 2 + h# 0588 tx-reg0 io! \ 2 - h# 00f0 rx-reg0 io-clr \ RX_SQ_THRESH_MASK 00f0 - h# 00a0 rx-reg0 io-set \ a +\ h# 037f tx-reg1 io-clr \ TX_VDD12_MASK 300 , TX_AMP_MASK 70, TX_CK60_PHSEL_MASK f +\ h# 0344 tx-reg1 io-set \ 3 4 4 + h# 07c4 tx-reg1 io! - h# 0008 rx-reg1 io-set \ 1 << OTG_PU_OTG_SHIFT (3) +\ h# 0c00 tx-reg2 io-clr \ TX_DRV_SLEWRATE_MASK c00 +\ h# 0800 tx-reg2 io-set \ 2 << 10 + h# 0eff tx-reg2 io! + +\ h# 00f0 rx-reg0 io-clr \ RX_SQ_THRESH_MASK 00f0 +\ h# 00a0 rx-reg0 io-set \ a + h# aaa1 rx-reg0 io! + + h# 5000 ana-reg1 io-set \ Power up Analog Port + h# 0008 otg-reg0 io-set \ Power up OTG Port + +\ h# 0008 rx-reg1 io-set \ 1 << OTG_PU_OTG_SHIFT (3) \ Calibrate PHY d# 200 us Modified: cpu/arm/olpc/build-fw.fth ============================================================================== --- cpu/arm/olpc/build-fw.fth Tue Jul 31 11:05:47 2012 (r3104) +++ cpu/arm/olpc/build-fw.fth Wed Aug 1 00:41:17 2012 (r3105) @@ -316,9 +316,6 @@ warning @ warning off : stand-init stand-init -[ifdef] olpc-cl4 -." build-fw.fth: Skipping root node properties" cr exit -[then] root-device model-version$ 2dup model ( name$ ) " OLPC " encode-bytes 2swap encode-string encode+ " banner-name" property @@ -856,11 +853,7 @@ \+ use-screen-kbd ?text-on [ifdef] probe-usb factory-test? if d# 1000 ms then \ Extra USB probe delay in the factory -[ifdef] olpc-cl4 - ." build-fw.fth: not probing usb" cr -[else] probe-usb -[then] report-disk report-keyboard [then] Modified: cpu/arm/olpc/usb.fth ============================================================================== --- cpu/arm/olpc/usb.fth Tue Jul 31 11:05:47 2012 (r3104) +++ cpu/arm/olpc/usb.fth Wed Aug 1 00:41:17 2012 (r3105) @@ -29,9 +29,6 @@ : init-usb ( -- ) h# 9 h# 5c pmua! \ Enable clock to USB block reset-usb-hub -[ifdef] olpc-cl4 - ." olpc/usb.fth: Skipping USB phy init!" cr exit -[then] init-usb-phy ;

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[commit] r3104 - cpu/arm/mmp2
by repository service 31 Jul '12

31 Jul '12

Author: wmb Date: Tue Jul 31 11:05:47 2012 New Revision: 3104 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3104 Log: OLPC ARM - revert the change to the SSP SSP_SSPSP register, as it was ineffective. Leave the cosmetic change to the way the other register offsets were specified, for clarity. Modified: cpu/arm/mmp2/sspspi.fth Modified: cpu/arm/mmp2/sspspi.fth ============================================================================== --- cpu/arm/mmp2/sspspi.fth Tue Jul 31 07:38:25 2012 (r3103) +++ cpu/arm/mmp2/sspspi.fth Tue Jul 31 11:05:47 2012 (r3104) @@ -11,14 +11,12 @@ : ssp-sscr1 ( -- adr ) ssp-base 4 + ; : ssp-sssr ( -- adr ) ssp-base 8 + ; : ssp-ssdr ( -- adr ) ssp-base h# 10 + ; -: ssp-sspsp ( -- adr ) ssp-base h# 2c + ; : ssp-spi-start ( -- ) \ Avoid reinitializing the device after the first time, as that \ seems to cause glitches that confuse the SPI FLASH chip ssp-sscr1 io@ 0= if exit then - h# 01 ssp-sspsp io! h# 07 ssp-sscr0 io! 0 ssp-sscr1 io! h# 87 ssp-sscr0 io!

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