Author: wmb
Date: Wed Oct 24 20:37:38 2012
New Revision: 3380
URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3380
Log:
OLPC XO-1.75 - Script to modify fuse settings so that production 1 GHz MMP2 chips use the same speed code as 1 Ghz engineering sample chips.
Added:
cpu/arm/mmp2/fusepgm.fth
Added: cpu/arm/mmp2/fusepgm.fth
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ cpu/arm/mmp2/fusepgm.fth Wed Oct 24 20:37:38 2012 (r3380)
@@ -0,0 +1,86 @@
+\ Script to change the speed code in 1 GHz production MMP2 chips to
+\ match the old speed code value that was used for 1 GHz engineering
+\ sample MMP2 chips.
+
+0 value fuse-block#
+: fuse-ena! ( n -- ) h# 68 pmua! ;
+: fuse-ena@ ( -- n ) h# 68 pmua@ ;
+
+: ena-fuse-module ( -- )
+ \ Do not touch the enable register if it is already enabled.
+ \ That register also controls the interface between the SP and
+ \ PJ4 processors, which is used for keyboard communication.
+ \ The enabling process resets the device, causing system lockups
+ \ if the keyboard interface is active.
+ fuse-ena@ h# 1b = if exit then
+
+ h# 08 fuse-ena!
+ h# 09 fuse-ena!
+ h# 19 fuse-ena!
+ h# 1b fuse-ena!
+;
+
+: fuse-ctl! ( n -- )
+ fuse-block# d# 18 lshift or h# 292804 io!
+ d# 100 ms
+;
+
+: otp-setup ( -- )
+ ena-fuse-module
+ h# 0002.0000 fuse-ctl! \ HiV
+ h# 0042.0000 fuse-ctl! \ Reset + HiV
+ h# 0002.0000 fuse-ctl! \ HiV
+;
+: otp-teardown ( -- )
+ h# 0200.4000 fuse-ctl! \ ClkDiv + SOFT
+ h# 0240.4000 fuse-ctl! \ ClkDiv + SetRst + SOFT
+ h# 0200.4000 fuse-ctl! \ ClkDiv + SOFT
+;
+
+: pgm-fuses2 ( v7 v6 v5 v4 v3 v2 v1 v0 block# -- )
+ to fuse-block# ( v7 v6 v5 v4 v3 v2 v1 v0 )
+ otp-setup ( v7 v6 v5 v4 v3 v2 v1 v0 )
+ h# 292838 h# 20 bounds do i io! 4 +loop ( )
+
+ h# 0203.4000 fuse-ctl! \ ClkDiv + HiV + Burn + SOFT
+ begin h# 292984 io@ h# 100 and until \ Wait for complete
+ h# 0202.4000 fuse-ctl! \ ClkDiv + HiV + + SOFT
+ h# 0200.4000 fuse-ctl! \ ClkDiv + + SOFT
+ h# 0240.4000 fuse-ctl! \ ClkDiv + SetRst + SOFT
+ h# 0200.4000 fuse-ctl! \ ClkDiv + + SOFT
+
+ otp-teardown
+;
+
+2 value es-speed-1g \ This is the engineering sample speed code for 1 GHz parts
+: fix-speed ( -- )
+ ena-fuse-module
+
+ \ Reprogram only if the divider values are the ones that we
+ \ observe in the first batch of production parts - indicating
+ \ that the SoC is not an engineering sample
+ h# 290c fuse@ h# 90001410 = if
+
+ \ Reprogram only if the SW version field is 0 - a virgin part
+ \ that we have not yet reprogrammed
+ h# 2898 fuse@ 0= if
+
+ \ If the speed code indicates a 988 MHz part, change the
+ \ speed code to the old engineering sample code for 1001 MHz
+ \ and reboot to switch to the higher speed
+ rated-speed 0= if
+ es-speed-1g d# 14 lshift 0 0 1 0 0 0 0 3 pgm-fuses2
+ bye
+ then
+
+ \ If the speed code has already been reprogrammed to the
+ \ engineering sample 1001 MHz value, but the SW version field
+ \ is 0, set the SW version field to 1. This fixes an initial
+ \ batch of 200 chips whose speed code was reprogrammed
+ \ using a different procedure.
+ rated-speed 2 = if
+ 0 0 0 1 0 0 0 0 3 pgm-fuses2
+ then
+ then
+ then
+;
Author: rsmith
Date: Sat Oct 20 03:43:01 2012
New Revision: 3376
URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3376
Log:
OLPC XO-4 - EC Code 0.2.04
Modified:
cpu/arm/olpc/4.0/ec-version.fth
Modified: cpu/arm/olpc/4.0/ec-version.fth
==============================================================================
--- cpu/arm/olpc/4.0/ec-version.fth Sat Oct 20 03:42:59 2012 (r3375)
+++ cpu/arm/olpc/4.0/ec-version.fth Sat Oct 20 03:43:01 2012 (r3376)
@@ -1,6 +1,6 @@
\ The EC microcode
macro: EC_PLATFORM cl4
-macro: EC_VERSION 7_0_2_03
+macro: EC_VERSION 7_0_2_04
\ Alternate command for getting EC microcode, for testing new versions.
\ Temporarily uncomment the line and modify the path as necessary
Author: rsmith
Date: Sat Oct 20 03:42:59 2012
New Revision: 3375
URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3375
Log:
OLPC ARM: convert s3-selftest to use sus power measurement
ec-sus-pwr reads a power measurement from the EC that only happens
after the EC senses the SoC is in suspend. This reading gives much
more consistent results as long as the SoC is suspended for long
enough for the EC to update. (1s or more)
Modified:
cpu/arm/mmp2/rtc.fth
Modified: cpu/arm/mmp2/rtc.fth
==============================================================================
--- cpu/arm/mmp2/rtc.fth Sat Oct 20 02:20:13 2012 (r3374)
+++ cpu/arm/mmp2/rtc.fth Sat Oct 20 03:42:59 2012 (r3375)
@@ -67,7 +67,7 @@
\ on the operator.
." Testing suspend/resume" cr
." Sleeping for 3 seconds .. " d# 1000 ms
- ec-rst-pwr ['] cancel-alarm 3 rtc-wake str ec-max-pwr ( power )
+ ec-rst-pwr ['] cancel-alarm 3 rtc-wake str ec-sus-pwr ( power )
\ Negative power is consumed from battery, positive is supplied to battery
dup suspend-power-limit < if ( power )
." System used too much power during suspend - " negate .d ." mW" cr ( )
Author: quozl
Date: Sat Oct 20 01:47:51 2012
New Revision: 3373
URL: http://tracker.coreboot.org/trac/openfirmware/changeset/3373
Log:
OLPC - accelerometer stack effect comment fix
Modified:
cpu/arm/olpc/accelerometer.fth
Modified: cpu/arm/olpc/accelerometer.fth
==============================================================================
--- cpu/arm/olpc/accelerometer.fth Wed Oct 17 09:05:36 2012 (r3372)
+++ cpu/arm/olpc/accelerometer.fth Sat Oct 20 01:47:51 2012 (r3373)
@@ -109,7 +109,7 @@
error? if accelerometer-off true exit then
false
;
-: lis3dhtr-selftest ( -- )
+: lis3dhtr-selftest ( -- error? )
\ Use the device's selftest function to force a change in one direction
delay ( )
average-acceleration@ ( x y z )