Author: wmb
Date: 2009-05-29 04:26:07 +0200 (Fri, 29 May 2009)
New Revision: 1205
Added:
cpu/x86/pc/olpc/via/boardrev.fth
cpu/x86/pc/olpc/via/ec.bth
Modified:
cpu/x86/pc/olpc/via/config.fth
cpu/x86/pc/olpc/via/devices.fth
cpu/x86/pc/olpc/via/fw.bth
cpu/x86/pc/olpc/via/ioinit.fth
cpu/x86/pc/olpc/via/romreset.bth
cpu/x86/pc/olpc/via/startgfxinit.fth
cpu/x86/pc/olpc/via/versions.fth
Log:
VIA - checkpoint - video works
Added: cpu/x86/pc/olpc/via/boardrev.fth
===================================================================
--- cpu/x86/pc/olpc/via/boardrev.fth (rev 0)
+++ cpu/x86/pc/olpc/via/boardrev.fth 2009-05-29 02:26:07 UTC (rev 1205)
@@ -0,0 +1,50 @@
+purpose: Determine the board revision based on hardware and EC info
+\ See license at end of file
+
+0 value board-revision
+
+\ Constructs a string like "B4" or "preB4" or "postB4"
+: model-name$ ( -- model$ )
+ board-revision h# 10 /mod ( minor major )
+ swap dup 8 = if ( major minor )
+ drop " " ( major prefix$ )
+ else ( major minor )
+ 8 < if " pre" else " post" then ( major prefix$ )
+ then ( major prefix$ )
+ push-hex
+ rot <# u# u# drop hold$ 0 u#> ( adr len )
+ pop-base
+ 2dup + 2- 2 upper ( model$ ) \ Upper case for base model
+;
+
+stand-init: board revision
+ ['] board-id@ catch if 0 then case
+ 0 of 0 endof \ EC broken
+ ( board-id ) dup h# 10 * 8 + swap \ E.g. b3 -> b38
+ endcase
+ to board-revision
+;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2007 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Modified: cpu/x86/pc/olpc/via/config.fth
===================================================================
--- cpu/x86/pc/olpc/via/config.fth 2009-05-27 23:07:49 UTC (rev 1204)
+++ cpu/x86/pc/olpc/via/config.fth 2009-05-29 02:26:07 UTC (rev 1205)
@@ -6,6 +6,9 @@
create compute-timings
\ create demo-board
create xo-board
+[ifdef] xo-board
+\ create use-ec
+[then]
\ --- The environment that "boots" us ---
\ - Image Format - Example Media - previous stage bootloader
Modified: cpu/x86/pc/olpc/via/devices.fth
===================================================================
--- cpu/x86/pc/olpc/via/devices.fth 2009-05-27 23:07:49 UTC (rev 1204)
+++ cpu/x86/pc/olpc/via/devices.fth 2009-05-29 02:26:07 UTC (rev 1205)
@@ -260,9 +260,11 @@
fload ${BP}/dev/olpc/kb3700/ecserial.fth \ Serial access to EC chip
+.( Implement ignore-power-button) cr
+: ignore-power-button ( -- ) ;
fload ${BP}/dev/olpc/kb3700/ecio.fth \ I/O space access to EC chip
-fload ${BP}/cpu/x86/pc/olpc/boardrev.fth \ Board revision decoding
+fload ${BP}/cpu/x86/pc/olpc/via/boardrev.fth \ Board revision decoding
[then]
: cpu-mhz ( -- n )
@@ -305,7 +307,7 @@
[ifdef] use-ec
fload ${BP}/cpu/x86/pc/olpc/mfgdata.fth \ Manufacturing data
fload ${BP}/cpu/x86/pc/olpc/mfgtree.fth \ Manufacturing data in device tree
-fload ${BP}/cpu/x86/pc/olpc/kbdtype.fth \ Export keyboard type
+\ fload ${BP}/cpu/x86/pc/olpc/kbdtype.fth \ Export keyboard type
fload ${BP}/dev/olpc/kb3700/battery.fth \ Battery status reports
Added: cpu/x86/pc/olpc/via/ec.bth
===================================================================
--- cpu/x86/pc/olpc/via/ec.bth (rev 0)
+++ cpu/x86/pc/olpc/via/ec.bth 2009-05-29 02:26:07 UTC (rev 1205)
@@ -0,0 +1,18 @@
+purpose: Fetch the EC (Embedded Controller, i.e. KB3700) microcode
+
+command: &builder &this
+build-now
+
+fload ${BP}/cpu/x86/pc/olpc/via/versions.fth
+
+\ If there is a GET_EC macro, use it instead of fetching the released version.
+" ${GET_EC}" expand$ nip [if]
+ " ${GET_EC}" expand$ $sh
+[else]
+ " wget -q http://dev.laptop.org/pub/ec/ec_v${EC_VERSION}.img -O ec.img" expand$ $sh
+[then]
+
+\ This forces the creation of an ec.log file, so we don't re-fetch ec.img
+writing ec.version
+" ${EC_VERSION}"n" expand$ ofd @ fputs
+ofd @ fclose
Modified: cpu/x86/pc/olpc/via/fw.bth
===================================================================
--- cpu/x86/pc/olpc/via/fw.bth 2009-05-27 23:07:49 UTC (rev 1204)
+++ cpu/x86/pc/olpc/via/fw.bth 2009-05-29 02:26:07 UTC (rev 1205)
@@ -697,6 +697,12 @@
\ " flash http:\\18.85.46.172\new.rom" eval
;
+: sci-wakeup ( -- ) ;
+: acpi-l@ ( index -- l ) drop 0 ;
+: acpi-l! ( l index -- ) 2drop ;
+: s3 ( -- ) ;
+
+
[ifdef] use-ec
\ Fancy battery charge logger.
fload ${BP}/cpu/x86/pc/olpc/charge.fth
Modified: cpu/x86/pc/olpc/via/ioinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/ioinit.fth 2009-05-27 23:07:49 UTC (rev 1204)
+++ cpu/x86/pc/olpc/via/ioinit.fth 2009-05-29 02:26:07 UTC (rev 1205)
@@ -103,11 +103,13 @@
c1 20 00 mreg \ Disable USB PIRQ
end-table
+[ifndef] xo-board
d# 16 2 devfunc \ UHCI Ports 4,5
4a 02 02 mreg \ Enable Stop Bus Master Cycle if HALT Bit is Asserted
4b 60 60 mreg \ Enable New UHCI Dynamic Scheme - 66MHz (40) & 33MHz (20)
c1 20 00 mreg \ Disable USB PIRQ
end-table
+[then]
d# 16 4 devfunc \ EHCI
42 40 40 mreg \ Enable Check PRESOF of ITDOUT Transaction during Fetching Data from DRAM
@@ -139,17 +141,27 @@
\ 4d 01 01 mreg \ Enable LPC TPM
\ 4e 08 08 mreg \ Enable ports 74/75 for CMOS RAM access
4e 18 18 mreg \ Enable ports 74/75 for CMOS RAM access - 10 res be like Phx
-\ 50 40 40 mreg \ Disable USB device mode
- 50 c0 c0 mreg \ Disable USB device mode - 80 res be like Phx
+
+[ifdef] demo-board
+ 50 40 40 mreg \ Disable USB device mode
+[then]
[ifdef] xo-board
+ 50 40 40 mreg \ Disable USB device mode
51 9f 88 mreg \ Enable SDIO and internal RTC, disable card reader, int mouse & kbd
[then]
+
52 1b 19 mreg \ No wait state between SIRQ transactions (10), Enable SIRQ (08), SIRQ frame is 6 clocks (3>1)
+.( Check PC/PCI DMA necessity) cr
53 80 80 mreg \ Enable PC/PCI DMA
+.( Check interrupt routing) cr
55 ff a0 mreg \ INTA and External General interrupt routing - INTA:IRQ10
56 ff b9 mreg \ INTB,C routing - INTC:IRQ11, INTB:IRQ9
57 f0 a0 mreg \ INTD routing - INTD:IRQ10
+.( Check RTC century byte mapping to cmos 32 - see d17f0 rx58) cr
58 40 40 mreg \ Enable Internal APIC
+[ifdef] xo-board
+ 59 ff 18 mreg \ Keyboard (ports 60,64) and ports 62,66 on LPC bus (EC)
+[then]
\ 5b 10 10 mreg \ Enable APIC Clock Gating
5b 53 53 mreg \ Enable APIC Clock Gating - 43 res be like Phx
68 80 80 mreg \ Enable HPETs
@@ -179,12 +191,14 @@
[ifdef] demo-board
97 ff 80 mreg \ be like Phx
[then]
-[ifdef] xo-board
- 97 ff 81 mreg \ GPIO4/5 not KBDT/KBCK
-[then]
- 9b ff 88 mreg \ 80 res be like Phx
+\ NO! This doesn't work. If these lines are set as GPIOs, the system
+\ will crash when you disable the internal KBC.
+\ [ifdef] xo-board
+\ 97 ff 81 mreg \ GPIO4/5 not KBDT/KBCK
+\ [then]
+ 9b ff 88 mreg \ 80 undoc but is LVDS power. 0 forces LVDS power off, 1 lets 3d5.D2[7,6,3] control it
[ifdef] xo-board
9f ff 08 mreg \ Slot 3 is SDIO, no pullup on KB/MS, fastest SD
[then]
Modified: cpu/x86/pc/olpc/via/romreset.bth
===================================================================
--- cpu/x86/pc/olpc/via/romreset.bth 2009-05-27 23:07:49 UTC (rev 1204)
+++ cpu/x86/pc/olpc/via/romreset.bth 2009-05-29 02:26:07 UTC (rev 1205)
@@ -164,7 +164,6 @@
\ fload ${BP}/cpu/x86/pc/olpc/via/startgtlinit.fth
-.( Not doing io init)
fload ${BP}/cpu/x86/pc/olpc/via/ioinit.fth
\ Enable the keyboard controller
Modified: cpu/x86/pc/olpc/via/startgfxinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startgfxinit.fth 2009-05-27 23:07:49 UTC (rev 1204)
+++ cpu/x86/pc/olpc/via/startgfxinit.fth 2009-05-29 02:26:07 UTC (rev 1205)
@@ -51,7 +51,12 @@
5a 3c4 port-wb 00 3c5 port-wb \ Point back to primary registers
6d 3c4 port-wb e0 3c5 port-wb \ Base address [28:21] of SL in System Memory - base is 1c00.0000 - fbsize, memsize
+[ifdef] demo-board
6e 3c4 port-wb 00 3c5 port-wb \ Base address [36:29] of SL in System Memory
+[then]
+[ifdef] xo-board
+ 6e 3c4 port-wb 01 3c5 port-wb \ Base address [36:29] of SL in System Memory
+[then]
6f 3c4 port-wb 00 3c5 port-wb \ Base address [47:37] of SL in System Memory
36 3c4 port-wb 11 3c5 port-wb \ Subsystem Vendor ID 1
Modified: cpu/x86/pc/olpc/via/versions.fth
===================================================================
--- cpu/x86/pc/olpc/via/versions.fth 2009-05-27 23:07:49 UTC (rev 1204)
+++ cpu/x86/pc/olpc/via/versions.fth 2009-05-29 02:26:07 UTC (rev 1205)
@@ -2,7 +2,7 @@
\ The overall firmware revision
macro: FW_MAJOR A
-macro: FW_MINOR 03d
+macro: FW_MINOR 03e
\ The EC microcode
macro: EC_VERSION a00
1
0
Author: wmb
Date: 2009-05-28 01:07:49 +0200 (Thu, 28 May 2009)
New Revision: 1204
Added:
cpu/x86/pc/olpc/via/startgtlinit.fth
dev/mmc/sdhci/sdhcixo.bth
Modified:
cpu/x86/pc/olpc/via/addrs.fth
cpu/x86/pc/olpc/via/config.fth
cpu/x86/pc/olpc/via/demodram.fth
cpu/x86/pc/olpc/via/devices.fth
cpu/x86/pc/olpc/via/dramtiming.fth
cpu/x86/pc/olpc/via/fw.bth
cpu/x86/pc/olpc/via/ioinit.fth
cpu/x86/pc/olpc/via/olpc.bth
cpu/x86/pc/olpc/via/romreset.bth
cpu/x86/pc/olpc/via/sd8686.bth
cpu/x86/pc/olpc/via/startcacheasram.fth
cpu/x86/pc/olpc/via/startdraminit.fth
cpu/x86/pc/olpc/via/startgfxinit.fth
cpu/x86/pc/olpc/via/starthostctl.fth
cpu/x86/pc/olpc/via/startmacros.fth
cpu/x86/pc/olpc/via/versions.fth
cpu/x86/pc/ramtest.fth
cpu/x86/pc/resetend.fth
Log:
OLPV VIA version - checkpoint build that works on XO 1.5 Atest boards.
Modified: cpu/x86/pc/olpc/via/addrs.fth
===================================================================
--- cpu/x86/pc/olpc/via/addrs.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/addrs.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -8,7 +8,8 @@
\ h# fffe.0000 constant rom-pa \ Physical address of boot ROM
\ h# 2.0000 constant /rom \ Size of boot ROM
rom-pa constant dropin-base
-[else]
+[then]
+[ifdef] xo-board
h# fff0.0000 constant rom-pa \ Physical address of boot ROM
h# 10.0000 constant /rom \ Size of boot ROM
rom-pa h# 1.0000 + constant dropin-base
@@ -18,7 +19,8 @@
dropin-base h# 20 + constant ResetBase \ Location of "reset" dropin in ROM
-h# 1bc0.0000 value fw-pa \ Changed in probemem.fth
+\ h# 1bc0.0000 value fw-pa \ Changed in probemem.fth
+h# bc0.0000 value fw-pa \ Changed in probemem.fth
h# 20.0000 constant /fw-ram
[then]
Modified: cpu/x86/pc/olpc/via/config.fth
===================================================================
--- cpu/x86/pc/olpc/via/config.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/config.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -3,7 +3,9 @@
create olpc \ OLPC-specific build
-create demo-board
+create compute-timings
+\ create demo-board
+create xo-board
\ --- The environment that "boots" us ---
\ - Image Format - Example Media - previous stage bootloader
@@ -11,9 +13,9 @@
\ - OBMD format - ROM - direct boot from ROM
create rom-loaded
-create coreboot-loaded
+\ create coreboot-loaded
-create virtual-mode
+\ create virtual-mode
create addresses-assigned \ Define if base addresses are already assigned
\ create serial-console \ Define to default to serial port for console
create pc
Modified: cpu/x86/pc/olpc/via/demodram.fth
===================================================================
--- cpu/x86/pc/olpc/via/demodram.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/demodram.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -14,8 +14,13 @@
\ Must use "CPU delay" to make sure VLINK is dis-connect
0 7 devfunc 47 00 04 mreg end-table d# 20 wait-us
0 3 devfunc 90 07 07 mreg end-table d# 20 wait-us \ First set DRAM Freq to invalid
+[ifdef] demo-board
+ 0 3 devfunc 90 07 04 mreg end-table d# 20 wait-us \ 266 MHz !ATEST
+[then]
+[ifdef] xo-board
\ 0 3 devfunc 90 07 03 mreg end-table d# 20 wait-us \ 200 MHz ATEST
- 0 3 devfunc 90 07 04 mreg end-table d# 20 wait-us \ 266 MHz !ATEST
+ 0 3 devfunc 90 e7 03 mreg end-table d# 20 wait-us \ 200 MHz ATEST
+[then]
0 3 devfunc 6b d0 c0 mreg end-table d# 20 wait-us \ PLL Off
0 3 devfunc 6b 00 10 mreg end-table d# 20 wait-us \ PLL On
0 3 devfunc 6b c0 00 mreg end-table \ Adjustments off
@@ -49,17 +54,22 @@
62 07 TCL 2 - mreg \ CL 3
62 08 08 mreg \ 8-bank timing constraint
+\ !!!
62 f0 Tras ns>tck 5 - 4 << mreg \ Tras: ceil( 40.00/5) = 8 - 5 = 0x03
\ 62 ff 3a mreg \ CL, 8-bank constraint, Tras Tras = 8T (3+5=8)
63 e0 Twr ns>tck 2 - 5 << mreg \ Twr: ceil( 15.00/5) = 3 - 2 = 0x01
- 63 08 Trtp ns>tck 2 - 3 << mreg \ Trtp: ceil( 7.00/5) = 2 - 2 = 0x00
+\ !!!
+ 63 08 Trtp ns>tck 2 - 3 << mreg \ Trtp: ceil( 7.50/5) = 2 - 2 = 0x00
+\ !!!
63 03 Twtr ns>tck 2 - mreg \ Twtr: ceil( 10.00/5) = 2 - 2 = 0x00
\ 63 ff 20 mreg \ Twr, Twtr, Trtp Twr=3T (15ns/5), Twtr=2T (10/5) Trtp=2T ceil(7.5/5)
+\ !!!
64 0e Trp ns>tck 2 - 1 << mreg \ Trp: ceil( 15.00/5) = 3 - 2 = 0x01
+\ !!!
64 e0 Trcd ns>tck 2 - 5 << mreg \ Trcd: ceil( 15.00/5) = 3 - 2 = 0x01
\ 64 ff 22 mreg \ Trp 3, Trcd 3
@@ -69,6 +79,7 @@
\ DRDR_BL.c
\ DRAMDRDYsetting
0 2 devfunc
+[ifdef] demo-board
60 ff aa mreg \ DRDY Timing Control 1 for Read Line
61 ff 0a mreg \ DRDY Timing Control 2 for Read Line
62 ff 00 mreg \ Reserved, probably channel B
@@ -79,11 +90,25 @@
67 ff 00 mreg \ Reserved, probably channel B
54 0a 08 mreg \ Misc ctl 1 - special mode for DRAM cycles
51 80 80 mreg \ Last step - enable DRDY timing
+[then]
+[ifdef] xo-board
+ 60 ff 2a mreg \ DRDY Timing Control 1 for Read Line
+ 61 ff 00 mreg \ DRDY Timing Control 2 for Read Line
+ 62 ff 00 mreg \ Reserved, probably channel B
+ 63 ff 15 mreg \ DRDY Timing Control 1 for Read QW
+ 64 ff 00 mreg \ DRDY Timing Control 2 for Read QW
+ 65 ff 00 mreg \ Reserved, probably channel B
+ 66 ff 00 mreg \ Burst DRDR Timing Control for Second cycle in burst
+ 67 ff 00 mreg \ Reserved, probably channel B
+ 54 1e 1c mreg \ Misc ctl 1 - special mode for DRAM cycles
+ 51 ff f8 mreg \ Last step - enable DRDY timing
+[then]
end-table
\ DRAMBurstLength
0 3 devfunc
6c 08 08 mreg \ Burst length 8
+[ifdef] demo-board
\ DrivingSetting.c
\ DrivingODT
d0 ff 88 mreg \ Pull up/down Termination strength
@@ -120,6 +145,8 @@
\ DRAMClkCtrl
\ WrtDataPhsCtrl
+ 70 ff 00 mreg \ Output delay
+ 71 ff 04 mreg
74 07 00 mreg \ DQS Phase Offset
75 07 00 mreg \ DQ Phase Offset
76 ef 07 mreg \ Write data Phase control
@@ -141,9 +168,87 @@
78 3f 03 mreg \ DQS Input Capture Range Control A
7a 0f 00 mreg \ Reserved
7b 7f 20 mreg \ Read Data Phase Control
+[then]
-\ DCLKPhsCtrl
- 99 1e 12 mreg \ MCLKOA[4,3,0] outputs
+[ifdef] xo-board \ DDR400
+\ DrivingSetting.c
+\ DrivingODT
+ d0 ff 88 mreg \ Pull up/down Termination strength
+ d6 fc fc mreg \ DCLK/SCMD/CS drive strength
+ d3 03 01 mreg \ Compensation control - enable DDR Compensation
+ 9f f3 00 mreg \ 533,667,800: 11 SDRAM ODT Control 2 - Late extension values
+ d5 f0 00 mreg \ DQ/DQS Burst and ODT Range Select - disable bursts for channel A
+ d7 c0 00 mreg \ SCMD/MA Burst - Disable SDMD/MAA burst
+ d5 0f 05 mreg \ Enable DRAM MD Pad ODT of Channel A High 32 bits
+
+ 9c ff e4 mreg \ ODT Lookup table - XO uses ODT0 only
+ d4 3f 30 mreg \ ChannelA MD ODT dynamic-on
+ 9e ff 81 mreg \ 533: 91 667: a1 800: a1 Enable Channel A differential DQS Input
+
+\ DrivingDQS,DQ,CS,MA,DCLK
+ e0 ff ee mreg \ DQS A
+ e2 ff ac mreg \ DQ A
+ e4 ff 44 mreg \ CS A
+ e8 ff 86 mreg \ MA A
+ e6 ff ff mreg \ MCLK A
+\ e1 ff ee mreg \ DQS B
+\ e3 ff ca mreg \ DQ B
+\ e5 ff 44 mreg \ CS B
+\ e9 ff 86 mreg \ MA B
+\ e7 ff ff mreg \ MCKL B
+
+\ ClkCtrl.c (register tables in mainboard/via/6413e/DrivingClkPhaseData.c)
+\ DutyCycleCtrl
+ ec ff 30 mreg \ DQS/DQ Output duty control
+ ed ff 88 mreg \ 533: 84 667: 88 800: 88
+ ee ff 00 mreg \ 533: 00 667: 40 800: 40 DCLK Output duty control
+ ef 33 00 mreg \ DQ CKG Input Delay
+
+\ DRAMClkCtrl
+\ WrtDataPhsCtrl
+ 70 ff 00 mreg \ Output delay
+ 71 ff 05 mreg \ 533: 4 667: 6 800: 5
+ 74 07 07 mreg \ DQS Phase Offset 533: 0 667: 0 800: 1
+ 75 07 07 mreg \ DQ Phase Offset 533: 0 667: 0 800: 1
+ 76 ef 06 mreg \ Write data Phase control 533: 7 667: 87 800: 80
+ 8c 03 03 mreg \ DQS Output Control
+
+\ ClkPhsCtrlFBMDDR2
+ 91 07 07 mreg \ DCLK Phase 533: 0 667: 1 800: 2
+ 92 07 02 mreg \ CS/CKE Phase 533: 3 667: 3 800: 4
+ 93 07 03 mreg \ SCMD/MA Phase 533: 4 667: 5 800: 6
+\ Channel B fields
+\ 91 70 70 mreg \ DCLK Phase 533: 0 667: 10 800: 20
+\ 92 70 20 mreg \ CS/CKE Phase 533: 30 667: 30 800: 40
+\ 93 70 30 mreg \ SCMD/MA Phase 533: 40 667: 50 800: 60
+
+\ DQDQSOutputDlyCtrl
+ f0 77 00 mreg \ Group A0/1
+ f1 77 00 mreg \ Group A2/3
+ f2 77 00 mreg \ Group A4/5
+ f3 77 00 mreg \ Group A6/7
+
+ f4 77 00 mreg \ ?
+ f5 77 00 mreg \ ?
+ f6 77 00 mreg \ ?
+ f7 77 00 mreg \ ?
+
+\ DQSInputCaptureCtrl
+ 77 bf 9b mreg \ DQS Input Delay - Manual, value from VIA's BIOS
+ 78 3f 01 mreg \ 533: 3 667: 7 800: d DQS Input Capture Range Control A
+ 79 ff 83 mreg \ 533: 87 667: 89 800: 89
+ 7a ff 00 mreg \ Reserved
+ 7b ff 10 mreg \ 533: 20 667: 34 800: 34 Read Data Phase Control
+ 8b ff 10 mreg \ 533: 20 667: 34 800: 34
+[then]
+
+\ DCLKPhsCtrl - depends on which clock outputs are used
+[ifdef] demo-board
+ 99 1e 12 mreg \ MCLKOA[3,2,1,0] outputs
+[then]
+[ifdef] xo-board
+ 99 1e 1e mreg \ MCLKOA[1,0] outputs
+[then]
end-table
\ DevInit.c
@@ -158,7 +263,7 @@
54 ff 00 mreg \ default PR0=VR0; PR1=VR1
55 ff 00 mreg \ default PR2=VR2; PR3=VR3
56 ff 00 mreg \ default PR4=VR4; PR5=VR5
- 57 ff 00 mreg \ default PR4=VR4; PR5=VR5
+ 57 ff 00 mreg \ default PR6=VR6; PR7=VR7
60 ff 00 mreg \ disable fast turn-around
65 ff d1 mreg \ AGP timer = D; Host timer = 1; (coreboot uses 9 for host timer)
@@ -166,7 +271,7 @@
68 ff 0C mreg
69 0F 04 mreg \ set RX69[3:0]=0000b
6A ff 00 mreg \ refresh counter
- 6E 07 80 mreg \ must set 6E[7],or else DDR2 probe test will fail
+ 6E 87 80 mreg \ must set 6E[7],or else DDR2 probe test will fail
85 ff 00 mreg
40 ff 00 mreg
end-table
@@ -201,8 +306,14 @@
end-table
DDRinit #) call
+[else]
+ 0 3 devfunc
+ 55 ff 00 mreg \ Disable ranks 2 and 3 and leave them off
+ end-table
[then]
+ h# 12 port80
+
forth #ranks 3 >= assembler [if]
0 3 devfunc
41 ff 00 mreg \ Rank 1 top back to 0 to work on other ranks
@@ -224,6 +335,8 @@
end-table
[then]
+ h# 13 port80
+
forth #ranks 4 >= assembler [if]
0 3 devfunc
54 ff 00 mreg \ Disable ranks 0,1
@@ -239,96 +352,147 @@
end-table
[then]
+ h# 14 port80
+
0 3 devfunc
- 69 03 03 mreg \ Reinstate page optimizations (03) - FF #ranks !ATEST
-\ 69 c3 c3 mreg \ Reinstate page optimizations (03) - FF #ranks ATEST 8-bank interleave
+forth #banks 8 = assembler [if]
+ 69 c3 c3 mreg \ Reinstate page optimizations (03) 8-bank interleave (c0)
+[else]
+ 69 c3 83 mreg \ Reinstate page optimizations (03) 4-bank interleave (80)
+[then]
+
\ RankMap.c
\ DRAMBankInterleave
\ (see 69 above)
87 ff 00 mreg \ Channel B #banks or some such - FF BA
\ SizingMATypeM
+
+[ifdef] compute-timings
+ 50 ff ma-type 5 << mreg
+[else]
50 ff 20 mreg \ MA Map type - ranks 0/1 type 1 - 2 bank bits, 10 column bits !ATEST
+\ Check 1T command rate. What controls it?
\ 50 ff a1 mreg \ 1T Command Rate, RMA Map type - ranks 0/1 type 5 - 3 bank bits, 14 row bits, 10 col bits ATEST
+[then]
+
51 ff 60 mreg \ "Reserved"
52 ff 33 mreg \ Bank interleave on A17, A18, and
- 53 ff 3f mreg \ A19 (but BA2 off because 4 banks), Rank interleave on A20 and A21 !ATEST
-\ 53 ff bf mreg \ BA2 on (80), A19, Rank interleave on A20 and A21 ATEST
+
+forth #banks 8 = [if]
+ 53 ff bf mreg \ BA2 on (80), A19, Rank interleave on A20 and A21
+[else]
+ 53 ff 3f mreg \ A19 (but BA2 off because 4 banks), Rank interleave on A20 and A21
+[then]
\ Different interleave bits might improve performance on some workloads
- 54 ff 89 mreg \ Rank map A 0/1 !ATEST
-\ 54 ff 80 mreg \ Rank map A 0/1 ATEST Rank 0 only
- 55 ff 00 mreg \ Rank map A 2/3
+forth #ranks 1 > assembler [if]
+ 54 ff 89 mreg \ Rank map A 0/1 Ranks 0 and 1
+[else]
+ 54 ff 80 mreg \ Rank map A 0/1 Rank 0 only
+[then]
+
+forth #ranks 3 < assembler [if]
+ 55 ff 00 mreg \ Rank map A 2/3 2 & 3 off
+[then]
+forth #ranks 3 = assembler [if]
+ 55 ff a0 mreg \ Rank map A 2/3 2 on 3 off
+[else]
+ 55 ff ab mreg \ Rank map A 2/3 2 & 3 on
+[then]
+
56 ff 00 mreg \ Rank map B ?
57 ff 00 mreg \ Rank map B ?
- 40 ff 04 mreg \ Rank top 0 !ATEST
-\ 40 ff 10 mreg \ Rank top 0 ATEST 1 GiB
- 41 ff 08 mreg \ Rank top 1 !ATEST
-\ 41 ff 00 mreg \ Rank top 1 ATEST
+ 40 ff rank-top0 mreg \ Rank top 0 (register value in units of 64MB)
+ 41 ff rank-top1 mreg \ Rank top 1
+ 42 ff rank-top2 mreg \ Rank top 2
+ 43 ff rank-top3 mreg \ Rank top 3
- 42 ff 00 mreg \ Rank top 2
- 43 ff 00 mreg \ Rank top 3
-
- 48 ff 00 mreg \ Rank base 0
- 49 ff 04 mreg \ Rank base 1 !ATEST
-\ 49 ff 00 mreg \ Rank base 1 ATEST
- 4a ff 00 mreg \ Rank base 2
- 4b ff 00 mreg \ Rank base 3
+ 48 ff rank-base0 mreg \ Rank base 0
+ 49 ff rank-base1 mreg \ Rank base 1
+ 4a ff rank-base2 mreg \ Rank base 2
+ 4b ff rank-base3 mreg \ Rank base 3
end-table
- 20 8f60 config-wb \ DRAM Bank 7 ending address - controls DMA upstream !ATEST
-\ 40 8f60 config-wb \ DRAM Bank 7 ending address - controls DMA upstream ATEST
+ h# 15 port80
+
+ total-size 8f60 config-wb \ DRAM Bank 7 ending address - controls DMA upstream
0388 config-rb ax bx mov 0385 config-setup bx ax mov al dx out \ Copy Low Top from RO reg 88 to reg 85
0388 config-rb ax bx mov 8fe5 config-setup bx ax mov al dx out \ Copy Low Top from RO reg 88 to SB Low Top e5
-0 [if] \ Very simple memtest
+\ d# 17 7 devfunc
+\ e6 ff 07 mreg \ Enable Top, High, and Compatible SMM
+\ end-table
+
+1 [if] \ Very simple memtest
+long-offsets on
ax ax xor
-h# 12345678 # bx mov
-bx 0 [ax] mov
-h# 5555aaaa # 4 [ax] mov
-0 [ax] dx mov
-dx bx cmp = if
- ascii G report ascii 2 report h# 20 report
+h# 12345678 # bx mov \ Data value to write to address 0
+bx 0 [ax] mov \ Write to address 0
+h# 5555aaaa # h# 40 [ax] mov \ Write 5555aaaa to address 0x40
+0 [ax] dx mov \ Read from address 0 into register EDX
+dx bx cmp = if \ Compare expected value (EBX) with read value (EDX)
+ \ Compare succeeded
+\ ascii G report ascii 2 report h# 20 report \ Display "G2 " - Good
else
- dx ax mov dot #) call
- ascii B report ascii 2 report h# 20 report
+ \ Compare failed
+ dx ax mov dot #) call \ Display read value
+ ascii B report ascii 2 report h# 20 report \ Display "B2 " - Bad
+
+ h# ffff.0000 # ax mov ax call \ C Forth
+
hlt
then
[then]
-\ d# 17 7 devfunc
-\ e6 ff 07 mreg \ Enable Top, High, and Compatible SMM
-\ end-table
+ h# 16 port80
\ DQSSearch.c
\ DRAMDQSOutputSearch
0 3 devfunc
- 70 ff 00 mreg \ Output delay
- 71 ff 04 mreg
\ DRAMDQSInputSearch
- 77 ff 00 mreg \ Input delay auto
+\ Leave the following set to the manual value.
+\ Eventually we should implement an auto-search
+\ 77 ff 00 mreg \ Input delay auto
\ FinalSetting.c
\ RefreshCounter
+[ifdef] demo-board
6a ff 86 mreg \ Refresh interval - FF frequency !ATEST
-\ 6a ff ca mreg \ Refresh interval - FF frequency ATEST
+[then]
+[ifdef] xo-board
+ 6a ff 65 mreg \ Refresh interval - FF frequency ATEST
+[then]
\ DRAMRegFinalValue
60 00 d0 mreg \ Fast turn-around
66 30 80 mreg \ DRAMC queue = 4 (already set to 88 up above), park at last owner
69 00 07 mreg \ Enable multiple page
+[ifdef] demo-board
95 ff 0d mreg \ Self-refresh controls
- 96 f0 a0 mreg \ Auto self-refresh stuff
+[then]
+[ifdef] xo-board
+ 95 ff 03 mreg \ Self-refresh controls, depends on #ranks
+[then]
+ 96 f0 a0 mreg \ Enable pairwise by-rank self refresh, after 2 auto-refreshes
fb ff 3e mreg \ Dynamic clocks
fd ff a9 mreg \ Dynamic clocks
fe ff 0f mreg \ Chips select power saving for self-refresh
ff ff 3d mreg \ DSQB input delay, SCMD enabled
+[ifdef] demo-board
96 0f 03 mreg \ Enable self-refresh for ranks 0 and 1
+[then]
+[ifdef] xo-board
+ 96 0f 01 mreg \ Enable self-refresh for rank 0
+[then]
+
end-table
+ h# 17 port80
+
1 [if]
ax ax xor
h# 12345678 # bx mov
@@ -337,5 +501,3 @@
0 [ax] dx mov
dx bx cmp <> if ascii B report ascii A report ascii D report begin again then
[then]
-
-\ fload ${BP}/cpu/x86/pc/ramtest.fth
Modified: cpu/x86/pc/olpc/via/devices.fth
===================================================================
--- cpu/x86/pc/olpc/via/devices.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/devices.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -92,10 +92,10 @@
\ Create a node below the top-level FLASH node to accessing the portion
\ containing the dropin modules
-0 0 " 80000" " /flash" begin-package
+0 0 " 10000" " /flash" begin-package
" dropins" device-name
- h# 70000 constant /device
+ h# d0000 constant /device
fload ${BP}/dev/subrange.fth
end-package
Modified: cpu/x86/pc/olpc/via/dramtiming.fth
===================================================================
--- cpu/x86/pc/olpc/via/dramtiming.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/dramtiming.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -1,24 +1,61 @@
d# 5.00 value Tck
+0 value #ranks
+0 value #banks
+0 value #row-bits
+0 value #col-bits
+
\ Compute ceil(ns/tck)
: ns>tck ( ns -- tck ) Tck + 1- Tck / ;
+: ma-type ( -- ma-type-code )
+ #banks 8 = if ( )
+ #col-bits 5 - ( ma-type )
+ dup 7 u> ( ma-type error? )
+ else ( )
+ #col-bits 9 - ( ma-type )
+ dup 3 u> ( ma-type error? )
+ then
+ abort" Invalid MA type"
+;
+\ The 3 << is because of the 64-bit data width, i.e. 8 bytes, i.e. 1 << 3
+\ We compute carefully to prevent overflow or underflow
+: rank-size ( -- rank-64mb )
+ 1 #row-bits #col-bits + 3 + d# 20 - << ( bank-mb )
+ #banks * ( rank-mb )
+ 6 >> ( rank-64mb )
+;
+
[ifdef] xo-board
+.( Using XO timings) cr
+
\ DDR-400 timings for HY5PS1G4831C
d# 5.00 to Tck
d# 127.50 constant Trfc
d# 7.50 constant Trrd
+\ d# 10.00 constant Trrd
d# 3 constant TCL
-d# 40.00 constant Tras
+\ d# 40.00 constant Tras
+ d# 45.00 constant Tras
d# 15.00 constant Twr
-d# 7.50 constant Trtp
+ d# 7.50 constant Trtp
+\ d# 10.00 constant Trtp
d# 10.00 constant Twtr
d# 15.00 constant Trp
d# 15.00 constant Trcd
-1 constant #ranks
-8 constant #banks
+1 to #ranks
+8 to #banks
+d# 10 to #col-bits
+d# 14 to #row-bits
+
+0 constant rank-base0 rank-size constant rank-top0
+0 constant rank-base1 0 constant rank-top1
+0 constant rank-base2 0 constant rank-top2
+0 constant rank-base3 0 constant rank-top3
+
+rank-size #ranks * constant total-size
[then]
[ifdef] demo-board
@@ -35,6 +72,16 @@
d# 15.00 constant Trp
d# 15.00 constant Trcd
-2 constant #ranks
-4 constant #banks
+2 to #ranks
+4 to #banks
+d# 10 to #col-bits
+\ d# 14 to #row-bits
+
+0 constant rank-base0 rank-size constant rank-top0
+rank-top0 constant rank-base1 rank-base0 rank-size + constant rank-top1
+
+0 constant rank-base2 0 constant rank-top2
+0 constant rank-base3 0 constant rank-top3
+
+rank-size #ranks * constant total-size
[then]
Modified: cpu/x86/pc/olpc/via/fw.bth
===================================================================
--- cpu/x86/pc/olpc/via/fw.bth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/fw.bth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -470,7 +470,6 @@
fload ${BP}/cpu/x86/pc/olpc/via/memtest.fth
-[ifdef] Later
fload ${BP}/ofw/wifi/wifi-cfg.fth
support-package: supplicant
fload ${BP}/ofw/wifi/loadpkg.fth
@@ -481,6 +480,7 @@
;
' olpc-ssids to default-ssids
+[ifdef] Later
fload ${BP}/cpu/x86/pc/olpc/nandcastui.fth
fload ${BP}/cpu/x86/pc/olpc/wifichannel.fth
fload ${BP}/cpu/x86/pc/olpc/fsupdate.fth
Modified: cpu/x86/pc/olpc/via/ioinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/ioinit.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/ioinit.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -69,11 +69,13 @@
8f 09 01 mreg \ Falling edge trigger on slot 3 output clock under high speed
[ifdef] demo-board
99 ff f9 mreg \ Two slots
-[else]
+[then]
+[ifdef] xo-board
99 ff fa mreg \ Three slots
[then]
end-table
+0 [if]
d# 15 0 devfunc \ EIDE tuning
40 02 02 mreg \ Enable primary channel
4a ff 5e mreg \ Drive1 timing
@@ -86,6 +88,7 @@
\ d4 ac 24 mreg \ Config 3
d4 bc 34 mreg \ Config 3 - 10 res be like Phx
end-table
+[then]
\ USB Tuning
d# 16 0 devfunc \ UHCI Ports 0,1
@@ -128,6 +131,9 @@
d# 17 0 devfunc \ Bus control and power management
40 44 44 mreg \ Enable I/O Recovery time (40), Enable ports 4d0/4d1 for edge/level setting (04)
+[ifdef] xo-board
+ 41 40 40 mreg \ Enable fff0.0000-fff7.ffff ROM on LPC bus
+[then]
42 fc f0 mreg \ Various setting related to DMA line buffers
43 0f 0b mreg \ Enable PCI delayed transactions (08), Write transaction timer (02), Read transaction timer (01)
\ 4d 01 01 mreg \ Enable LPC TPM
@@ -135,6 +141,9 @@
4e 18 18 mreg \ Enable ports 74/75 for CMOS RAM access - 10 res be like Phx
\ 50 40 40 mreg \ Disable USB device mode
50 c0 c0 mreg \ Disable USB device mode - 80 res be like Phx
+[ifdef] xo-board
+ 51 9f 88 mreg \ Enable SDIO and internal RTC, disable card reader, int mouse & kbd
+[then]
52 1b 19 mreg \ No wait state between SIRQ transactions (10), Enable SIRQ (08), SIRQ frame is 6 clocks (3>1)
53 80 80 mreg \ Enable PC/PCI DMA
55 ff a0 mreg \ INTA and External General interrupt routing - INTA:IRQ10
@@ -160,16 +169,28 @@
8a 9f 1f mreg \ C-state auto switching with normal latencies
[ifdef] demo-board
8d 18 18 mreg \ fast clock as throttle timer tick, hold SMI# low until event status cleared (FIXME for OLPC)
-[else]
+[then]
+[ifdef] xo-board
8d 18 10 mreg \ fast clock as throttle timer tick, do not hold SMI# low
[then]
94 ff 68 mreg \ be like Phx
95 ff c1 mreg \ be like Phx
+[ifdef] demo-board
97 ff 80 mreg \ be like Phx
+[then]
+[ifdef] xo-board
+ 97 ff 81 mreg \ GPIO4/5 not KBDT/KBCK
+[then]
9b ff 88 mreg \ 80 res be like Phx
+
+[ifdef] xo-board
+ 9f ff 08 mreg \ Slot 3 is SDIO, no pullup on KB/MS, fastest SD
+[then]
+[ifdef] demo-board
9f ff ad mreg \ be like Phx (slot 3 is Card Reader not SDIO)
+[then]
b4 80 00 mreg \ No positive decoding for UART1 ???
b7 40 40 mreg \ 40 res be like Phx
@@ -183,7 +204,12 @@
d1 ff 05 mreg \ SMBUS IO Base Address high
d2 0f 01 mreg \ Enable SMBUS and set other characteristics
e2 80 80 mreg \ Inhibit C4 during USB isochronous transaction
+[ifdef] demo-board
e4 ff a0 mreg \ Enable short C3/C4 (80), select various multi-function pins
+[then]
+[ifdef] xo-board
+ e4 ff c0 mreg \ Enable short C3/C4 (80), select GPO10 (10) (USB_PWR_EN)
+[then]
e5 60 60 mreg \ Enable NM bus master as source of bus master status, enable NB int to wakeup from Cx
e6 20 20 mreg \ Enable USB Device Mode Bus Master as Break Event
e7 80 80 mreg \ Enable APIC Cycle Reflect to ALL Bus Master Activity Effective Signal
Modified: cpu/x86/pc/olpc/via/olpc.bth
===================================================================
--- cpu/x86/pc/olpc/via/olpc.bth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/olpc.bth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -9,6 +9,7 @@
in: ${BP}/cpu/x86/pc/olpc/via/build/paging.di
in: ${BP}/cpu/x86/pc/olpc/via/build/fw.dic
in: ${BP}/dev/mmc/sdhci/build/sdhci2.fc
+in: ${BP}/dev/mmc/sdhci/build/sdhcixo.fc
in: ${BP}/dev/mmc/sdhci/build/sdmmc.fc
in: ${BP}/dev/mmc/sdhci/mv8686/build/mv8686.fc
in: ${BP}/dev/usb2/hcd/ohci/build/ohci.fc
@@ -58,7 +59,7 @@
" ${FW_VERSION}.rom" expand$ 2dup lower ( adr len )
2dup type cr ( adr len )
$new-file
-[ifdef] Later
+[ifdef] xo-board
" ec.img" $add-file
[then]
@@ -78,7 +79,8 @@
" paging.di" $add-file
" ${BP}/cpu/x86/build/inflate.bin" " inflate" $add-dropin
- " fw.img" " firmware" $add-deflated-dropin
+\ " fw.img" " firmware" $add-deflated-dropin
+ " fw.img" " firmware" $add-dropin
" ${BP}/dev/usb2/hcd/ohci/build/ohci.fc" " class0c0310" $add-deflated-dropin
" ${BP}/dev/usb2/hcd/ehci/build/ehci.fc" " class0c0320" $add-deflated-dropin
@@ -93,7 +95,12 @@
" ${BP}/dev/pci/build/pcibridg.fc" " class060400" $add-deflated-dropin
\ " ${BP}/dev/ide/build/leghier.fc" " class01018a" $add-deflated-dropin
" ${BP}/dev/ide/build/idehier.fc" " class01018a" $add-deflated-dropin
+[ifdef] xo-board
+ " ${BP}/dev/mmc/sdhci/build/sdhcixo.fc" " class080501" $add-deflated-dropin
+[then]
+[ifdef] demo-board
" ${BP}/dev/mmc/sdhci/build/sdhci2.fc" " class080501" $add-deflated-dropin
+[then]
" ${BP}/dev/mmc/sdhci/build/sdmmc.fc" " sdmmc" $add-deflated-dropin
" ${BP}/dev/mmc/sdhci/mv8686/build/mv8686.fc" " mv8686" $add-deflated-dropin
" sd8686_helper.bin" " helper_sd.bin" $add-deflated-dropin
@@ -101,9 +108,9 @@
" builton.fth" " probe-" $add-dropin
- " ${BP}/clients/emacs/x86/emacs" " emacs" $add-deflated-dropin
- " ${BP}/clients/emacs/x86/emacs.rc" " emacs.rc" $add-deflated-dropin
- " ${BP}/clients/emacs/emacs.hlp" " emacs.hlp" $add-deflated-dropin
+\ " ${BP}/clients/emacs/x86/emacs" " emacs" $add-deflated-dropin
+\ " ${BP}/clients/emacs/x86/emacs.rc" " emacs.rc" $add-deflated-dropin
+\ " ${BP}/clients/emacs/emacs.hlp" " emacs.hlp" $add-deflated-dropin
" ${BP}/ofw/fcode/memtest.fth" " memtest.fth" $add-deflated-dropin
@@ -164,6 +171,9 @@
/rom h# 10000 - pad-file \ coreboot init image must be in last FLASH block
" coreboot.img" $add-file
[else]
+ /rom h# 10000 - pad-file \ coreboot init image must be in last FLASH block
+ " cforth.img" $add-file \ Small Forth that runs from cache
+
/rom h# 400 - pad-file \ rmstart image must start 0x400 from end
" rmstart.img" $add-file
Modified: cpu/x86/pc/olpc/via/romreset.bth
===================================================================
--- cpu/x86/pc/olpc/via/romreset.bth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/romreset.bth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -52,7 +52,7 @@
dropin-base /dcached - constant dcached-base
h# 10.0000 constant ramtest-start
-h# 20.0000 constant ramtest-end
+h# 100.0000 constant ramtest-end
fload ${BP}/cpu/x86/pc/olpc/via/startmacros.fth \ Via-oriented startup macros
@@ -68,12 +68,16 @@
fload ${BP}/cpu/x86/pc/romfind.fth \ find-dropin subroutine
+[ifdef] debug-startup
+fload ${BP}/cpu/x86/pc/dot.fth \ Numeric output subroutine
+fload ${BP}/cpu/x86/pc/olpc/via/startinteract.fth \ emitpause subroutine
+[then]
+
fload ${BP}/cpu/x86/pc/olpc/via/startusdelay.fth \ microsecond delay subroutine
fload ${BP}/cpu/x86/pc/olpc/via/startcfgio.fth \ masked config write subroutine
fload ${BP}/cpu/x86/pc/olpc/via/startdraminit.fth \ DDRinit subroutine
[ifdef] debug-startup
-fload ${BP}/cpu/x86/pc/dot.fth \ Numeric output subroutine
fload ${BP}/cpu/x86/pc/olpc/via/startcominit.fth \ cominit subroutine
[then]
@@ -93,6 +97,10 @@
00 8898 config-wb \ Disable BIOS init timer GP3
+ 08 00c config-wb \ Cache line size D0F0
+ 20 00d config-wb \ PCI master latency timer D0F0
+ 08 20c config-wb \ Cache line size D0F2
+
[ifdef] debug-startup
cominit #) call
[then]
@@ -120,14 +128,43 @@
fload ${BP}/cpu/x86/pc/olpc/via/starthostctl.fth
fload ${BP}/cpu/x86/pc/olpc/via/demodram.fth
- char o report
- h# 1e port80
+ fload ${BP}/cpu/x86/pc/olpc/via/startgfxinit.fth
+0 [if] \ Fire up C Forth
+ dcached-base 6 + 0 206 set-msr \ Dcache base address, write back
+ /dcached negate h# 800 + f 207 set-msr \ Dcache size
+ \ This region is for CForth
+ h# ffff.0000 6 + 0 208 set-msr \ ROM base address
+ /icached negate h# 800 + f 209 set-msr \ Icache size
+
+ \ Access ROM to load it into the icache
+ h# ffff.0000 # esi mov
+ /icached 4 / # ecx mov
+ rep eax lods
+
+ \ Access "RAM" area to load it into the dcache
+ dcached-base # esi mov
+ /dcached 4 / # ecx mov
+ rep eax lods
+
+ \ Put the stack pointer at the top of the dcached area
+ dcached-base /dcached + 4 - # esp mov
+ ds ax mov ax ss mov
+
+ h# ffff.0000 # ax mov ax jmp
+[then]
+
+\ fload ${BP}/cpu/x86/pc/ramtest.fth
+
fload ${BP}/cpu/x86/pc/olpc/via/startmtrrinit.fth
\ Cache is now setup normally, backed by memory
- 'ebda # sp mov \ Move stack to real memory
- fload ${BP}/cpu/x86/pc/olpc/via/startgfxinit.fth
+ char o report
+ h# 1e port80
+
+\ fload ${BP}/cpu/x86/pc/olpc/via/startgtlinit.fth
+
+.( Not doing io init)
fload ${BP}/cpu/x86/pc/olpc/via/ioinit.fth
\ Enable the keyboard controller
@@ -137,6 +174,7 @@
\ e2 2e port-wb 7 2f port-wb
fload ${BP}/cpu/x86/pc/olpc/via/startmemtop.fth
+
fload ${BP}/cpu/x86/pc/olpc/via/startcpuspeed.fth
h# 1f port80
Modified: cpu/x86/pc/olpc/via/sd8686.bth
===================================================================
--- cpu/x86/pc/olpc/via/sd8686.bth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/sd8686.bth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -5,6 +5,9 @@
fload ${BP}/cpu/x86/pc/olpc/via/versions.fth
+" ${GET_WLAN}" expand$ nip [if]
+ " ${GET_WLAN}" expand$ $sh
+[else]
" rm -f sd8686.bin sd8686_helper.bin" expand$ $sh
" wget -q http://dev.laptop.org/pub/firmware/libertas/sd8686-${WLAN_VERSION}.bin" expand$ $sh
@@ -18,6 +21,7 @@
" md5sum -b sd8686_helper.bin | cmp - sd8686_helper.bin.md5" expand$ $sh
" rm sd8686-${WLAN_VERSION}.bin.md5 sd8686_helper.bin.md5" expand$ $sh
+[then]
\ This forces the creation of a .log file, so we don't re-fetch
writing sd8686.version
Modified: cpu/x86/pc/olpc/via/startcacheasram.fth
===================================================================
--- cpu/x86/pc/olpc/via/startcacheasram.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/startcacheasram.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -14,7 +14,11 @@
/dcached negate h# 800 + f 201 set-msr \ Dcache size
dropin-base 6 + 0 202 set-msr \ ROM base address
/icached negate h# 800 + f 203 set-msr \ Icache size
+ \ This region is for CForth
+ h# ffff.0000 6 + 0 204 set-msr \ ROM base address
+ /icached negate h# 800 + f 205 set-msr \ Icache size
+
00000000.00000800. 2ff set-msr \ Enable variable MTRRs in DefType
@@ -22,7 +26,7 @@
cld
- \ Access ROM to load it into the dcache
+ \ Access ROM to load it into the icache
dropin-base # esi mov
/icached 4 / # ecx mov
rep eax lods
Modified: cpu/x86/pc/olpc/via/startdraminit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startdraminit.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/startdraminit.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -23,11 +23,30 @@
loopa
13 36b config-wb \ SDRAM MRS Enable
- 101258 #) ax mov \ Depends on Twr, CL, and Burst Length
+\ 101258 #) ax mov \ Depends on Twr, CL, and Burst Length
+ 1021d8 #) ax mov \ Depends on Twr, CL, and Burst Length
+0 [if]
+2024b
+011 BL 8
+1 BT interleave
+100 CL 4 Anck
+0 TM normal
+0 DLL rst no
+001 WR 2 write recov for autoprecharge
+ 2 and 3 are possible for 400
+0 PD fast exit from active power down
+000 ???
+
+ 12
+10 0000
+10 BA1,0 EMR2
+[then]
+
21e00 #) ax mov \ For 150 ohm; 75 ohm is 21c20
20200 #) ax mov \ For 150 ohm; 75 ohm is 21c20
+
10 36b config-wb \ SDRAM Normal
ret
Modified: cpu/x86/pc/olpc/via/startgfxinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startgfxinit.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/startgfxinit.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -1,7 +1,7 @@
\ UMARamSetting.c
\ SetUMARam
0 3 devfunc
- 99 ff 73 mreg \ 61 res be like Phx
+ \ 99 ff 73 mreg \ 61 res be like Phx
a1 00 80 mreg \ Enable internal GFX
a2 ff ee mreg \ Set GFX timers
a4 ff 01 mreg \ GFX Data Delay to Sync with Clock
Added: cpu/x86/pc/olpc/via/startgtlinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startgtlinit.fth (rev 0)
+++ cpu/x86/pc/olpc/via/startgtlinit.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -0,0 +1,59 @@
+\ After-the-fact tweaks to ROMSIP values
+0 2 devfunc
+ 70 ff 55 mreg
+ 71 ff aa mreg
+ 72 ff 66 mreg
+ 73 ff cc mreg
+ 74 00 00 mreg
+ 75 0f 04 mreg
+ 76 00 00 mreg
+ 77 00 00 mreg
+ 78 00 00 mreg
+ 79 80 00 mreg
+ 7a 00 00 mreg
+ 7b 00 00 mreg
+ a0 f1 70 mreg
+ a1 ff d6 mreg
+ a2 ff 88 mreg
+ a3 03 00 mreg
+ a4 ff 77 mreg
+ a5 0f 07 mreg
+ a6 ff 77 mreg
+ a7 ff 77 mreg
+ a8 ff 77 mreg
+ a9 ff 77 mreg
+ aa 1c 04 mreg
+ af ff 77 mreg
+ ac ff 77 mreg
+ ad ff 77 mreg
+ ae ff 77 mreg
+ af ff 77 mreg
+ b0 ff 77 mreg
+ b1 ff 77 mreg
+ b2 ff 77 mreg
+ b3 ff 77 mreg
+ b4 ff 77 mreg
+ b5 ff 77 mreg
+ b6 ff 77 mreg
+ b7 ff 77 mreg
+ b8 ff 77 mreg
+ b9 ff 77 mreg
+ ba ff 77 mreg
+ bb ff 77 mreg
+ bc 00 00 mreg
+ bd 1f 14 mreg
+ be ff 77 mreg
+ bf ff 77 mreg
+ c0 b7 10 mreg
+ c1 b7 14 mreg
+ c2 b7 14 mreg
+ c3 ff 75 mreg
+ c4 b7 10 mreg
+ c5 b7 14 mreg
+ c6 b7 20 mreg
+ c7 b7 14 mreg
+ c8 00 00 mreg
+ c9 00 00 mreg
+ ca b7 10 mreg
+ cb b7 04 mreg
+end-table
Modified: cpu/x86/pc/olpc/via/starthostctl.fth
===================================================================
--- cpu/x86/pc/olpc/via/starthostctl.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/starthostctl.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -17,6 +17,8 @@
0 2 devfunc \ HOST CPU CTL
50 1f 08 mreg \ Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
51 ff 78 mreg \ CPU I/F Ctrl-1: Disable Fast DRDY and RAW (coreboot uses 7c)
+\ Try the following value !!
+\ 51 ff f8 mreg \ CPU I/F Ctrl-1: Enable Fast DRDY and RAW (coreboot uses 7c)
52 cb cb mreg \ CPU I/F Ctrl-2: Enable all for performance
53 ff 44 mreg \ Arbitration: Host/Master Occupancy timer = 4*4 HCLK
54 1e 1c mreg \ Misc Ctrl: Enable 8QW burst Mem Access
@@ -27,6 +29,9 @@
5e ff 88 mreg \ Bandwidth Timer
5f 46 46 mreg \ CPU Misc Ctrl
+[ifdef] xo-board
+ 90 03 03 mreg \ 5T faster Host to DRAM cycles
+[then]
96 0b 0a mreg \ Write Policy
98 c1 41 mreg \ Bandwidth Timer
99 0e 06 mreg \ CPU Misc Ctrl
Modified: cpu/x86/pc/olpc/via/startmacros.fth
===================================================================
--- cpu/x86/pc/olpc/via/startmacros.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/startmacros.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -1,4 +1,5 @@
: devfunc ( dev func -- )
+\ ." Device " over .d ." function " dup .d cr
h# 100 * swap h# 800 * or h# 8000.0000 or
[ also assembler ]
# ebp mov " masked-config-writes" evaluate #) call
@@ -6,7 +7,10 @@
;
: end-table 0 c, ;
-: mreg ( reg# and or -- ) rot c, swap c, c, ;
+: mreg ( reg# and or -- )
+\ 2 pick .2 over .2 dup .2 cr \ Display the setup values at compile time
+ rot c, swap c, c,
+;
: wait-us ( us -- )
" # ax mov usdelay #) call" evaluate
;
Modified: cpu/x86/pc/olpc/via/versions.fth
===================================================================
--- cpu/x86/pc/olpc/via/versions.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/versions.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -2,14 +2,16 @@
\ The overall firmware revision
macro: FW_MAJOR A
-macro: FW_MINOR 02c
+macro: FW_MINOR 03d
\ The EC microcode
-macro: EC_VERSION e34
+macro: EC_VERSION a00
\ Alternate command for getting EC microcode, for testing new versions.
\ Temporarily uncomment the line and modify the path as necessary
-\ macro: GET_EC cp pq2e18c.img ec.img
+\ macro: GET_EC cp pq3a00.img ec.img
+\ macro: GET_EC cp "/c/Documents and Settings/Mitch Bradley/My Documents/OLPC/VIA/ecimage.bin" ec.img
+macro: GET_EC cp /via/ecimage.bin ec.img
macro: KEYS mpkeys
\ macro: KEYS testkeys
@@ -17,6 +19,10 @@
\ The wireless LAN module firmware
macro: WLAN_VERSION 9.70.7.p0
+\ Alternate command for getting WLAN firmware, for testing new versions.
+\ Temporarily uncomment the line and modify the path as necessary
+macro: GET_WLAN cp "/c/Documents and Settings/Mitch Bradley/My Documents/OLPC/DiskImages/sd8686-9.70.7.p0.bin" sd8686.bin; cp "/c/Documents and Settings/Mitch Bradley/My Documents/OLPC/DiskImages/sd8686_helper.bin" sd8686_helper.bin
+
\ The bios_verify image
macro: CRYPTO_VERSION 0.2
Modified: cpu/x86/pc/ramtest.fth
===================================================================
--- cpu/x86/pc/ramtest.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/ramtest.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -15,7 +15,35 @@
begin
0 [ax] bx mov
ax bx cmp <> if
+ ax di mov
ascii B report ascii A report ascii D report
+ di ax mov dot #) call
+ 0 [di] ax mov dot #) call
+1 [if] \ Fire up C Forth
+ dcached-base 6 + 0 206 set-msr \ Dcache base address, write back
+ /dcached negate h# 800 + f 207 set-msr \ Dcache size
+ \ This region is for CForth
+ h# ffff.0000 6 + 0 208 set-msr \ ROM base address
+ /icached negate h# 800 + f 209 set-msr \ Icache size
+
+ \ Access ROM to load it into the icache
+ h# ffff.0000 # esi mov
+ /icached 4 / # ecx mov
+ rep eax lods
+
+ \ Access "RAM" area to load it into the dcache
+ dcached-base # esi mov
+ /dcached 4 / # ecx mov
+ rep eax lods
+
+ \ Put the stack pointer at the top of the dcached area
+ dcached-base /dcached + 4 - # esp mov
+ ds ax mov ax ss mov
+
+ h# ffff.0000 # ax mov ax jmp
+[then]
+
+
begin again
then
4 # ax add
@@ -37,11 +65,13 @@
begin
0 [ax] bx mov
h# 55555555 # bx cmp <> if
+ ( bx ax mov ) dot #) call
ascii B report ascii A report ascii D report
+ h# ffff.0000 # ax mov ax jmp \ CForth
begin again
then
4 # ax add
- ramtest-end ax # cmp
+ ramtest-end # ax cmp
0= until
ascii G report ascii o report ascii o report ascii d report
carret report linefeed report
Modified: cpu/x86/pc/resetend.fth
===================================================================
--- cpu/x86/pc/resetend.fth 2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/resetend.fth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -110,8 +110,10 @@
inflate-base # ax mov \ Base address of inflater
ax call \ Inflate the firmware
else
+ ax push
h# 26 # al mov al h# 80 # out
ascii h report
+ ax pop
\ The firmware dropin isn't compressed, so we just copy it to RAM
4 [ax] cx mov \ Length of firmware (byte-swapped)
@@ -119,8 +121,8 @@
d# 32 [ax] si lea \ si: Base address of firmware code in dropin
fw-virt-base # di mov \ Firmware RAM address (destination)
- cld rep byte movs \ Copy the firmware
+ cx 2 # shr cld rep movs \ Copy the firmware
ascii m report
then
long-offsets off
Added: dev/mmc/sdhci/sdhcixo.bth
===================================================================
--- dev/mmc/sdhci/sdhcixo.bth (rev 0)
+++ dev/mmc/sdhci/sdhcixo.bth 2009-05-27 23:07:49 UTC (rev 1204)
@@ -0,0 +1,29 @@
+purpose: Load file for SDHCI (Secure Digital Host Controller Interface)
+
+command: &tokenize &this
+build-now
+
+silent on
+
+begin-tokenizing sdhcixo.fc
+
+FCode-version2
+fload ${BP}/dev/mmc/sdhci/sdhci.fth
+
+init
+
+new-device
+ 2 encode-int " reg" property
+ " sdmmc" " $load-driver" eval drop
+finish-device
+
+new-device
+ 1 encode-int " reg" property
+ " mv8686" " $load-driver" eval drop
+finish-device
+
+
+fload ${BP}/dev/mmc/sdhci/selftest.fth
+end0
+
+end-tokenizing
1
0
Author: wmb
Date: 2009-05-28 00:58:18 +0200 (Thu, 28 May 2009)
New Revision: 1203
Modified:
dev/usb2/hcd/ehci/intr.fth
Log:
USB - Fix from Lilian for interrupt endpoints on EHCI.
Modified: dev/usb2/hcd/ehci/intr.fth
===================================================================
--- dev/usb2/hcd/ehci/intr.fth 2009-05-25 20:38:16 UTC (rev 1202)
+++ dev/usb2/hcd/ehci/intr.fth 2009-05-27 22:58:18 UTC (rev 1203)
@@ -27,7 +27,7 @@
intr-in-data!
;
-: process-intr-args ( buf len pipe timeout -- ) process-bulk-args ;
+: process-intr-args ( buf len pipe -- ) process-bulk-args ;
: alloc-intr-qhqtds ( -- qh qtd ) alloc-bulk-qhqtds ;
: fill-intr-io-qtds ( dir qtd -- )
my-#qtds 0 do ( dir qtd )
@@ -51,8 +51,9 @@
to intr-in-interval
dup to intr-in-pipe
- intr-in-timeout process-intr-args
+ process-intr-args
alloc-intr-qhqtds to intr-in-qtd to intr-in-qh
+ intr-in-timeout intr-in-qh >qh-timeout l!
\ IN qTDs
TD_PID_IN intr-in-qtd fill-intr-io-qtds
@@ -101,6 +102,7 @@
intr-in-qtd restart-intr-in-qtd
\ Setup QH again
+ intr-in-timeout intr-in-qh >qh-timeout l!
intr-in-qh >hcqh-endp-char dup le-l@ QH_TD_TOGGLE invert and swap le-l!
intr-in-qtd >qtd-phys l@ intr-in-qh >hcqh-overlay >hcqtd-next le-l!
intr-in-qh sync-qhqtds
1
0
Author: wmb
Date: 2009-05-25 22:38:16 +0200 (Mon, 25 May 2009)
New Revision: 1202
Added:
cpu/mips/build/builder.dic
Log:
MIPS - checkin builder.dic
Added: cpu/mips/build/builder.dic
===================================================================
(Binary files differ)
Property changes on: cpu/mips/build/builder.dic
___________________________________________________________________
Added: svn:mime-type
+ application/octet-stream
1
0
r1201 - in cpu/mips: . Linux QEMU atlas atlas/build bonito broadcom/avx build cobalt
by svn＠openfirmware.info 25 May '09
by svn＠openfirmware.info 25 May '09
25 May '09
Author: wmb
Date: 2009-05-25 22:35:46 +0200 (Mon, 25 May 2009)
New Revision: 1201
Added:
cpu/mips/Linux/makefile
cpu/mips/QEMU/forth
cpu/mips/QEMU/mipsfth
cpu/mips/argv.fth
cpu/mips/asmtools.fth
cpu/mips/assem.fth
cpu/mips/assembler.html
cpu/mips/atlas/build/makerom
cpu/mips/atlas/forthmon.bth
cpu/mips/atlas/isaio.fth
cpu/mips/atlas/physaddr.fth
cpu/mips/atlas/virtaddr.fth
cpu/mips/basefw.bth
cpu/mips/bonito/bonito.fth
cpu/mips/bonito/devalias.fth
cpu/mips/bonito/devices.fth
cpu/mips/bonito/excption.fth
cpu/mips/bonito/flash.fth
cpu/mips/bonito/forthmon.bth
cpu/mips/bonito/fw.bth
cpu/mips/bonito/initbon.fth
cpu/mips/bonito/initcom1.fth
cpu/mips/bonito/initsb.fth
cpu/mips/bonito/initsio.fth
cpu/mips/bonito/intr.fth
cpu/mips/bonito/isaio.fth
cpu/mips/bonito/mappci.fth
cpu/mips/bonito/nvram.fth
cpu/mips/bonito/pcicfg.fth
cpu/mips/bonito/pcinode.fth
cpu/mips/bonito/physaddr.fth
cpu/mips/bonito/report.fth
cpu/mips/bonito/reset.bth
cpu/mips/bonito/resetjmp.bth
cpu/mips/bonito/rom.bth
cpu/mips/bonito/rootnode.fth
cpu/mips/bonito/start.bth
cpu/mips/bonito/virtaddr.fth
cpu/mips/boot.fth
cpu/mips/broadcom/avx/68kio.fth
cpu/mips/broadcom/avx/bcuart.fth
cpu/mips/broadcom/avx/boot.fth
cpu/mips/broadcom/avx/broadcom.fth
cpu/mips/broadcom/avx/devalias.fth
cpu/mips/broadcom/avx/devices.fth
cpu/mips/broadcom/avx/excption.fth
cpu/mips/broadcom/avx/flash.fth
cpu/mips/broadcom/avx/fw.bth
cpu/mips/broadcom/avx/initbc.fth
cpu/mips/broadcom/avx/initcom1.fth
cpu/mips/broadcom/avx/intr.fth
cpu/mips/broadcom/avx/mappci.fth
cpu/mips/broadcom/avx/ofwfind.fth
cpu/mips/broadcom/avx/pcicfg.fth
cpu/mips/broadcom/avx/pcinode.fth
cpu/mips/broadcom/avx/physaddr.fth
cpu/mips/broadcom/avx/report.fth
cpu/mips/broadcom/avx/reset.bth
cpu/mips/broadcom/avx/resetjmp.bth
cpu/mips/broadcom/avx/rom.bth
cpu/mips/broadcom/avx/romraw.bth
cpu/mips/broadcom/avx/rootnode.fth
cpu/mips/broadcom/avx/start.bth
cpu/mips/broadcom/avx/test.bth
cpu/mips/broadcom/avx/virtaddr.fth
cpu/mips/broadcom/avx/vpd.fth
cpu/mips/build/build
cpu/mips/builder.bth
cpu/mips/builton.bth
cpu/mips/cache.fth
cpu/mips/call.fth
cpu/mips/catchexc.fth
cpu/mips/ccalls.fth
cpu/mips/centry.fth
cpu/mips/cobalt/devalias.fth
cpu/mips/cobalt/devices.fth
cpu/mips/cobalt/diaguart.fth
cpu/mips/cobalt/dropins.bth
cpu/mips/cobalt/fixexc.fth
cpu/mips/cobalt/flashpkg.fth
cpu/mips/cobalt/fw.bth
cpu/mips/cobalt/mappci.fth
cpu/mips/cobalt/pciinit.fth
cpu/mips/cobalt/probemem.fth
cpu/mips/cobalt/reboot.fth
cpu/mips/cobalt/regacc.fth
cpu/mips/cobalt/reports.fth
cpu/mips/code.fth
cpu/mips/cpubpsup.fth
cpu/mips/cpustate.fth
cpu/mips/ctrace.fth
cpu/mips/debugm.fth
cpu/mips/decompm.fth
cpu/mips/disassem.fth
cpu/mips/field.fth
cpu/mips/filecode.fth
cpu/mips/finish.fth
cpu/mips/fixvoc.fth
cpu/mips/float.fth
cpu/mips/forthint.fth
cpu/mips/ftrace.fth
cpu/mips/getms.fth
cpu/mips/initpgm.fth
cpu/mips/installation.html
cpu/mips/intctl.fth
cpu/mips/irq.fth
cpu/mips/kernboot.fth
cpu/mips/kerncode.fth
cpu/mips/kernel.bth
cpu/mips/ksegaddr.fth
cpu/mips/lmove.fth
cpu/mips/loadmach.fth
cpu/mips/machdep.fth
cpu/mips/makeinflater.notes
cpu/mips/metainit.fth
cpu/mips/metarel.fth
cpu/mips/objsup.fth
cpu/mips/pause.fth
cpu/mips/physaddr.fth
cpu/mips/probemem.fth
cpu/mips/r4000cp0.fth
cpu/mips/regacc.fth
cpu/mips/register.fth
cpu/mips/resetjmp.bth
cpu/mips/rootnode.fth
cpu/mips/savefort.fth
cpu/mips/savemeta.fth
cpu/mips/startup.html
cpu/mips/sys.fth
cpu/mips/target.fth
cpu/mips/testasm.fth
cpu/mips/tickint.fth
cpu/mips/tools.bth
cpu/mips/traps.fth
cpu/mips/unalign.fth
cpu/mips/virtaddr.fth
cpu/mips/zipcrc.fth
Log:
MIPS - checkin leaf files for MIPS
Added: cpu/mips/Linux/makefile
===================================================================
--- cpu/mips/Linux/makefile (rev 0)
+++ cpu/mips/Linux/makefile 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,38 @@
+# Wrapper makefile for Unix: FreeBSD, Linux, etc.
+# Copyright 1997 FirmWorks. All rights reserved.
+#
+CC = mipsel-linux-gnu-gcc-4.3
+
+CFLAGS = -O -g -D__linux__ -DMIPS -DHOSTMIPS
+LFLAGS = -Xlinker -static -static-libgcc
+
+WRDIR = ${BP}/forth/wrapper
+ZIPDIR = ${WRDIR}/zip
+
+ZIPOBJS = zipmem.o deflate.o trees.o bits.o util.o inflate.o
+
+OBJS = wrapper.o logger.o ${ZIPOBJS}
+
+all: forth
+
+wrapper.o: ${BP}/forth/wrapper/wrapper.c
+ ${CC} ${CFLAGS} -c ${BP}/forth/wrapper/wrapper.c
+
+%.o: ${WRDIR}/%.c
+ ${CC} -c ${CFLAGS} $< -o $@
+
+%.o: ${ZIPDIR}/%.c
+ ${CC} -c ${CFLAGS} -I${ZIPDIR} $< -o $@
+
+forth: ${OBJS}
+ ${CC} $(LFLAGS) -o $@ ${OBJS}
+
+clean:
+ @rm -f forth *.o
+
+install: forth
+ cp forth ${BP}/bin/mips/`uname|tr A-Z a-z`/forth
+ cp forth ${BP}/bin/mips/`uname|tr A-Z a-z`/mipsfth
+
+dist:
+ (cd ${BP}; zip /tmp/wrapper.zip os/unix/mips/makefile ${SRCS})
Added: cpu/mips/QEMU/forth
===================================================================
--- cpu/mips/QEMU/forth (rev 0)
+++ cpu/mips/QEMU/forth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,2 @@
+#!/bin/sh
+qemu-mipsel ../Linux/mipsforth $@
Property changes on: cpu/mips/QEMU/forth
___________________________________________________________________
Added: svn:executable
+ *
Added: cpu/mips/QEMU/mipsfth
===================================================================
--- cpu/mips/QEMU/mipsfth (rev 0)
+++ cpu/mips/QEMU/mipsfth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,2 @@
+#!/bin/sh
+qemu-mipsel ../Linux/mipsforth $@
Property changes on: cpu/mips/QEMU/mipsfth
___________________________________________________________________
Added: svn:executable
+ *
Added: cpu/mips/argv.fth
===================================================================
--- cpu/mips/argv.fth (rev 0)
+++ cpu/mips/argv.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,105 @@
+\ See license at end of file
+purpose: Split a command string into an argv array
+
+\ argc,argv ( command$ name$ -- argv argc )
+\ Places a pointer to a null-terminated representation of the "adr len"
+\ string "name$" in the first element of a pointer array whose base
+\ address is "argv". Then parses the "adr len" string "command$" into
+\ constituent substrings, storing pointers to the null-terminated
+\ substrings in subsequent elements of the "argv" array.
+\ Returns the number of pointers in the array, including the pointer to
+\ name$, as "argc". An extra null pointer (i.e. the number 0) is stored
+\ at the end of the array but is not included in the "argc" count.
+\
+\ The substrings are delimited by white space, except that
+\ a) If a backslash is encountered, it "quotes" the next character;
+\ if that character is whitespace, it does not delimit the
+\ substring. To embed the \ character itself, double it.
+\ b) If the first character of a substring is either " or ', the
+\ substring continues until the next non-quoted occurence of
+\ that quote character. (A " character can be embedded within
+\ a quoted string by preceding it with \ .)
+\ These quoting rules are intended to be similar to those of Unix shells.
+
+: skipwhite ( adr len -- adr' len' )
+ begin dup while
+ over c@ bl > if exit then
+ 1 /string
+ repeat
+;
+
+: append-char ( ptr adr len char -- ptr' adr len )
+ 3 roll tuck c! 1+ -rot
+;
+
+: collect-arg ( ptr adr len delim -- ptr' adr' len' )
+ >r
+ begin dup while ( ptr adr len )
+ over c@ ( ptr adr len char )
+
+ \ Exit when delimiter found
+ \ If delim is < 0, then parse nonwhite characters. Otherwise parse
+ \ with a specific delimiter.
+ dup r@ dup 0< if drop bl <= else = then if
+ r> 2drop 1 /string 0 append-char exit
+ then
+
+ dup [char] \ = if ( ptr adr len char )
+ drop ( ptr adr len )
+ 1 /string ( ptr adr' len' )
+ dup 0= if 0 append-char r> drop exit then
+ over c@ ( ptr adr len char )
+ then ( ptr adr len char )
+ append-char 1 /string ( ptr' adr' len' )
+ repeat
+ r> drop
+;
+
+: add-arg ( ptr adr len -- ptr' adr' len' )
+ dup 0= if exit then
+
+ 2 pick , ( ptr adr len )
+ over c@ dup [char] " =
+ swap [char] ' = or if ( ptr adr len )
+ 1 /string over 1- c@ collect-arg ( ptr adr len )
+ else
+ -1 collect-arg
+ then
+;
+
+: argv,argc ( command$ name$ -- argv argc )
+ align here >r ( command$ name$ ) ( r: argv )
+ $cstr , ( command$ )
+ dup alloc-mem -rot ( ptr command$ )
+ begin dup while ( ptr command$ )
+ skipwhite ( ptr command$' )
+ add-arg ( ptr' command$' )
+ repeat ( ptr command$ )
+ 3drop ( ) ( r: argv )
+ r> here over - /n / ( argv argc )
+ 0 ,
+;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/asmtools.fth
===================================================================
--- cpu/mips/asmtools.fth (rev 0)
+++ cpu/mips/asmtools.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,108 @@
+purpose: Tools for creating disembodied assembly code sequences
+\ See license at end of file
+
+[ifndef] set-transize
+fload ${BP}/forth/lib/transien.fth
+true is suppress-transient? \ Disable transient definitions for now
+[then]
+
+\needs suppress-headerless? fload ${BP}/fm/lib/headless.fth
+
+[ifndef] mips-assembler
+fload ${BP}/cpu/mips/assem.fth
+fload ${BP}/cpu/mips/code.fth
+fload ${BP}/forth/lib/loclabel.fth
+[then]
+
+\ The default is to assemble in the native endian-ness of the host system
+: assemble-little-endian ( -- )
+ [ also mips-assembler ]
+ ['] le-l! is asm!
+ ['] le-l@ is asm@
+ [ previous ]
+;
+: assemble-big-endian ( -- )
+ [ also mips-assembler ]
+ ['] be-l! is asm!
+ ['] be-l@ is asm@
+ [ previous ]
+;
+
+also forth definitions
+: c$, ( adr len -- )
+ 1+ here swap note-string dup allot move 4 (align)
+;
+previous definitions
+
+false value transient-labels?
+0 value asm-origin
+0 value asm-base
+: pad-to ( n -- )
+ begin dup here asm-base - asm-origin + u> while 0 c, repeat drop
+;
+: align-to ( boundary -- )
+ here asm-base - swap round-up pad-to
+;
+
+[ifndef] enable-transient?
+: enable-transient ( -- )
+ suppress-transient? if
+ unused 4 / d# 1000 set-transize
+ false is suppress-transient?
+ false is suppress-headerless?
+ then
+;
+[then]
+enable-transient
+
+: tconstant ( value "name" -- )
+ transient? 0= dup >r if transient then
+ constant
+ r> if resident then
+;
+: label ( "name" -- )
+ transient-labels? if
+ here tconstant
+ [ also mips-assembler ] init-labels [ previous ] !csp entercode
+ else
+ label
+ then
+;
+
+: set-asm-origin ( -- )
+ here to asm-base
+ 0 to asm-origin
+;
+
+0 0 2value old-asms
+: start-assembling ( -- )
+ set-asm-origin
+ true to transient-labels?
+;
+: end-assembling ( -- )
+ false to transient-labels?
+;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/assem.fth
===================================================================
--- cpu/mips/assem.fth (rev 0)
+++ cpu/mips/assem.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,575 @@
+purpose: Forth Assembler for MIPS
+\ See license at end of file
+
+: set-relocation-bit ;
+
+\ requires case.f
+\ alias l0< 0<
+\ alias l<> <>
+
+\ requires string-array.f
+
+vocabulary mips-assembler
+also mips-assembler definitions
+
+alias lor or \ Because "or" gets redefined in the assembler
+
+defer here \ For switching between resident and meta assembling
+defer asm-allot \ For switching between resident and meta assembling
+defer asm@ \ For switching between resident and meta assembling
+defer asm! \ For switching between resident and meta assembling
+
+\ Install as a resident assembler
+: resident ( -- )
+ [ forth ] ['] here [ mips-assembler ] is here
+ [ forth ] ['] allot [ mips-assembler ] is asm-allot
+ [ forth ] ['] @ [ mips-assembler ] is asm@
+ [ forth ] ['] n! [ mips-assembler ] is asm!
+;
+resident
+
+decimal
+
+\ This is used for delay slot optimization. This variable is set
+\ to the starting address of each code sequence, to the address following
+\ the delay slot of each branch instruction, and to the target address
+\ of forward branches. If "next" notices that the value in delay-barrier
+\ is the same as "here", it won't move the previous instruction into
+\ its next's delay slot.
+nuser delay-barrier
+: block-delay ( -- ) here la1+ delay-barrier ! ;
+: block-here ( -- ) here delay-barrier ! ;
+
+h# .ffff constant immedmask
+h# .7fff constant maximmed
+h# ffff.8000 constant minimmed
+h# 1f constant regmask
+h# 1000.0000 constant regmagic
+
+\ Bias register constants outside the range of signed immediate values
+: reg ( n -- ) regmagic + ;
+: register \ name ( n -- )
+ create , does> @ reg
+;
+
+\ Register names; these just return constants.
+
+ 0 register $0 1 register $1 2 register $2 3 register $3
+ 4 register $4 5 register $5 6 register $6 7 register $7
+ 8 register $8 9 register $9 10 register $10 11 register $11
+12 register $12 13 register $13 14 register $14 15 register $15
+16 register $16 17 register $17 18 register $18 19 register $19
+20 register $20 21 register $21 22 register $22 23 register $23
+24 register $24 25 register $25 26 register $26 27 register $27
+28 register $28 29 register $29 30 register $30 31 register $31
+
+alias $at $1
+alias $kt0 $26
+alias $kt1 $27
+alias $gp $28
+alias $sp $29
+alias $a0 $4
+alias $a1 $5
+alias $a2 $6
+alias $a3 $7
+alias ra $31
+alias s0 $16
+alias s1 $17
+alias s2 $18
+alias s3 $19
+alias s4 $20
+alias s5 $21
+alias s6 $22
+alias s7 $23
+alias s8 $30
+alias t0 $8
+alias t1 $9
+alias t2 $10
+alias t3 $11
+alias t4 $12
+alias t5 $13
+alias t6 $14
+alias t7 $15
+alias t8 $24
+alias t9 $25
+alias k0 $26
+alias k1 $27
+alias v0 $2
+alias v1 $3
+
+32 register $f0 33 register $f1 34 register $f2 35 register $f3
+36 register $f4 37 register $f5 38 register $f6 39 register $f7
+40 register $f8 41 register $f9 42 register $f10 43 register $f11
+44 register $f12 45 register $f13 46 register $f14 47 register $f15
+48 register $f16 49 register $f17 50 register $f18 51 register $f19
+52 register $f20 53 register $f21 54 register $f22 55 register $f23
+56 register $f24 57 register $f25 58 register $f26 59 register $f27
+60 register $f28 61 register $f29 62 register $f30 63 register $f31
+
+\ Test operand values to see what kind of operand they are.
+
+: 16-bit? ( n -- flag ) minimmed maximmed between ;
+
+: ?freg ( r -- r )
+ dup $f0 $f30 between 0= abort" Floating point register required"
+;
+
+: ?ireg ( r -- r )
+ dup $0 $31 between 0= abort" Integer register required"
+;
+
+\ Words to encode operands into their appropriate fields
+
+: setbits ( opcode -- ) here asm! /l asm-allot ;
+: opaddr ( -- addr ) here /l - ;
+: addbits ( bits -- ) opaddr asm@ + opaddr asm! ;
+: >regfld ( reg shift -- bits ) swap regmask land swap lshift ;
+: regset ( reg shift -- ) >regfld addbits ;
+: rs ( rs -- ) 21 regset ;
+: rd ( rd -- ) 11 regset ;
+: rt ( rt -- ) 16 regset ;
+: sa ( re -- ) 6 regset ;
+
+: uimmed ( value -- ) immedmask land addbits ;
+: immed ( value -- )
+ dup 16-bit? 0= abort" Immediate operand doesn't fit in 16 bits"
+ uimmed
+;
+
+\ Set the opcode field
+: set-op ( n -- ) d# 26 lshift setbits ;
+
+: special ( n -- ) 0 set-op addbits ;
+: regimm ( n -- ) 1 set-op rt ;
+: special2 ( n -- ) 34 set-op addbits ;
+
+\ Define the various opcodes according to their formats.
+octal
+
+: ld: ( opcode -- ) \ Load instructions
+ create , does> ( rs imm rt opc-adr -- ) @ set-op rt immed rs
+;
+32 ld: ldl 33 ld: ldr
+40 ld: lb 41 ld: lh 42 ld: lwl 43 ld: lw
+44 ld: lbu 45 ld: lhu 46 ld: lwr 47 ld: lwu
+57 ld: cache
+60 ld: ll 61 ld: lwc1 62 ld: lwc2 63 ld: pref \ pref is rs imm hint
+64 ld: lld 65 ld: ldc1 66 ld: ldc2 67 ld: ld
+
+: st: ( opcode -- ) \ Store instructions
+ create , does> ( rt rs imm opc-adr -- ) @ set-op immed rs rt
+;
+50 st: sb 51 st: sh 52 st: swl 53 st: sw 54 st: sdl 55 st: sdr 56 st: swr
+70 st: sc 71 st: swc1 72 st: swc2 74 st: scd 75 st: sdc1
+76 st: sdc2 77 st: sd
+
+: 2op: ( opcode -- ) \ Two-operand instructions (add, sub, etc)
+ create , does> ( rs rt rd opc-adr -- ) @ special rd rt rs
+;
+40 2op: add 41 2op: addu 42 2op: sub 43 2op: subu
+44 2op: and 45 2op: or 46 2op: xor 47 2op: nor
+52 2op: slt 53 2op: sltu
+54 2op: dadd 55 2op: daddu 56 2op: dsub 57 2op: dsubu
+
+: lui ( imm rt -- )
+ o# 17 set-op rt
+ dup h# ffff > abort" Immediate operand doesn't fit in 16 bits"
+ addbits
+;
+: sethi ( imm rt -- ) swap d# 16 >> swap lui ;
+
+: li ( n dst -- )
+ swap dup h# ffff land -rot ( nlow dst n )
+ dup 0 h# ffff between if ( nlow dst n )
+ drop 15 set-op rt $0 rs uimmed \ dst nlow dst ori
+ exit
+ then ( nlow dst n )
+
+ dup h# ffff.8000 -1 between if ( nlow dst n )
+ drop 11 set-op rt $0 rs uimmed \ $0 nlow dst addiu
+ exit
+ then ( nlow dst n )
+
+ \ We have to use two instructions unless the low 16 bits are 0
+ d# 16 >> over lui ( nlow dst )
+ over if
+ 15 set-op dup rt rs uimmed \ dst nlow dst ori
+ else
+ 2drop
+ then
+;
+
+alias set li
+
+\ XXX we need to handle the case where immed is too big for 16 bits,
+\ loading $at in that case.
+: ?set-immed ( rs imm rt op -- rs imm rt op )
+ 2 pick 16-bit? if exit then ( rs imm rt op )
+ rot $at li ( rs rt op )
+ 30 + special rd $at rt rs
+ r> drop
+;
+: ?set-uimmed ( rs imm rt op -- rs imm rt op )
+ 2 pick h# 10000 u< if exit then ( rs imm rt op )
+ rot $at li ( rs rt op )
+ 30 + special rd $at rt rs
+ r> drop
+;
+
+: imm: ( opcode -- ) \ Two-operand immediate instructions (addi, etc)
+ create , does> ( rs imm rt opc-adr -- ) @ ?set-immed set-op rt uimmed rs
+;
+10 imm: addi 11 imm: addiu 12 imm: slti 13 imm: sltiu
+30 imm: daddi 31 imm: daddiu
+
+: uimm: ( opcode -- ) \ Two-operand immediate instructions (addi, etc)
+ create , does> ( rs imm rt opc-adr -- ) @ ?set-uimmed set-op rt uimmed rs
+;
+14 uimm: andi 15 uimm: ori 16 uimm: xori
+
+: jmpi: ( opcode -- ) \ Jump absolute
+ create , does> ( target opc-adr -- ) @ set-op
+ dup h# fc00.0000 land here h# fc00.0000 land <>
+ abort" Jump target outside of current 28-bit bank"
+ 2 >> h# 3ff.ffff land addbits
+ block-delay
+;
+02 jmpi: j 03 jmpi: jal
+
+: jr ( rs -- ) o# 10 special rs block-delay ;
+: jalr ( rs rd -- ) o# 11 special rd rs block-delay ;
+
+: shift: ( opcode -- ) \ Shift instructions
+ create , does> ( rt sa rd opc-adr -- ) @ special rd sa rt
+;
+00 shift: sll 02 shift: srl 03 shift: sra
+70 shift: dsll 72 shift: dsrl 73 shift: dsra
+74 shift: dsll32 76 shift: dsrl32 77 shift: dsra32
+: shiftv: ( opcode -- ) \ Shift instructions
+ create , does> ( rt rs rd opc-adr -- ) @ special rd rs rt
+;
+04 shiftv: sllv 06 shiftv: srlv 07 shiftv: srav
+24 shiftv: dsllv 26 shiftv: dsrlv 27 shiftv: dsrav
+
+: mul: ( opcode -- ) \ Two-operand instructions with implicit destination
+ create , does> ( rs rt opc-adr -- ) @ special rt rs
+;
+31 mul: mult 31 mul: multu 32 mul: div 33 mul: divu
+34 mul: dmult 35 mul: dmultu 36 mul: ddiv 37 mul: ddivu
+60 mul: tge 61 mul: tgeu 62 mul: tlt 63 mul: tltu
+64 mul: teq 66 mul: tne
+
+: fhilo: ( opcode -- ) \ HI and LO access
+ create , does> ( rd opc-adr -- ) @ special rd
+;
+: thilo: ( opcode -- ) \ HI and LO access
+ create , does> ( rd opc-adr -- ) @ special rs
+;
+20 fhilo: mfhi 21 thilo: mthi 22 fhilo: mflo 23 thilo: mtlo
+
+: dset ( d reg -- )
+ >r r@ set r@ 0 r@ dsll32 ( d.low )
+ dup 0< swap ( negative? d.low )
+ $at set ( negative? )
+\ [ also forth ] if [ previous ]
+if
+ $at 0 $at dsll32 $at 0 $at dsrl32 \ Zero high bits
+then
+\ [ also forth ] then [ previous ]
+ $at r@ r> daddu
+;
+
+
+: >br-offset ( target-adr br-adr -- offset )
+ 4 + - ( byte-offset )
+ 2 >>a ( word-offset )
+ dup 16-bit? 0= abort" Branch offset doesn't fit in 16 bits"
+ immedmask land
+;
+: br-offset ( adr -- )
+ opaddr >br-offset addbits
+ block-delay
+;
+: br2: ( opcode -- ) \ 2-operand conditional branches
+ create , does> ( adr rs rt opc-adr -- ) @ set-op rt rs br-offset
+;
+04 br2: beq 05 br2: bne 24 br2: beql 25 br2: bnel
+
+: br1: ( opcode -- ) \ 1-operand conditional branches
+ create , does> ( adr rs opc-adr -- ) @ set-op rs br-offset
+;
+06 br1: blez 07 br1: bgtz 26 br1: blezl 27 br1: bgtzl
+
+: brx: ( opcode -- ) \ 1-operand conditional branches (extensions)
+ create , does> ( adr rs opc-adr -- ) @ regimm rs br-offset
+;
+00 brx: bltz 01 brx: bgez 02 brx: bltzl 03 brx: bgezl
+20 brx: bltzal 21 brx: bgezal 22 brx: bltzall 23 brx: bgezall
+
+: bal ( adr -- ) $0 bgezal ;
+
+: cop0 ( -- ) o# 20 set-op ;
+: cop1 ( -- ) o# 21 set-op ;
+
+: brf0: ( adr opcode -- ) \ Floating-point branches
+ create , does> @ cop0 d# 16 << addbits br-offset
+;
+: brf1: ( adr opcode -- ) \ Floating-point branches
+ create , does> @ cop1 d# 16 << addbits br-offset
+;
+400 brf0: bc0f 402 brf0: bc0fl 401 brf0: bc0t 403 brf0: bc0tl
+400 brf1: bc1f 402 brf1: bc1fl 401 brf1: bc1t 403 brf1: bc1tl
+
+: trapi: ( opcode -- ) \ Trap immediate
+ create , does> ( rs imm opc-adr -- ) @ regimm immed rs block-here
+;
+10 trapi: tgei 11 trapi: tgeiu 12 trapi: tlti
+13 trapi: tltiu 14 trapi: teqi 16 trapi: tnei
+
+: syscall ( -- ) 14 special block-here ;
+: break ( -- ) 15 special block-here ;
+: sync ( -- ) 17 special block-here ;
+
+: dbreak ( -- ) 77 special2 block-here ;
+: dret ( -- ) 76 special2 block-here ;
+: mtdr ( dbreg rt -- ) 75 special2 4 rs rt rd ;
+: mfdr ( dbreg rt -- ) 75 special2 0 rs rt rd ;
+
+d# 16 constant single
+d# 17 constant double
+d# 19 constant fixed
+double value float-mode
+
+: set-cop ( apf -- ) @ cop1 addbits float-mode rs ;
+
+: fr2: ( opcode -- ) \ 2-operand floating point computation instructions
+ create ,
+ does> ( fs ft fd -- ) set-cop ( fs ft fd ) sa rt rd
+;
+00 fr2: addf 01 fr2: subf 02 fr2: mulf 03 fr2: divf
+
+: fr: ( opcode -- ) \ 1-operand floating point computation instructions
+ create ,
+ does> ( fs fd -- ) set-cop ( fs fd ) sa 0 rt rd
+;
+
+04 fr: sqrt 05 fr: abs 06 fr: movf 07 fr: negf
+14 fr: round.w 15 fr: trunc.w 16 fr: ceil.w 17 fr: floor.w
+40 fr: cvt.s 41 fr: cvt.d
+44 fr: cvt.w
+60 fr: cxx
+
+: fc: ( opcode -- ) \ floating point comparison instructions
+ create ,
+ does> ( ft fs -- ) set-cop ( ft fs ) 0 sa rd rt
+;
+
+
+: fc1: ( opcode -- )
+ create , does> ( fs rt -- ) @ cop1 rs rt rd
+;
+0 fc1: mfc1 2 fc1: cfc1 4 fc1: mtc1 6 fc1: ctc1
+
+: mfc0 ( cpreg rt -- ) cop0 0 rs rt rd ;
+: mtc0 ( cpreg rt -- ) cop0 4 rs rt rd ;
+: dmfc0 ( cpreg rt -- ) cop0 1 rs rt rd ;
+: dmtc0 ( cpreg rt -- ) cop0 5 rs rt rd ;
+: tlbp ( -- ) cop0 h# 0200.0008 addbits ;
+: tlbr ( -- ) cop0 h# 0200.0001 addbits ;
+: tlbwi ( -- ) cop0 h# 0200.0002 addbits ;
+: tlbwr ( -- ) cop0 h# 0200.0006 addbits ;
+: eret ( -- ) cop0 h# 0200.0018 addbits block-here ;
+
+: fmt: ( format-code -- )
+ \ Replace FMT field with correct format
+ create , does> opaddr asm@ h# 03e0.0000 invert land opaddr asm! @ rs
+;
+d# 16 fmt: .s d# 17 fmt: .d d# 20 fmt: .w
+
+hex
+
+\ Standard assembler macros
+: nop $0 0 $0 sll ;
+
+: inhibit-delay nop ;
+
+: la ( n dst -- ) swap set-relocation-bit swap li ;
+\ : ulh
+\ : ulhu
+\ : ulw
+\ : ush
+\ : usw
+\ : abs
+\ : neg
+\ : negu
+\ : not
+\ : div
+\ : divu
+\ : mul
+\ : mulo
+\ : mulou
+\ : rem
+\ : remu
+\ : rol
+\ : seq
+\ : sle
+\ : sleu
+\ : sgt
+\ : sgtu
+\ : sge
+\ : sgeu
+\ : sne
+\ : bgt ( adr imm src -- )
+\ : bge ( adr imm src -- )
+\ : bgeu ( adr imm src -- )
+\ : bgtu ( adr imm src -- )
+\ : blt ( adr imm src -- )
+\ : ble ( adr imm src -- )
+\ : bleu ( adr imm src -- )
+\ : bltu ( adr imm src -- )
+\ : bal ( adr -- )
+\ : move ( src dst -- )
+
+\ XXX edited to here
+
+: asm-align ( boundary -- )
+ 1- begin dup here land while nop repeat
+;
+
+\ Control transfer instructions
+
+hex
+: -cond ( condition -- not-condition )
+ dup h# 1000.0000 land if h# 0400.0000 else h# 0001.0000 then
+ [ forth ] xor [ mips-assembler ]
+;
+
+: brif ( adr cond -- ) setbits br-offset ;
+
+\ 6 branch: brfif ( address reg condition -- )
+\ 7 branch: brcif ( address reg condition -- )
+: bra ( adr -- ) $0 bgez ;
+: branch! ( target-adr branch-adr -- )
+ tuck >br-offset h# 1000.0000 + swap asm!
+;
+: put-branch ( target-adr branch-adr -- ) branch! ;
+
+
+\ Structured conditionals
+
+: <mark ( -- <mark ) here ;
+: >mark ( -- >mark ) here ;
+: >resolve ( >mark -- )
+ here over >br-offset over asm@ + swap asm!
+ block-here
+;
+\ >+resolve is used when the resolution follows a branch, so the delay slot
+\ must be skipped (block-delay is not needed, because the back branch did it)
+: >+resolve ( >mark -- )
+ here la1+ over >br-offset over asm@ + swap asm!
+;
+: <resolve ( -- ) ;
+
+: but ( mark1 mark2 -- mark2 mark1 ) swap ;
+: yet ( mark -- mark mark ) dup ;
+
+: ahead ( -- >mark ) >mark here 4 + bra ;
+: if ( cond -- >mark ) >mark here 4 + rot -cond brif ;
+: then ( >mark -- ) >resolve ;
+: else ( >mark -- >mark1 ) ahead but >+resolve ;
+: begin ( -- <mark ) <mark ;
+: until ( <mark cond -- ) -cond brif ;
+: again ( <mark -- ) bra ;
+: repeat ( <mark >mark -- ) again >+resolve ;
+: while ( <mark cond -- <mark >mark ) if but ;
+
+\ Define these last to delay overloading of the forth versions
+
+hex
+
+: +rs ( rs template -- template' ) swap d# 21 >regfld lor ;
+: +rt ( rs template -- template' ) swap d# 16 >regfld lor ;
+
+: = ( rs rt -- cond ) 1000.0000 +rt +rs ;
+: <> ( rs rt -- cond ) 1400.0000 +rt +rs ;
+
+: 0<= ( rs -- cond ) 1800.0000 +rs ;
+: 0> ( rs -- cond ) 1c00.0000 +rs ;
+: 0< ( rs -- cond ) 0400.0000 +rs ;
+: 0>= ( rs -- cond ) 0401.0000 +rs ;
+
+
+\ \ Floating-point operations; these aren't needed for the kernel
+\
+\ : set-opf ( opcode-adr -- ) 34 2 set-op @ 5 l<< addbits ;
+\ : ffop \ name ( opcode -- )
+\ create ,
+\ does> ( frs frd opc-adr -- ) set-opf ?freg rd ?freg rs2
+\ ;
+\ 0c9 ffop fstod 0cd ffop fstox
+\ 0c6 ffop fdtos 0ce ffop fdtox
+\ 0c7 ffop fxtos 0cb ffop fxtod
+\
+\ 001 ffop fmovs 005 ffop fnegs 009 ffop fabss
+\ 029 ffop fsqrts 02a ffop fsqrtd 02b ffop fsqrtx
+\
+\ 0c4 ffop fitos 0c8 ffop fitod 0cc ffop fitox
+\
+\ 0c1 ffop fstoir 0c2 ffop fdtoir 0c3 ffop fxtoir
+\ 0d1 ffop fstoi 0d2 ffop fdtoi 0d3 ffop fxtoi
+\
+\ : f2op \ name ( opcode -- )
+\ create ,
+\ does> ( frs1 frs2 frd opc-adr -- )
+\ set-opf ?freg rd ?freg rs2 ?freg rs
+\ ;
+\ 041 f2op fadds 042 f2op faddd 043 f2op faddx
+\ 045 f2op fsubs 046 f2op fsubd 047 f2op fsubx
+\ 049 f2op fmuls 04a f2op fmuld 04b f2op fmulx
+\ 04d f2op fdivs 04e f2op fdivd 04f f2op fdivx
+\
+\ : fcmpop \ name ( opcode -- )
+\ create ,
+\ does> ( frs1 frs2 opc-adr -- )
+\ set-opf 1 td 19 << addbits ?freg rs2 ?freg rs
+\ ;
+\ 051 fcmpop fcmps 052 fcmpop fcmpd 053 fcmpop fcmpx
+\ 055 fcmpop fcmpes 056 fcmpop fcmped 057 fcmpop fcmpex
+
+previous definitions
+
+headers
+
+: fix-immed16 ( n adr -- )
+ tuck l@ h# ffff.0000 and or swap l!
+;
+
+: fix-set32 ( n adr -- )
+ >r lwsplit
+ r@ fix-immed16
+ r> /l + fix-immed16
+;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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+\ LICENSE_END
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+<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+ <title>MIPS Assembler</title>
+
+ <meta http-equiv="content-type"
+ content="text/html; charset=ISO-8859-1">
+
+ <meta name="author" content="Mitch Bradley">
+</head>
+ <body>
+
+<h2>MIPS Assembler</h2>
+<br>
+<a href="#Introduction">Introduction</a><br>
+<a href="#Entering_Assembler_Mode">Entering Assembler Mode</a><br>
+<a href="#Basic_Syntax">Basic Syntax</a><br>
+<a href="#Register_names">Register Names</a><br>
+<a href="#Opcodes">Opcodes</a><br>
+<a href="#Structured_Conditionals">Structured Conditionals</a><br>
+<a href="#Local_Labels">Local Labels</a><br>
+<a href="#Directives">Directives</a>
+<h3><a name="Introduction"></a>Introduction</h3>
+Open Firmware includes an assembler for the MIPS instruction set. The
+same assembler is present in both the development compiler (builder) and
+the target system.<br>
+ <br>
+ The Open Firmware assembler is quite different from conventional MIPS assemblers.<br>
+
+<ul>
+ <li>Its syntax is postfix - the operands are specified before the opcode,
+which makes it much easier to support assembler macros</li>
+ <li>It supports the opcodes that are actually present in the MIPS hardware
+instruction set, plus a select few pseudo-ops that generate multiple instructions,
+instead of synthesizing a whole suite of "instructions" that are not really
+in the instruction set.</li>
+ <li>It supports structured conditional directives like <b>if .. else ..
+then</b> and <b>begin .. until</b> so you rarely need to invent labels for
+simple conditionals and loops.</li>
+ <li>It does not reorder the instruction stream to fill delay slots, nor
+does it attempt to optimize the instruction stream for any particular MIPS
+implementation's pipeline characteristics. What you write is what you get.</li>
+ <li>It does not generate or process standard object file formats containing
+linkage information. Instead, it is intended to be used either for incremental
+compilation of short "code words" that operate within the framework of Open
+Firmware's Forth interpreter or for self-contained "dropin modules" that execute
+during the Open Firmware early startup sequence (typically to do things like
+configuring the memory controller).</li>
+ <li>It has only limited support for the floating point (coprocessor) instruction
+set. The basic floating point instructions are supported, but many of the
+elaborations are not.<br>
+ </li>
+
+</ul>
+ The net result is that the Open Firmware MIPS assembler is much smaller
+that conventional assemblers. The binary code is approximately 12K bytes,
+compared to over 2Mbytes for some versions of gas . It is small enough to
+leave the assembler resident in the target system, thus making it possible
+to create short assembly language test sequences at any time, without needing
+access to a development host.
+<h3><a name="Entering_Assembler_Mode"></a>Entering Assembler Mode</h3>
+There are several different ways to enter assembler mode, depending on how
+the assembled code will be used.<br>
+<table cellpadding="2" cellspacing="2" border="1">
+ <tbody>
+ <tr>
+ <td valign="top"><b>code</b> <i>newname</i><br>
+ <i> assembly code<br>
+ </i><i> ...</i><br>
+ <b>c;</b><br>
+ </td>
+ <td valign="top"><b>code</b> creates (i.e. incrementally adds to the
+resident Forth dictionary) a new Forth word named <i>newname</i> and enters
+assembler mode so you can implement the new word in assembly language. <b>c;</b>
+assembles the appropriate instruction sequence to return control to the Forth
+execution engine and exits from assembler mode. You can then execute the
+new word by typing its name, as with any other Forth word. <br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"><b>label</b> <i>newname</i><br>
+ <i>assembly code</i><br>
+ ...<br>
+ <b>end-code</b><br>
+ </td>
+ <td valign="top"><b>label</b> creates a new Forth word named <i>newname</i>
+and enters assembler mode so you can assemble some machine instructions that
+will be used within the context of the current Forth dictionary, but that
+will not be called directly as a Forth word. <b>end-code</b> exits from assembler
+mode. Later execution of <i>newname</i> pushes on the Forth stack the beginning
+address of that sequence of machine instructions. <b>label</b> is typically
+used to create instruction sequences, for example interrupt handlers, that
+will be executed in a context other than from the Forth virtual machine.<br>
+ <br>
+It is also possible to mix the constructs: <b>code</b> <i>newname</i>
+... <b>end-code</b> creates a Forth word that can be executed by typing its
+name, but that will not return to Forth. <b>label</b> <i>newname</i>
+... <b>c;</b> creates a code sequence that could be entered from elsewhere
+(e.g. from an exception hander), but which would enter Forth when it was
+done.<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"><b>start-assembling</b><br>
+ <i>assembly code</i><br>
+ ...<br>
+ <b>end-assembling</b><br>
+ </td>
+ <td valign="top"><b>start-assembling .. end-assembling</b> is
+uses to create a block of code that will later be written out to a file (often
+in the form of a "dropin module") for use in a target system environment.
+See <a href="#Directives">Directives.</a><br>
+ </td>
+ </tr>
+ </tbody>
+</table>
+<h3><a name="Basic_Syntax"></a>Basic Syntax</h3>
+The assembler is really just a Forth vocabulary containing Forth words that
+put MIPS machine instructions in memory when they are executed.<br>
+The basic syntax of the Open Firmware MIPS assembler is postfix, just like
+ordinary Forth code. You first execute Forth words to push items on
+the stack - those items typically identify registers, numbers, or addresses,
+i.e. the operands. Then you execute a word that names the opcode, which assembles
+the machine instruction corresponding to that opcode with those operands.<br>
+ <br>
+ The order of the operands is generally source first, then destination.<br>
+ <br>
+ Example:<br>
+ <br>
+ v0 20 t3 ld<br>
+ <br>
+ This is equivalent to "ld $t3,20($v0)" in conventional syntax.<br>
+<br>
+When the assembler is active, the vocabulary containing the MIPS opcode and
+operand words is first in the search order, but the "forth" vocabulary containing
+all the other Forth tools is also in the search order, so you can execute
+ordinary Forth commands while assembling MIPS code. This is useful for things
+like including other files (by using the "fload" command) and calculating
+the values of numeric constants.<br>
+
+<h3><a name="Register_names"></a>Register names</h3>
+ Executing the name of a MIPS register pushes on the stack a number that
+identifies that register. The register names are:<br>
+ <br>
+<b> $0</b> .. <b>$31</b> Basic
+names for the 32 integer registers<br>
+<b> $f0</b> .. <b>$f31</b> Basic names
+for the 32 floating point registers<br>
+ <br>
+<b> v0</b> .. <b>v1</b><br>
+<b> k0</b> .. <b>k1</b><br>
+<b> t0</b> .. <b>t9</b><br>
+<b> s0</b> .. <b>s8</b> <br>
+<b> $a0</b> .. <b>$a3</b><br>
+<b> $sp $gp ra $at</b><br>
+<b> $kt0</b> .. <b>$kt1</b><br>
+<blockquote>Aliases for certain integer registers, reflecting their conventional
+use by MIPS compilers.<br>
+</blockquote>
+ <b>sp rp up ip np base tos w</b><br>
+<blockquote>Aliases for certain integer registers, reflecting their use within
+the Forth virtual machine.<br>
+sp = $sp , rp=s6 , up=s3 , ip=s5, np=s1 , base=s2, tos=s4, w=t0<br>
+</blockquote>
+The inconsistent naming (some alias names begin with $ and some don't) is
+historical accident - in part it is due to the fact that the names a0, a1,
+a2, and a3 conflict with hex numbers.<br>
+
+<h3><a name="Opcodes"></a>Opcodes</h3>
+ rs - A register (in load and store instructions, this register is the one
+that <br>
+ rt - A register (in load and store instructions, this register is
+the one that receives or supplies the data)<br>
+ imm - immediate operand<br>
+ <br>
+
+<table cellpadding="2" cellspacing="2" border="1">
+ <tbody>
+ <tr>
+ <th valign="top">Opcodes<br>
+ </th>
+ <th valign="top" nowrap="true">Stack Operands<br>
+ </th>
+ <th valign="top">Comments<br>
+ </th>
+ </tr>
+ <tr>
+ <td valign="top">ldl, ldr, lb, lh, lwl, lw, lbu, lhu, lwr, lwu, cache,
+ll, lwc1, lwc2, pref, lld, ldc1, ldc2, ld<br>
+ </td>
+ <td valign="top" nowrap="true">( rs imm rt -- )<br>
+ </td>
+ <td valign="top">Load instructions - rt receives the data<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">sb, sh, swl, sw, sdl, sdr, swr, sc, swc1, swc2, scd,
+sdc1, sdc2, sd<br>
+ </td>
+ <td valign="top" nowrap="true">( rt rs imm -- )<br>
+ </td>
+ <td valign="top">Store instructions - rt supplies the data<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">add, addu, sub, subu, and, or, xor, nor, slt, sltu,
+dadd, daddu, dsub, dsubu<br>
+ </td>
+ <td valign="top" nowrap="true">( rs rt rd -- )<br>
+ </td>
+ <td valign="top">Two-operand instructions - rs OP rd -> rd<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">lui<br>
+ </td>
+ <td valign="top" nowrap="true">( imm rt -- )<br>
+ </td>
+ <td valign="top">Load upper immediate - (imm << 16) -> rt<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">sethi<br>
+ </td>
+ <td valign="top" nowrap="true">( imm1 rt -- )<br>
+ </td>
+ <td valign="top">Alternative form of lui - you specify the actual
+immediate value that you want to appear in the register. E.g. h# 0f450000
+$a2 sethi<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">addi, addiu, slti, sltiu, daddi, daddiu, andi, ori,
+xori<br>
+ </td>
+ <td valign="top" nowrap="true">( rs imm rt -- )<br>
+ </td>
+ <td valign="top">Two-operand immediate instructions - rs OP imm ->
+rt<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">j, jal<br>
+ </td>
+ <td valign="top" nowrap="true">( adr -- )<br>
+ </td>
+ <td valign="top">Jump/Jump and link to target address adr<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">sll, srl, sra, dsll, dsrl, dsra, dsll32, dsrl32,
+dsra32<br>
+ </td>
+ <td valign="top" nowrap="true">( rt imm rd -- )<br>
+ </td>
+ <td valign="top">Shift instructions - rt SHIFT imm -> rd<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">sllv, srlv, srav, dsllv, dsrlv, dsrav<br>
+ </td>
+ <td valign="top" nowrap="true">( rt rs rd -- )<br>
+ </td>
+ <td valign="top">Variable shift instructions - rt SHIFT rs -> rd<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">mult, multu, div, divu, dmult, dmultu, ddiv, ddivu,
+tge, tgeu, tlt, tltu, teq, tne<br>
+ </td>
+ <td valign="top" nowrap="true">( rs rt -- )<br>
+ </td>
+ <td valign="top">Two-operand instructions with implicit destination
+register<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">mfhi, mthi, mflo, mtlo<br>
+ </td>
+ <td valign="top" nowrap="true">( rd -- )<br>
+ </td>
+ <td valign="top">Access to HI and LO registers. rd is the source
+of destination as appropriate.<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">beq, bne, beql, bnel<br>
+ </td>
+ <td valign="top" nowrap="true">( adr rs rt -- )<br>
+ </td>
+ <td valign="top">Two-operand conditional branches - branch to address
+'adr' if rs COND rt<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">blez, bgtz, blezl, bgtzl, bltz, bgez, bltzl, bgezl,
+bltzal, bgezal, bltzall, bgezall<br>
+ </td>
+ <td valign="top">( adr rs -- )<br>
+ </td>
+ <td valign="top">One operand conditional branches - branch to address
+'adr' if COND(rs)<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">bra, bal</td>
+ <td valign="top">( adr -- )<br>
+ </td>
+ <td valign="top">Branch, branch and link (the former is a special
+case of a conditional branch)<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">bc0f, bc0fl, bc0t, bc0tl, bc1f, bc1fl, bc1t, bc1tl<br>
+ </td>
+ <td valign="top">( adr -- )<br>
+ </td>
+ <td valign="top">Coprocessor branches<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">tgei, tgeiu, tlti, tltiu, teqi, tnei<br>
+ </td>
+ <td valign="top">( rs imm -- )<br>
+ </td>
+ <td valign="top">Trap immediate - trap if rs COND imm<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">syscall, break, sync, dbreak<br>
+ </td>
+ <td valign="top">( -- )<br>
+ </td>
+ <td valign="top">Zero-operand instructions<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">mtdr, mfdr<br>
+ </td>
+ <td valign="top">( dbreg rt -)<br>
+ </td>
+ <td valign="top">Access to debug registers<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">single, double, float<br>
+ </td>
+ <td valign="top">( -- )<br>
+ </td>
+ <td valign="top">Set the mode for subsequent floating point instructions<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">addf, subf, mulf, divf<br>
+ </td>
+ <td valign="top">( fs ft fd -- )<br>
+ </td>
+ <td valign="top">Two-operand floating point instructions - fs OP ft
+-> fd<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">sqrt, abs, movf, negf, round.w, trunc.w, ceil.w,
+floor.w, cvt.s, cvt.d, cvt.w, cxx<br>
+ </td>
+ <td valign="top">( fs fd -- )<br>
+ </td>
+ <td valign="top">One-operand floating point instructions - OP(fs)
+-> fd<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">mfc1, cfc1, mtc1, ctc1<br>
+ </td>
+ <td valign="top">( fs rt -- )<br>
+ </td>
+ <td valign="top">Floating-point coprocessor-register to integer-register
+instructions<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">mfc0, mtc0, dmfc0, dmtc0<br>
+ </td>
+ <td valign="top">( cpreg rt -- )<br>
+ </td>
+ <td valign="top">System coprocessor-register to integer-register instructions<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">tlbp, tlbr, tlbwi, tlbwr,eret<br>
+ </td>
+ <td valign="top">( -- )<br>
+ </td>
+ <td valign="top">TLB and exception instructions<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">.s, .d, .w<br>
+ </td>
+ <td valign="top">( -- )<br>
+ </td>
+ <td valign="top">Floating point formats<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">dset<br>
+ </td>
+ <td valign="top" nowrap="true">( low high reg -- )<br>
+ </td>
+ <td valign="top">Assemble code to put the 64-bit number low, high
+into the register<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">li, set<br>
+ </td>
+ <td valign="top" nowrap="true">( n reg -- )<br>
+ </td>
+ <td valign="top">Assemble code to put the 32-bit number n into the
+register (li and set are equivalent)<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">la<br>
+ </td>
+ <td valign="top">( adr dst -- )<br>
+ </td>
+ <td valign="top">Like li but sets a relocation bit for the Forth dictionary
+file.<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">brif<br>
+ </td>
+ <td valign="top">( adr cond -- )<br>
+ </td>
+ <td valign="top">Assemble a branch from a conditional constructor
+(see below)<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">=, <><br>
+ </td>
+ <td valign="top">( rs rt -- cond )<br>
+ </td>
+ <td valign="top">Constructor for two-operand structured conditionals
+- rs COND rt<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">0<=, 0>, 0<, 0>=<br>
+ </td>
+ <td valign="top">( rs -- cond )<br>
+ </td>
+ <td valign="top">Constructor for one-operand structured conditionals
+- COND(rs)<br>
+ </td>
+ </tr>
+
+ </tbody>
+</table>
+
+<h3><a name="Structured_Conditionals"></a>Structured Conditionals</h3>
+The MIPS assembler includes macros for constructing common flow control structures
+without having to make up label names. The structures shown below can be
+nested to arbitrary depth.<br>
+The easiest way to deal with branch delay slots is just to fill them with
+nop's.<br>
+In the following examples, the delay-slot instructions are indented the same
+as the code <i>preceding</i> their branch instruction, to emphasize that
+the delay instruction is logically a part of the preceding code flow. <br>
+<br>
+
+<table cellpadding="2" cellspacing="2" border="1">
+ <tbody>
+ <tr>
+ <th valign="top" nowrap="true">Usage Form<br>
+ </th>
+ <th valign="top" nowrap="true">Example<br>
+ </th>
+ <th valign="top" nowrap="true">Equivalent Code<br>
+(in noreorder mode) <br>
+ </th>
+ <th valign="top">Comments<br>
+ </th>
+ </tr>
+ <tr>
+ <td valign="top" nowrap="true"><i>cond</i> if .. then<br>
+ </td>
+ <td valign="top" nowrap="true"><tt>t3 t4 <> if<br>
+nop \ Delay<br>
+ t3 1 t3 addiu<br>
+then</tt><br>
+ </td>
+ <td valign="top" nowrap="true"><tt> beq t3,t4,1f<br>
+ nop<br>
+ addiu t3,1,t3<br>
+1:</tt><br>
+ </td>
+ <td valign="top">1) The conditional in this case is "t3 t4 <>",
+i.e not equal, which takes two register operands.<br>
+2) Note the branch delay slot after the "if"<br>
+3) There is no delay slot after "then" because it just marks the target of
+a forward branch.<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top" nowrap="true"><i>cond</i> if .. else
+ .. then<br>
+ </td>
+ <td valign="top" nowrap="true"><tt>t2 0> if<br>
+$7 0 $4 lw \ Delay<br>
+ sp -4 sp addiu<br>
+ $a1 $a3 mult<br>
+else<br>
+ $3 $4 $5 add \ Delay<br>
+ <br>
+ $7 4 $4 lw<br>
+then<br>
+ </tt><br>
+ </td>
+ <td valign="top" nowrap="true"><tt> blez t2,1f<br>
+ lw $4,0($7)<br>
+ addiu $sp,$sp,4<br>
+ mult $a1,$a3<br>
+ b 2f<br>
+ add $3,$4,$5<br>
+1:<br>
+ lw $4,4($7)<br>
+2:</tt><br>
+ </td>
+ <td valign="top">1) The conditional in this case is "t2 0>", i.e.
+t2 greater than zero.<br>
+2) Note the branch delay slots after "if" and "else", because of the implicit
+branch around the else clause.<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top" nowrap="true">begin .. again<br>
+ </td>
+ <td valign="top" nowrap="true"><tt>begin<br>
+again<br>
+ t3 0 t4 lw \ Delay</tt> <br>
+ </td>
+ <td valign="top" nowrap="true"><tt>1:<br>
+ beq $0,$0,1b<br>
+ lw $t4,0($t4)</tt><br>
+ </td>
+ <td valign="top">1) In this infinite-loop example, there are no other
+instructions between "begin" and "again". The important work is done in the
+delay slot after the unconditional branch that "again" generates. It is of
+course possible to put instructions between "begin" and "again"<br>
+2) Note that there is no delay slot after "begin", because "begin" does not
+generate a branch instruction; it marks the target of a backward branch.<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top" nowrap="true">begin .. <i>cond</i> until<br>
+ </td>
+ <td valign="top" nowrap="true"><tt>begin<br>
+ s0 s1 s1 add<br>
+ t3 t4 t5 add<br>
+t5 t6 = until<br>
+ nop \ Delay</tt><br>
+ </td>
+ <td valign="top" nowrap="true"><tt>1:<br>
+ add $s1,$s0,$s1<br>
+ add $t5,$t3,$t4<br>
+ bne $t5,$t6,1b<br>
+ nop</tt><br>
+ </td>
+ <td valign="top">1) "until" generates a conditional backward branch,
+so it has a delay slot<br>
+2) "\ Delay" is just a comment to remind you what is happening. It does not
+affect the code that is generated.<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top" nowrap="true">begin ..<br>
+ <i>cond</i> while ...<br>
+repeat<br>
+ </td>
+ <td valign="top" nowrap="true"><tt>begin<br>
+ $a0 8 $a1 lw<br>
+$a1 $0 <> while<br>
+ nop \ Delay<br>
+ $a0 4 $a0 lw<br>
+repeat nop \ Delay<br>
+ </tt> <br>
+ </td>
+ <td valign="top" nowrap="true"><tt>1:<br>
+ lw $a1,8($a0)<br>
+ beq $a1,$0, 2f<br>
+ nop<br>
+ lw $a0,4($a0)<br>
+ beq $0,$0,1b<br>
+ nop<br>
+2:</tt><br>
+ </td>
+ <td valign="top">1) "while" generates a conditional forward branch
+past the <br>
+"repeat", so it has a delay slot<br>
+2) "repeat" generates a conditional backward branch to <br>
+"begin", so it has a delay slot<br>
+3) Note that the delay instruction can be on the same line as the "repeat"
+if you wish. This is generally true; since the assembler syntax is postfix
+without any need for "lookahead", line boundaries are irrelevant. You can
+put multiple opcodes on one line if you wish.<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top">ahead .. then<br>
+ </td>
+ <td valign="top"><tt>ahead<br>
+nop \ Delay<br>
+ 12345 ,<br>
+ 6789 ,<br>
+ 3 , <br>
+then</tt><br>
+ </td>
+ <td valign="top"><tt> beq $0,$0, 1f<br>
+ nop<br>
+ .word 12345<br>
+ .word 6786<br>
+ .word 3<br>
+1:</tt><br>
+ </td>
+ <td valign="top">1) "ahead" generates an unconditional forward branch
+to "then". It has a delay slot.<br>
+2) In this example we are using it to skip some data that we have placed
+in-line.<br>
+3) The most common use of unconditional forward branches is subsumed by the
+"if .. else .. then" construct, so "ahead" is rarely used.<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top" nowrap="true">ahead .. but then<br>
+ </td>
+ <td valign="top" nowrap="true"><tt>ahead<br>
+t0 0 t1 lw \ Delay<br>
+begin<br>
+ t0 4 t2 lw<br>
+ t2 t3 t3 add<br>
+but then<br>
+t1 $0 = until<br>
+ t1 -1 t1 addiu \ Delay<br>
+ <br>
+ </tt><br>
+ </td>
+ <td valign="top" nowrap="true"><tt> beq $0,$0,1f<br>
+ lw $t1,0($t0)<br>
+2:<br>
+ lw $t2,4($t0)<br>
+ add $t3,$t2,$t3<br>
+1:<br>
+ bne $t1,$0,2b<br>
+ addiu $t1,$t1,-1</tt><br>
+ </td>
+ <td valign="top">This is an advanced usage in which two conditional
+constructs ("begin .. until" and "ahead .. then") are not properly
+nested. The intention here is to start the loop execution at the test condition
+at the end. "ahead .. then" is used to branch forward to the test condition.
+The "but" rearranges the assembler's control flow stack so that "then" can
+resolve "ahead" without being confused by the intervening "begin".<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top" nowrap="true">begin ..<br>
+ <i>cond</i> if .. then<br>
+ <i>cond</i> until<br>
+ </td>
+ <td valign="top" nowrap="true"><tt>begin<br>
+ t0 8 t1 lw<br>
+ t1 t2 <> if<br>
+ nop \ Delay<br>
+ t1 t3 t3 add<br>
+ then<br>
+ t1 -5 t1 addiu<br>
+t1 0< until<br>
+ nop \ Delay </tt>
+ <br>
+ </td>
+ <td valign="top" nowrap="true"><tt>1:<br>
+ lw $t1,8($t0)<br>
+ beq $t1,$t2,2f<br>
+ nop<br>
+ add $t3,$t1,$t3<br>
+2:<br>
+ addiu $t1,$t1,-5<br>
+ bgez t1,1b<br>
+ nop</tt><br>
+ </td>
+ <td valign="top">This is a straightforward example of well-nested control
+structures.<br>
+ <br>
+Note the use of indentation to show the scope of the control flow. Especially
+note how the delay slots are indented the same as the code <i>preceding</i>
+the branch.<br>
+ </td>
+ </tr>
+
+ </tbody>
+</table>
+
+<h3><a name="Local_Labels"></a>Local Labels</h3>
+ Local (numbered) labels can be used in conjunction with branch instructions
+to create control flows that can't easily be represented with the structured
+conditionals. These are rarely needed, since the structured conditionals
+cover the most common cases, and your code will be easier to understand if
+you can express it in terms of those structures.<br>
+ <br>
+
+<table cellpadding="2" cellspacing="2" border="1">
+ <tbody>
+ <tr>
+ <th valign="top">Command<br>
+ </th>
+ <th valign="top">Stack Effect<br>
+ </th>
+ <th valign="top">Description<br>
+ </th>
+ </tr>
+ <tr>
+ <td valign="top"><b>l:</b><br>
+ </td>
+ <td valign="top">( label# -- )<br>
+ </td>
+ <td valign="top">(ell-colon) Create a local label with the given number<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"><b>f:</b><br>
+ </td>
+ <td valign="top">( label# -- adr )<br>
+ </td>
+ <td valign="top">Return the address of the next occurrence of the
+given local label in the forward direction<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"><b>b:</b><br>
+ </td>
+ <td valign="top">( label# -- adr )<br>
+ </td>
+ <td valign="top">Return the address of the next occurrence of the
+given local label in the backward direction<br>
+ </td>
+ </tr>
+
+ </tbody>
+</table>
+
+<h3><a name="Directives"></a>Directives</h3>
+These assembler directives are primarily used to create assembly-language
+"dropin modules" that execute on target machines before the Forth execution
+environment has been set up.<br>
+<br>
+<table cellpadding="2" cellspacing="2" border="1">
+ <tbody>
+ <tr>
+ <th valign="top">Directive<br>
+ </th>
+ <th valign="top" nowrap="true">Stack</th>
+ <th valign="top">Description<br>
+ </th>
+ </tr>
+ <tr>
+ <td valign="top"><b> start-assembling</b><br>
+ </td>
+ <td valign="top" nowrap="true">( -- )<br>
+ </td>
+ <td valign="top">Set <b>asm-base</b> to the current address within
+Forth data space, thus marking that address as the start of memory that will
+later be written to a file. Set <b>asm-origin</b> to 0. Arrange for
+the names of any subsequent labels to be stored in a separate memory space.
+ <br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"><b> end-assembling</b><br>
+ </td>
+ <td valign="top" nowrap="true">( -- )<br>
+ </td>
+ <td valign="top">Restore labels to their default behavior (i.e. label
+names will subsequently be stored in-line in Forth data space rather than
+in a separate area).<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"><b> label</b> <i>newname</i><br>
+ </td>
+ <td valign="top" nowrap="true">( -- )<br>
+ </td>
+ <td valign="top">Mark the current location in Forth data space so that
+later execution of <i>newname</i> will return that address. When executed
+within the context of <b>start-assembling .. end-assembling</b> , the label
+name will be stored in a separate memory area outside of the Forth data space
+(normally, in a Forth dictionary context, the Forth data space consists of
+interspersed names and data).<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"><b>asm-origin</b><b> </b><br>
+ </td>
+ <td valign="top" nowrap="true">( -- <i>adr</i> )<br>
+ </td>
+ <td valign="top">A Forth <b>value </b>that contains the address within
+the target machine's address space that corresponds to the beginning of the
+memory marked by <b>start-assembling</b> .The default value, set by <b>start-assembling</b>,
+is 0, but it can be changed to an arbitrary value <i>n</i> by executing "<i>n</i>
+ <b> to asm-origin</b>" . <br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"><b>asm-base</b><b> </b><br>
+ </td>
+ <td valign="top" nowrap="true">( -- adr )<br>
+ </td>
+ <td valign="top">A Forth value that contains the start address within
+the host machines address space of the beginning of the memory marked by
+ <b>start-assembling</b> .<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"> <b>pad-to</b><br>
+ </td>
+ <td valign="top" nowrap="true">( <i>adr</i> -- )<br>
+ </td>
+ <td valign="top">Add 0x0 bytes to memory until the current address
+within the target machine's address space is <i>adr</i>. Specifically, (
+ <b>here</b> - <b>asm-origin</b> ) = ( <b>adr</b> - <b>asm-origin</b>
+) when pad-to completes. Aborts if the current address is already above <i>adr</i>
+. <br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"> <b>align-to</b><br>
+ </td>
+ <td valign="top" nowrap="true">( <i>n</i> -- )<br>
+ </td>
+ <td valign="top">Add 0x0 bytes to memory until the current address
+within the target machine's address space is a multiple of <i>n</i> <br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"> <b>assemble-little-endian</b><br>
+ </td>
+ <td valign="top" nowrap="true">( -- )<br>
+ </td>
+ <td valign="top">Configure the MIPS assembler to generate code in little-endian
+byte order. The default is the byte order of the host system.<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"> <b>assemble-big-endian</b><br>
+ </td>
+ <td valign="top" nowrap="true">( -- )<br>
+ </td>
+ <td valign="top">Configure the MIPS assembler to generate code in little-endian
+byte order. The default is the byte order of the host system.<br>
+ </td>
+ </tr>
+ <tr>
+ <td valign="top"><b> c$,</b><br>
+ </td>
+ <td valign="top" nowrap="true">( adr len -- )<br>
+ </td>
+ <td valign="top">Place the bytes from the range <i>adr len</i> into
+memory, followed by a null terminator byte (which need not be present in
+the source range) and sufficient padding for four-byte alignment. This is
+primarily used within the "reset" module to place the names of other dropin
+modules in-line within the code.<br>
+ </td>
+ </tr>
+ </tbody>
+</table>
+.<br>
+ <br>
+<br>
+<br>
+<br>
+<br>
+<br>
+<br>
+<br>
+<br>
+<br>
+<br>
+<br>
+ <br>
+ <br>
+ <br>
+ <br>
+</body>
+</html>
Added: cpu/mips/atlas/build/makerom
===================================================================
--- cpu/mips/atlas/build/makerom (rev 0)
+++ cpu/mips/atlas/build/makerom 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,4 @@
+#!/bin/sh
+build rom
+echo Converting to ELF format
+./bintoelf -a 0x80200000 -p 8 -l <rom.img >rom.elf
Property changes on: cpu/mips/atlas/build/makerom
___________________________________________________________________
Added: svn:executable
+ *
Added: cpu/mips/atlas/forthmon.bth
===================================================================
--- cpu/mips/atlas/forthmon.bth (rev 0)
+++ cpu/mips/atlas/forthmon.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,56 @@
+purpose: Load file for ForthMon for MIPS on the Atlas board
+copyright: Copyright 2000-2001 FirmWorks All Rights Reserved
+
+dictionary: ${BP}/cpu/mips/build/tools.dic
+command: &mipsfth &dictionary &this
+build-now
+
+\ ' $report-name is include-hook
+\ true to stand-init-debug?
+
+\ true ' fcode-debug? set-config-int-default
+\ " com1" ' output-device set-config-string-default
+\ " com1" ' input-device set-config-string-default
+
+fload ${BP}/cpu/mips/ksegaddr.fth
+fload ${BP}/cpu/mips/atlas/physaddr.fth
+fload ${BP}/cpu/mips/atlas/virtaddr.fth
+
+: rl@ l@ ; : rl! l! ;
+: rw@ w@ ; : rw! w! ;
+: rb@ c@ ; : rb! c! ;
+
+fload ${BP}/cpu/mips/atlas/isaio.fth \ ISA I/O space access
+fload ${BP}/dev/diag16550.fth \ Diagnostic driver for serial port
+h# 0 is uart-base
+d# 3686400 constant uart-clock-frequency
+
+fload ${BP}/forth/lib/sysuart.fth \ Plug UART routines into key and emit
+
+h# 1.0000 constant initial-heap-size
+fload ${BP}/cpu/mips/boot.fth \ Low-level startup code
+
+fload ${BP}/fm/lib/dumballo.fth \ Rudimentary memory allocator
+
+: stand-init-io ( -- )
+[ifdef] stand-init-io
+ stand-init-io
+[then]
+ install-dumb-alloc
+ install-uart-io
+;
+: stand-init ;
+
+: startup ( -- )
+ hex
+ warning on
+ only forth also definitions
+;
+
+install-rom-cold
+
+.( --- Saving forthmon.dic ---) " forthmon.dic" $save-forth cr
+
+\ \needs to-srecs fload ${BP}/tools/srec2.fth
+\ rom-pa rom-entry-pa to-srecs forthmon.dic forthmsr.sr
+\ rom-pa rom-entry-pa to-swapped-srecs forthmon.dic forthmsr.ssr
Added: cpu/mips/atlas/isaio.fth
===================================================================
--- cpu/mips/atlas/isaio.fth (rev 0)
+++ cpu/mips/atlas/isaio.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,12 @@
+purpose: Access to ISA IO space for the Atlas board
+copyright: Copyright 2000 Firmworks All Rights Reserved
+
+headers
+kseg1 uart-pa + value uart-base
+
+: pc@ ( offset -- n ) 3 lshift uart-base + rb@ ;
+: pc! ( n offset -- ) 3 lshift uart-base + rb! ;
+: pw@ ( offset -- n ) 3 lshift uart-base + rw@ ;
+: pw! ( n offset -- ) 3 lshift uart-base + rw! ;
+: pl@ ( offset -- n ) 3 lshift uart-base + rl@ ;
+: pl! ( n offset -- ) 3 lshift uart-base + rl! ;
Added: cpu/mips/atlas/physaddr.fth
===================================================================
--- cpu/mips/atlas/physaddr.fth (rev 0)
+++ cpu/mips/atlas/physaddr.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,36 @@
+purpose: Physical addresses for the Atlas board
+copyright: Copyright 2000 FirmWorks All Rights Reserved
+
+headerless
+
+h# 0000.0000 constant ram-pa
+h# 0800.0000 constant pci-lo0-pa
+h# 1800.0000 constant pci-lo1-pa
+h# 1c00.0000 constant rom-pa1
+h# 1e00.0000 constant rom-pa0
+h# 1fc0.0000 constant rom-pa
+\ h# 1fd0.0000 constant system-controller-specific
+\ h# 1fe0.0000 kseg1 + constant bonito-cfg-pa
+\ h# 1fe0.0100 kseg1 + constant bonito-reg-pa
+\ h# 1fe8.0000 constant pci-cfg-pa
+h# 1f00.0000 constant io0-pa
+h# 1f00.0900 constant uart-pa
+
+\ pci-io-pa kseg1 + constant isa-io-base
+
+h# 0200.0000 constant /ram-bank
+
+h# 20.0000 constant rom-base
+h# 20.0020 constant rom-entry
+h# 10.0000 constant /rom
+h# 60 constant /resetjmp
+rom-base kseg0 + constant rom-pa
+rom-entry kseg0 + constant rom-entry-pa
+rom-pa /resetjmp + constant dropin-base
+
+\ Bonito registers
+\ h# 18 bonito-reg-pa + constant pcimap_cfg
+\ h# 50 bonito-reg-pa + constant pcicachectrl
+\ h# 54 bonito-reg-pa + constant pcicachetag
+
+headers
Added: cpu/mips/atlas/virtaddr.fth
===================================================================
--- cpu/mips/atlas/virtaddr.fth (rev 0)
+++ cpu/mips/atlas/virtaddr.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,12 @@
+purpose: Virtual addresses for the Atlas board
+copyright: Copyright 2001 FirmWorks All Rights Reserved
+
+headerless
+
+rom-base kseg0 + value fw-virt-base \ 1 meg of mapping space
+h# 10.0000 value fw-virt-size
+
+headers
+
+\ fw-virt-base fw-virt-size + ' load-base set-config-int-default
+0 value load-limit \ Top address of area at load-base (set later)
Added: cpu/mips/basefw.bth
===================================================================
--- cpu/mips/basefw.bth (rev 0)
+++ cpu/mips/basefw.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,143 @@
+purpose: Load file for base firmware - no platform specifics
+\ See license at end of file
+
+dictionary: ${BP}/cpu/mips/build/tools.dic
+command: &mipsfth &dictionary &this
+build-now
+
+\ ' $report-name is include-hook
+
+create resident-packages
+create include-help \ Include help facility
+
+alias cfill fill
+fload ${BP}/ofw/core/ofwcore.fth \ Device tree and other OBP routines
+fload ${BP}/ofw/core/ofwfw.fth \ FirmWorks enhancements
+fload ${BP}/ofw/core/memops.fth \ Call memory node methods
+fload ${BP}/ofw/core/mmuops.fth \ Call MMU node methods
+
+fload ${BP}/cpu/mips/traps.fth \ Exception handlers
+fload ${BP}/cpu/mips/r4000cp0.fth \ Coprocessor 0 registers
+fload ${BP}/cpu/mips/getms.fth \ Timer access
+
+fload ${BP}/cpu/mips/centry.fth \ Low-level client entry and exit
+
+fload ${BP}/ofw/confvar/loadcv.fth \ Configuration variables
+fload ${BP}/ofw/core/silentmd.fth \ NVRAM variable silent-mode?
+
+fload ${BP}/ofw/termemu/loadfb.fth \ Frame buffer support
+fload ${BP}/ofw/termemu/difont.fth \ Get font from a dropin module
+
+fload ${BP}/ofw/termemu/fb8-ops.fth \ 8-bit frame buffer primitives
+\ fload ${BP}/cpu/mips/fb8-ops.fth \ 8-bit frame buffer primitives
+
+fload ${BP}/ofw/gui/alert.fth \ Basic dialogs and alerts
+fload ${BP}/dev/stringio.fth \ Output diversion
+
+fload ${BP}/ofw/core/loadmore.fth \ Load additional core stuff
+
+fload ${BP}/ofw/inet/loadtftp.fth \ Trivial File Transfer Protocol pkg.
+
+\ fload ${BP}/pkg/loadpkg.fth \ Load support packages
+\ fload ${BP}/pkg/inet/loadtcp.fth \ TCP extensions
+
+fload ${BP}/cpu/mips/catchexc.fth \ Exception handler
+fload ${BP}/cpu/mips/forthint.fth \ Alarm handler
+
+fload ${BP}/cpu/mips/regacc.fth \ Register access words
+
+fload ${BP}/ofw/fcode/loadfcod.fth \ S Fcode interpreter
+
+fload ${BP}/ofw/fcode/regcodes.fth \ Register access words
+fload ${BP}/ofw/fcode/extcodes.fth \ Firmworks extension FCodes
+
+fload ${BP}/ofw/core/initprog.fth \ FCode and Forth source load formats
+
+fload ${BP}/ofw/core/infltdi.fth \ Support for compressed dropin drivers
+
+h# 8010.0000 constant inflater-base
+0 0 2value old-inflater
+: mips-get-inflater ( -- )
+ (get-inflater)
+ inflater to old-inflater
+ inflater inflater-base swap 2dup to inflater move
+ inflater sync-cache
+;
+' mips-get-inflater to get-inflater
+
+: mips-release-inflater ( -- )
+ old-inflater free-mem
+;
+' mips-release-inflater to release-inflater
+
+fload ${BP}/cpu/mips/initpgm.fth \ Basic boot handler
+
+[ifdef] resident-packages
+support-package: fat-file-system
+ fload ${BP}/ofw/fs/fatfs/loadpkg.fth \ FAT file system reader
+end-support-package
+
+support-package: iso9660-file-system
+ fload ${BP}/ofw/fs/cdfs/loadpkg.fth \ ISO 9660 CD-ROM file system reader
+end-support-package
+
+support-package: disk-label
+ fload ${BP}/ofw/disklabel/loadpkg.fth \ Disk label package
+end-support-package
+[then]
+
+[ifdef] resident-packages
+fload ${BP}/ofw/fs/fatfs/fdisk2.fth \ Partition map administration
+[else]
+autoload: fdisk2.fth
+defines: $.partitions
+defines: .partitions
+\ defines: init-nt-disk
+defines: $partition
+[then]
+
+fload ${BP}/fm/lib/pattern.fth \ Text string pattern matching
+fload ${BP}/ofw/core/filecmds.fth \ File commands: dir, del, ren, etc.
+
+: ldump (s adr len -- )
+ base @ >r hex
+ bounds ?do
+ i 8 u.r ." : " i h# 10 bounds do
+ i l@ 8 u.r space space
+ /l +loop
+ i h# 10 bounds do
+ i c@ dup bl h# 80 within if emit else drop ." ." then
+ loop
+ cr
+ exit? (?leave)
+ h# 10 +loop
+ r> base !
+;
+
+[ifndef] no-heads
+.( --- Saving basefw.dic --- ) cr "" basefw.dic save-forth
+[then]
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/bonito/bonito.fth
===================================================================
--- cpu/mips/bonito/bonito.fth (rev 0)
+++ cpu/mips/bonito/bonito.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,84 @@
+purpose: Forth words for Bonito
+copyright: Copyright 2000-2001 FirmWorks All Rights Reserved
+
+defer pcicache-wbinv ' 2drop to pcicache-wbinv
+defer pcicache-inv ' 2drop to pcicache-inv
+
+: bonito-iobc-cmd! ( cmd line -- )
+ ( cmd ) ( line ) 3 << or dup pcicachectrl !
+ dup h# 20 or pcicachectrl !
+ begin pcicachectrl @ h# 20 and 0= until
+ pcicachectrl !
+;
+
+: bonito-iobc-range ( pa size cmd -- )
+ over 0= if 3drop exit then
+ rot h# 1fff.ffff and rot over + rot
+ 4 0 do ( pa top cmd )
+ 2 i bonito-iobc-cmd! ( pa top cmd ) \ Read tag
+ pcicachetag @ dup h# 0100.0000 and if
+ h# 00ff.ffff and 5 << ( pa top cmd tag )
+ 2 pick over > ( pa top cmd tag flag )
+ swap h# 20 + 4 pick > and ( pa top cmd flag )
+ if dup i bonito-iobc-cmd! then ( pa size cmd ) \ Write-back & invalidate
+ else
+ drop ( pa size cmd )
+ then
+ loop 3drop
+;
+
+: bonito-iobc-wbinv-all ( -- )
+ 4 0 do
+ 2 i bonito-iobc-cmd!
+ pcicachetag @ h# 0100.0000 and if
+ 1 i bonito-iobc-cmd!
+ then
+ loop
+ 3 0 bonito-iobc-cmd! \ Flush write queue
+;
+
+: bonito-iobc-wbinv ( pa size -- )
+ 1 bonito-iobc-range \ Write-back & invalidate range
+ 3 0 bonito-iobc-cmd! \ Flush write queue
+;
+' bonito-iobc-wbinv to pcicache-wbinv
+
+: bonito-iobc-inv-all ( -- )
+ 4 0 do
+ 2 i bonito-iobc-cmd!
+ pcicachetag @ h# 0100.0000 and if
+ 0 i bonito-iobc-cmd!
+ then
+ loop
+;
+: bonito-iobc-inv ( pa size -- )
+ 0 bonito-iobc-range \ Invalidate range
+;
+' bonito-iobc-inv to pcicache-inv
+
+: bonito-iobc-dump ( -- )
+ 4 0 do
+ 2 i bonito-iobc-cmd!
+ pcicachetag @
+ i u. dup u. h# ff.ffff and 5 << u. cr
+ loop
+;
+
+: init-bonito ( -- )
+ h# 0000.0800 h# 0c bonito-cfg-pa + w!
+ h# 0000.0000 h# 10 bonito-cfg-pa + l!
+ h# 2000.0000 h# 14 bonito-cfg-pa + l!
+ h# 1000.0000 h# 18 bonito-cfg-pa + l!
+
+ h# 0004.6144 pcimap l!
+ h# 0000.2c0f intedge l!
+ h# 6400.0000 intsteer l!
+ h# 6600.0000 intpol l!
+ h# 0004.21cf intenset l!
+ h# 1a41.fd1f intenclr l!
+;
+
+stand-init: Initialize Bonito
+ init-bonito
+ bonito-iobc-inv-all
+;
Added: cpu/mips/bonito/devalias.fth
===================================================================
--- cpu/mips/bonito/devalias.fth (rev 0)
+++ cpu/mips/bonito/devalias.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,7 @@
+devalias com1 /isa/serial@i3f8
+devalias com2 /isa/serial@i2f8
+devalias mouse /mouse
+devalias net /ethernet
+devalias disk /isa/ide/disk@0
+devalias c /isa/ide/disk@0
+devalias d /isa/ide/disk@1
Added: cpu/mips/bonito/devices.fth
===================================================================
--- cpu/mips/bonito/devices.fth (rev 0)
+++ cpu/mips/bonito/devices.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,86 @@
+purpose: Load device drivers for Bonito
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+hex
+
+fload ${BP}/cpu/mips/bonito/pcicfg.fth
+
+0 0 " " " /" begin-package
+ fload ${BP}/cpu/mips/bonito/mappci.fth \ Map PCI to root
+ fload ${BP}/dev/pcibus.fth \ Generic PCI bus package
+ fload ${BP}/cpu/mips/bonito/pcinode.fth \ System-specific words for PCI
+end-package
+stand-init: PCI host bridge
+ " /pci" " init" execute-device-method drop
+;
+
+fload ${BP}/dev/pciprobe.fth \ Generic PCI probing
+
+\ Create the /ISA node in the device tree, and load the ISA bridge code.
+\ Usually this includes the dma controller, interrupt controller, and timer.
+0 0 " 1c" " /pci" begin-package
+fload ${BP}/dev/fw82371.fth \ ISA node
+end-package
+
+fload ${BP}/dev/isa/irq.fth
+
+support-package: 16550
+fload ${BP}/dev/16550pkg/16550.fth \ Serial port support package
+end-support-package
+
+\ Super I/O support.
+\ Usually includes serial, parallel, floppy, and keyboard.
+\ The 87308 also has gpio and power control functions.
+fload ${BP}/dev/pc87307.fth \ SuperI/O
+
+0 0 dropin-base <# u#s u#> " /" begin-package
+ " flash" device-name
+
+ /rom value /device
+ my-address my-space /device reg
+ fload ${BP}/dev/flashpkg.fth
+end-package
+
+" rom" dropin-base <# u#s " /flash@" hold$ u#> $devalias
+
+fload ${BP}/dev/flashpkg.fth
+fload ${BP}/dev/amd29fxx.fth \ Low-level FLASH programming driver
+fload ${BP}/dev/at29c020.fth \ Low-level FLASH programming driver
+fload ${BP}/cpu/mips/bonito/flash.fth \ Platform-specific FLASH interface
+
+dev /rtc
+ fload ${BP}/cpu/mips/bonito/nvram.fth
+device-end
+
+stand-init: NVRAM
+ " /rtc" open-dev to nvram-node
+ nvram-node 0= if
+ ." The configuration EEPROM is not working" cr
+ then
+ ['] init-config-vars catch drop
+;
+
+0 0 ide0-pa <# u#s u#> " /" begin-package
+ fload ${BP}/dev/ide/bonito.fth
+ fload ${BP}/dev/ide/onelevel.fth
+end-package
+
+h# f800 constant ide-dma-bar
+
+0 0 " i1f0" " /isa" begin-package \ Master IDE
+ create include-secondary-ide
+ fload ${BP}/dev/ide/isaintf.fth
+ fload ${BP}/dev/ide/generic.fth
+ 2 to max#drives
+ fload ${BP}/dev/ide/onelevel.fth
+end-package
+
+: init-ide ( -- )
+ ide-dma-bar h# e120 config-l! \ Set I/O port
+ h# 8022 h# e140 config-w! \ Enable master IDE decoding
+ h# 8022 h# e142 config-w! \ Enable secondary IDE decoding
+ h# 5 h# e104 config-w! \ Enable I/O and bus mastering
+;
+stand-init: Enable IDE on Algorithmics
+ init-ide
+;
Added: cpu/mips/bonito/excption.fth
===================================================================
--- cpu/mips/bonito/excption.fth (rev 0)
+++ cpu/mips/bonito/excption.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,83 @@
+purpose: Exception handlers
+copyright: Copyright 2001 FirmWorks All Rights Reserved
+
+headers
+hex
+
+defer exception-hook ' noop to exception-hook
+
+: .dis1 ( addr -- ) [ also disassembler ] pc l! [ previous ] dis1 ;
+
+: .epc ( -- )
+ epc@
+ cause@ h# 8000.0000 and if la1+ then
+ .dis1
+;
+
+: .badvaddr ( -- )
+ ." Bad virtual address = " badvaddr@ u. cr reset-all
+;
+
+: (exception-handler) ( exception# -- )
+ base @ >r hex
+ exception-hook
+ dup (.exception)
+ .epc
+ case
+ 4 of .badvaddr endof
+ 5 of .badvaddr endof
+ endcase
+ r> base !
+;
+' (exception-handler) to dispatch-exceptions
+
+: ?report ( char -- )
+ " isa-io-base d# 16 >> t0 lui" evaluate
+ " begin t0 h# 3fd t1 lbu t1 h# 20 t1 andi t1 0 <> until nop" evaluate
+ ( char ) " t1 set t1 t0 h# 3f8 sb " evaluate
+;
+
+label (tlb-handler)
+ carret ?report linefeed ?report
+ ascii T ?report ascii L ?report ascii B ?report bl ?report
+ ascii R ?report ascii e ?report ascii f ?report ascii i ?report
+ ascii l ?report ascii l ?report bl ?report
+ ascii E ?report ascii x ?report ascii c ?report ascii e ?report
+ ascii p ?report ascii t ?report ascii i ?report ascii o ?report
+ ascii n ?report
+ carret ?report linefeed ?report
+ begin again
+ nop
+end-code
+' (tlb-handler) to tlb-handler
+
+label (xtlb-handler)
+ carret ?report linefeed ?report
+ ascii X ?report ascii T ?report ascii L ?report ascii B ?report bl ?report
+ ascii R ?report ascii e ?report ascii f ?report ascii i ?report
+ ascii l ?report ascii l ?report bl ?report
+ ascii E ?report ascii x ?report ascii c ?report ascii e ?report
+ ascii p ?report ascii t ?report ascii i ?report ascii o ?report
+ ascii n ?report
+ carret ?report linefeed ?report
+ begin again
+ nop
+end-code
+' (xtlb-handler) to xtlb-handler
+
+label (cache-handler)
+ carret ?report linefeed ?report
+ ascii C ?report ascii a ?report ascii c ?report ascii h ?report
+ ascii e ?report bl ?report
+ ascii E ?report ascii r ?report ascii r ?report ascii o ?report
+ ascii r ?report bl ?report
+ ascii E ?report ascii x ?report ascii c ?report ascii e ?report
+ ascii p ?report ascii t ?report ascii i ?report ascii o ?report
+ ascii n ?report
+ carret ?report linefeed ?report
+ begin again
+ nop
+end-code
+' (cache-handler) to cache-handler
+
+headers
Added: cpu/mips/bonito/flash.fth
===================================================================
--- cpu/mips/bonito/flash.fth (rev 0)
+++ cpu/mips/bonito/flash.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,23 @@
+purpose: Setup for Flash ROM access
+copyright: Copyright 1995-2001 Firmworks. All Rights Reserved.
+
+h# 10.0000 to /flash
+
+0 value flashbase
+
+headerless
+: (fctl!) ( n a -- ) flashbase + rb! ; ' (fctl!) to fctl!
+: (fdata!) ( n a -- ) flashbase + rb! ; ' (fdata!) to fdata!
+: (fc@) ( a -- n ) flashbase + rb@ ; ' (fc@) to fc@
+
+headers
+: open-flash ( -- )
+ flashbase 0= if
+ rom-pa /flash root-map-in to flashbase
+ then
+;
+: close-flash ( -- )
+ flashbase /flash root-map-out 0 to flashbase
+;
+' open-flash to enable-flash-writes
+
Added: cpu/mips/bonito/forthmon.bth
===================================================================
--- cpu/mips/bonito/forthmon.bth (rev 0)
+++ cpu/mips/bonito/forthmon.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,99 @@
+purpose: Load file for ForthMon for MIPS
+copyright: Copyright 2000-2001 FirmWorks All Rights Reserved
+
+dictionary: ${BP}/cpu/mips/build/basefw.dic
+command: &mipsfth &dictionary &this
+build-now
+
+\ ' $report-name is include-hook
+true to stand-init-debug?
+
+true ' fcode-debug? set-config-int-default
+" com1" ' output-device set-config-string-default
+" com1" ' input-device set-config-string-default
+
+fload ${BP}/cpu/mips/ksegaddr.fth
+fload ${BP}/cpu/mips/bonito/physaddr.fth
+fload ${BP}/cpu/mips/bonito/virtaddr.fth
+
+: rl@ l@ ; : rl! l! ;
+: rw@ w@ ; : rw! w! ;
+: rb@ c@ ; : rb! c! ;
+
+fload ${BP}/cpu/mips/bonito/isaio.fth \ ISA I/O space access
+fload ${BP}/dev/diag16550.fth \ Diagnostic driver for serial port
+h# 3f8 is uart-base
+fload ${BP}/forth/lib/sysuart.fth \ Plug UART routines into key and emit
+\ ' ukey is diag-key \ Feed UART input to "dl"
+
+h# 1000 to pagesize
+d# 12 to pageshift
+
+fload ${BP}/cpu/mips/cache.fth \ Cache synchronization/flushing
+fload ${BP}/cpu/mips/rootnode.fth \ Root node mapping
+dev /
+ " Algorithmics,P-6032" model
+ " Algorithmics" encode-string " architecture" property
+\ d# 33,333,333 " clock-frequency" integer-property
+device-end
+
+: (cpu-arch ( -- adr len )
+ " architecture" ['] root-node get-package-property drop
+ get-encoded-string
+;
+' (cpu-arch to cpu-arch
+
+h# 1.0000 constant initial-heap-size
+fload ${BP}/cpu/mips/boot.fth \ Low-level startup code
+
+\ Memory management services
+fload ${BP}/ofw/core/clntmem1.fth \ client services for memory
+fload ${BP}/ofw/core/memlist.fth \ Resource list common routines
+fload ${BP}/ofw/core/showlist.fth \ Linked list display tool
+fload ${BP}/ofw/core/allocph1.fth \ S Physical memory allocator
+fload ${BP}/ofw/core/availpm.fth \ Available memory list
+fload ${BP}/ofw/core/allocmor.fth \ S Allow alloc-mem to use more memory
+
+: (initial-heap) ( -- adr len ) sp0 @ ps-size - limit tuck - ;
+['] (initial-heap) to initial-heap
+
+\ fload ${BP}/forth/lib/dumballo.fth \ Rudimentary memory allocator
+
+variable bank-mask
+" Set bank-mask" ?reminder
+1 bank-mask !
+fload ${BP}/cpu/mips/probemem.fth \ Memory probing
+stand-init: Probing memory
+ " probe" memory-node @ $call-method
+;
+
+\ File system
+
+: call32 ; defer .subname
+fload ${BP}/ofw/core/allocsym.fth \ Allocate memory for symbol table
+fload ${BP}/ofw/core/symcif.fth
+fload ${BP}/ofw/core/symdebug.fth
+: release-load-area ( boundary-adr -- ) drop ;
+fload ${BP}/ofw/elf/elf.fth
+fload ${BP}/ofw/elf/elfdebug.fth
+' 2drop is elf-map-in
+
+\ Device Tree
+
+: stand-init-io ( -- )
+[ifdef] stand-init-io
+ stand-init-io
+[then]
+\ install-dumb-alloc
+ install-uart-io
+;
+
+: startup ( -- )
+ hex
+ warning on
+ only forth also definitions
+;
+
+install-rom-cold
+
+.( --- Saving forthmon.dic ---) " forthmon.dic" $save-forth cr
Added: cpu/mips/bonito/fw.bth
===================================================================
--- cpu/mips/bonito/fw.bth (rev 0)
+++ cpu/mips/bonito/fw.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,210 @@
+purpose: Load file for Bonito
+copyright: Copyright 2000-2001 FirmWorks All Rights Reserved
+
+dictionary: ${BP}/fm/cwrapper/mips/build/basefw.dic
+command: &mipsfth &dictionary &this
+build-now
+
+create rom-based?
+\ create ram-image
+
+\ ' $report-name is include-hook
+true to stand-init-debug?
+
+false ' auto-boot? set-config-int-default
+true ' fcode-debug? set-config-int-default
+true ' local-mac-address? set-config-int-default
+" com1" ' output-device set-config-string-default
+" com1" ' input-device set-config-string-default
+
+fload ${BP}/cpu/mips/ksegaddr.fth
+fload ${BP}/cpu/mips/bonito/physaddr.fth
+fload ${BP}/cpu/mips/bonito/virtaddr.fth
+
+: rl@ l@ ; : rl! l! ;
+: rw@ w@ ; : rw! w! ;
+: rb@ c@ ; : rb! c! ;
+
+fload ${BP}/cpu/mips/bonito/isaio.fth \ ISA I/O space access
+fload ${BP}/dev/diag16550.fth \ Diagnostic driver for serial port
+h# 3f8 is uart-base
+fload ${BP}/os/stand/sysuart.fth \ Plug UART routines into key and emit
+\ ' ukey is diag-key \ Feed UART input to "dl"
+
+h# 1000 to pagesize
+d# 12 to pageshift
+
+fload ${BP}/cpu/mips/cache.fth \ Cache synchronization/flushing
+fload ${BP}/cpu/mips/bonito/bonito.fth \ IOBC synchronization/flushing
+fload ${BP}/cpu/mips/bonito/rootnode.fth \ Root node mapping
+dev /
+ " Algorithmics,P-6032" model
+ " Algorithmics" encode-string " architecture" property
+\ d# 33,333,333 " clock-frequency" integer-property
+device-end
+
+: (cpu-arch ( -- adr len )
+ " architecture" ['] root-node get-package-property drop
+ get-encoded-string
+;
+' (cpu-arch to cpu-arch
+
+h# 1.0000 constant initial-heap-size
+fload ${BP}/cpu/mips/boot.fth \ Low-level startup code
+
+[ifdef] notyet
+0 config-int next-xid
+stand-init: Next xid
+ next-xid h# 10.0000 + dup to next-xid to rpc-xid
+;
+[then]
+
+\ Memory management services
+[ifdef] virtual-mode
+fload ${BP}/ofw/core/clntmem1.fth \ client services for memory
+[else]
+fload ${BP}/ofw/core/clntphy1.fth \ client services for memory
+[then]
+fload ${BP}/ofw/core/memlist.fth \ Resource list common routines
+fload ${BP}/ofw/core/showlist.fth \ Linked list display tool
+fload ${BP}/ofw/core/allocph1.fth \ S Physical memory allocator
+fload ${BP}/ofw/core/availpm.fth \ Available memory list
+fload ${BP}/ofw/core/allocmor.fth \ S Allow alloc-mem to use more memory
+
+: (initial-heap) ( -- adr len ) sp0 @ ps-size - limit tuck - ;
+['] (initial-heap) to initial-heap
+
+\ fload ${BP}/fm/lib/dumballo.fth \ Rudimentary memory allocator
+
+variable bank-mask
+" Set bank-mask" ?reminder
+1 bank-mask !
+fload ${BP}/cpu/mips/probemem.fth \ Memory probing
+stand-init: Probing memory
+ " probe" memory-node @ $call-method
+;
+
+\ Load file format handlers
+
+: call32 ; defer .subname
+fload ${BP}/ofw/core/allocsym.fth \ Allocate memory for symbol table
+fload ${BP}/ofw/core/symcif.fth
+fload ${BP}/ofw/core/symdebug.fth
+: release-load-area ( boundary-adr -- ) drop ;
+fload ${BP}/ofw/elf/elf.fth
+fload ${BP}/ofw/elf/elfdebug.fth
+' 2drop is elf-map-in
+
+\ File system
+fload ${BP}/cpu/mips/zipcrc.fth \ Assembly portion of CRC calculation
+fload ${BP}/forth/lib/crc32.fth \ High-level portion of CRC calculation
+
+fload ${BP}/pkg/fatfs/fdisk2.fth \ Partition map administration
+
+[ifdef] resident-packages
+support-package: fat-file-system
+ fload ${BP}/ofw/fs/fatfs/loadpkg.fth \ FAT file system reader
+end-support-package
+
+support-package: iso9660-file-system
+ fload ${BP}/ofw/fs/cdfs/loadpkg.fth \ ISO 9660 CD-ROM file system reader
+end-support-package
+
+support-package: disk-label
+ fload ${BP}/ofw/disklabel/loadpkg.fth \ Disk label package
+end-support-package
+
+[ifdef] use-ufs
+support-package: ufs-file-system
+ fload ${BP}/ofw/fs/ufs/ufs.fth \ Unix file system
+end-support-package
+[then]
+
+support-package: ext2-file-system
+ fload ${BP}/ofw/fs/ext2fs/ext2fs.fth \ Linux file system
+end-support-package
+
+support-package: dropin-file-system
+ fload ${BP}/ofw/fs/dropinfs.fth \ Dropin file system
+end-support-package
+
+support-package: nfs
+ fload ${BP}/ofw/fs/nfs/loadpkg.fth
+end-support-package
+[then]
+
+\ Device Tree
+fload ${BP}/cpu/mips/bonito/devices.fth
+fload ${BP}/cpu/mips/bonito/devalias.fth
+
+: stand-init-io ( -- )
+[ifdef] stand-init-io
+ stand-init-io
+[then]
+\ install-dumb-alloc
+ install-uart-io
+;
+
+fload ${BP}/cpu/mips/bonito/excption.fth
+fload ${BP}/cpu/mips/bonito/intr.fth
+
+: probe-all ( -- )
+ " probe-" do-drop-in
+ probe-pci
+ " probe+" do-drop-in
+;
+
+: startup ( -- )
+ hex
+ warning on
+ only forth also definitions
+ kseg0 to vector-base
+ " probe-all" ?type probe-all
+ " install-alarm" ?type install-alarm
+ " install-console" ?type install-console
+;
+
+: hello " net:192.168.1.9,|tftpboot|hello,192.168.1.22" boot-load ;
+: (linux) " net:192.168.1.9,|tftpboot|vmlinux,192.168.1.22" boot-load ;
+: linux (linux) go ;
+
+: bye ( -- )
+ h# 23.0000 intpol l!
+ bongencfg l@ 4 or bongencfg l! bongencfg l@ drop
+ begin again
+;
+' bye to reset-all
+
+defer linux-argc
+: ((linux-argc) ( adr len -- argc )
+ 0 >r begin
+ bl left-parse-string nip 0<> while
+ r> 1+ >r
+ repeat 2drop
+ r>
+;
+: (linux-argc) ( adr len -- argc ) 2drop 2 ;
+' (linux-argc) to linux-argc
+
+defer linux-argv
+: (linux-argv) ( adr len -- 'argv )
+ 3 /n * over + dup alloc-mem dup >r
+ swap erase
+ r@ 3 na+ r@ na1+ !
+ tuck $cstr swap 1+ r@ 3 na+ swap cmove
+ r>
+;
+' (linux-argv) to linux-argv
+
+: linux-setup ( -- )
+ disable-interrupts
+ kseg0 0 sync-cache
+ boot-file linux-argc to $a0
+ boot-file linux-argv to $a1
+ 0 to $a2
+;
+' linux-setup to go-hook
+
+install-rom-cold
+
+.( --- Saving fw.img ...) "" fw.img save-forth cr
Added: cpu/mips/bonito/initbon.fth
===================================================================
--- cpu/mips/bonito/initbon.fth (rev 0)
+++ cpu/mips/bonito/initbon.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,64 @@
+purpose: Initialize Bonito for startup
+copyright: Copyright 2001Firmworks All Rights Reserved
+
+transient
+: bonito! ( data bonito-adr -- )
+ " t0 set" evaluate
+ " t1 set" evaluate
+ " t1 t0 0 sw" evaluate
+;
+: bonito-clrbits ( bits bonito-adr -- )
+ " t0 set" evaluate
+ " t0 0 t2 lw" evaluate
+ invert " t1 set" evaluate
+ " t1 t2 t1 and" evaluate
+ " t1 t0 0 sw" evaluate
+;
+: bonito-setbits ( bits bonito-adr -- )
+ " t0 set" evaluate
+ " t0 0 t2 lw" evaluate
+ " t1 set" evaluate
+ " t1 t2 t1 or" evaluate
+ " t1 t0 0 sw" evaluate
+;
+: delay-ms ( ms -- )
+ d# 100.0000 * d# 830 + d# 1660 / " t0 set" evaluate
+ " begin t0 0 = until t0 -1 t0 addi" evaluate
+;
+resident
+
+label init-bonito ( -- ) \ Destroys: t0, t1 and t2
+ \ Bonito configuration registers
+\ h# 4020 bonponcfg bonito-clrbits \ little endian, enable cfg
+ h# 4000 bonponcfg bonito-clrbits \ little endian
+ h# 4040 bongencfg bonito-clrbits \ byte swap
+ h# 0410 bonponcfg bonito-setbits \ ROMCS0, arbiter
+
+ \ Bonito PCI configuration registers
+ h# 0600.0000 bonito-cfg-pa h# 08 + bonito! \ class
+ h# f900.0000 bonito-cfg-pa h# 04 + bonito! \ clear status
+ h# 0000.0000 bonito-cfg-pa h# 0c + bonito! \ latency timer
+ h# 0000.0000 bonito-cfg-pa h# 10 + bonito! \ pcibase0
+ h# 0000.0000 bonito-cfg-pa h# 14 + bonito! \ pcibase1
+ h# 0000.0000 bonito-cfg-pa h# 18 + bonito! \ pcibase2
+ h# 0000.0000 bonito-cfg-pa h# 30 + bonito! \ pciexprbase
+ h# 0000.0000 bonito-cfg-pa h# 3c + bonito! \ pciint
+ h# 0000.0047 bonito-cfg-pa h# 04 + bonito-setbits \ enable mem and I/O
+
+ \ Bonito configuration registers
+ h# 9302 bongencfg bonito-setbits \ I/O buffer
+ h# 0001 bongencfg bonito-clrbits \ disable debug
+
+ \ Reset PCI bus
+ h# 0000.0020 gpiodata bonito! \ pio_pcireset
+ h# ffff.ffcf gpioie bonito! \ pio_ie
+ 1 delay-ms
+ h# 0000.0020 gpiodata bonito-clrbits
+ d# 50 delay-ms
+
+ \ Other Bonito registers
+ h# 16e0 iodevcfg bonito-setbits \ cs
+
+ ra jr nop
+end-code
+
Added: cpu/mips/bonito/initcom1.fth
===================================================================
--- cpu/mips/bonito/initcom1.fth (rev 0)
+++ cpu/mips/bonito/initcom1.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,23 @@
+purpose: Initialize COM1 for startup messages
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+transient
+: isa-c! ( data isa-adr -- ) \ t0: isa-io-base
+ swap " t1 set" evaluate
+ " t1 t0 rot sb" evaluate
+;
+resident
+
+\ Initialize the 8250 (or compatible) COM1 serial port.
+label init-com1 ( -- ) \ Destroys t0 and t1
+ isa-io-base d# 16 >> t0 lui
+
+ \ SIOA
+ h# 3 h# 3fc isa-c! \ RTS and DTR on
+ h# 80 h# 3fb isa-c! \ Enable divisor latch
+ h# c h# 3f8 isa-c! \ Baud rate divisor low - 9600 baud
+ h# 0 h# 3f9 isa-c! \ Baud rate divisor high - 9600 baud
+ h# 3 h# 3fb isa-c! \ 8 bits, no parity
+
+ ra jr nop
+end-code
Added: cpu/mips/bonito/initsb.fth
===================================================================
--- cpu/mips/bonito/initsb.fth (rev 0)
+++ cpu/mips/bonito/initsb.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,59 @@
+purpose: Initialize SouthBridge for startup messages
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+h# 1000 constant sb-pci-addr
+transient
+: config-map ( reg -- )
+ pcimap_cfg " t0 set" evaluate
+ sb-pci-addr " t1 set" evaluate
+ " t1 t0 0 sw" evaluate
+ ( reg ) pci-cfg-pa + " t0 set" evaluate
+;
+: config-l! ( value reg -- )
+ config-map
+ ( value ) " t1 set" evaluate
+ " t1 t0 0 sw" evaluate
+;
+: config-w! ( value reg -- )
+ config-map
+ ( value ) " t1 set" evaluate
+ " t1 t0 0 sh" evaluate
+;
+: config-b! ( value reg -- )
+ config-map
+ ( value ) " t1 set" evaluate
+ " t1 t0 0 sb" evaluate
+;
+: pc@ ( reg -- ) \ t0: isa-io-base
+ ( reg ) " t0 swap t1 lbu" evaluate
+;
+: pc! ( data reg -- ) \ t0: isa-io-base
+ swap " t1 set" evaluate
+ ( reg ) " t1 t0 rot sb" evaluate
+;
+resident
+
+label init-southbridge ( -- ) \ Destroys: t0 and t1
+ h# fbfe.c001 h# 0b0 config-l! \ Set ISA mode
+ h# 0000.0000 h# 04e config-w! \ Disable RTC & KBD chip selects
+ h# 0000.000d h# 082 config-b! \ Enable PCI 2.1 timing support
+ h# 0000.00fe h# 069 config-b! \ Set top of memory to 16MB
+ h# 0000.0000 h# 0cb config-b! \ Disable internal RTC
+
+ smbus-base 1 + h# 390 config-l! \ Set SMB base address
+ h# 0000.0001 h# 3d2 config-b! \ Enable host controller
+ h# 0000.0001 h# 304 config-b! \ Enable I/O
+
+ isa-io-base d# 16 >> t0 lui
+
+[ifdef] notyet
+ \ Program ISA refresh counter
+ h# 43 pc@ \ Don't know why pmon code read this write-only reg
+ h# 74 h# 43 pc! \ Counter 1, r/w 0-7, 8-15, mode 1, binary
+ h# d6 h# 41 pc! \ Refresh timer
+ h# 00 h# 41 pc!
+[then]
+
+ ra jr nop
+end-code
+
Added: cpu/mips/bonito/initsio.fth
===================================================================
--- cpu/mips/bonito/initsio.fth (rev 0)
+++ cpu/mips/bonito/initsio.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,23 @@
+purpose: Initialize SuperI/O for startup messages
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+transient
+: sio-c! ( data reg -- ) \ t0: isa-io-base
+ ( reg ) " t1 set" evaluate
+ " t1 t0 h# 15c sb" evaluate
+ ( data ) " t1 set" evaluate
+ " t1 t0 h# 15d sb" evaluate
+;
+resident
+
+label init-sio ( -- ) \ Destroys: t0 and t1
+ isa-io-base d# 16 >> t0 lui
+
+ h# 06 h# 07 sio-c! \ Select com1
+ h# 03 h# 60 sio-c! \ At port 3f8
+ h# f8 h# 61 sio-c!
+ h# 01 h# 30 sio-c! \ Turn it on
+
+ ra jr nop
+end-code
+
Added: cpu/mips/bonito/intr.fth
===================================================================
--- cpu/mips/bonito/intr.fth (rev 0)
+++ cpu/mips/bonito/intr.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,19 @@
+purpose: Interrupt handlers
+copyright: Copyright 2001 FirmWorks All Rights Reserved
+
+headers
+hex
+
+: .intr-sw ( intr# -- ) ." Software Interrupt " u. cr ;
+: (intr-sw0) ( -- ) 0 .intr-sw ; ' (intr-sw0) to intr-sw0
+: (intr-sw1) ( -- ) 1 .intr-sw ; ' (intr-sw1) to intr-sw1
+
+: .intr-hw ( intr# -- ) ." Hardware Interrupt " u. cr ;
+' dispatch-interrupt to intr-hw0
+' dispatch-interrupt to intr-hw1
+: (intr-hw2) ( -- ) 2 .intr-hw ; ' (intr-hw2) to intr-hw2
+: (intr-hw3) ( -- ) 3 .intr-hw ; ' (intr-hw3) to intr-hw3
+: (intr-hw4) ( -- ) 4 .intr-hw ; ' (intr-hw4) to intr-hw4
+
+headers
+
Added: cpu/mips/bonito/isaio.fth
===================================================================
--- cpu/mips/bonito/isaio.fth (rev 0)
+++ cpu/mips/bonito/isaio.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,12 @@
+purpose: Access to ISA IO space
+copyright: Copyright 2000 Firmworks All Rights Reserved
+
+headers
+isa-io-base value io-base
+
+: pc@ ( offset -- n ) io-base + rb@ ;
+: pc! ( n offset -- ) io-base + rb! ;
+: pw@ ( offset -- n ) io-base + rw@ ;
+: pw! ( n offset -- ) io-base + rw! ;
+: pl@ ( offset -- n ) io-base + rl@ ;
+: pl! ( n offset -- ) io-base + rl! ;
Added: cpu/mips/bonito/mappci.fth
===================================================================
--- cpu/mips/bonito/mappci.fth (rev 0)
+++ cpu/mips/bonito/mappci.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,34 @@
+purpose: PCI physical address mapping to root node
+copyright: Copyright 1994-2001 FirmWorks All Rights Reserved
+
+hex
+
+headerless
+
+\ map-pci-phys creates a virtual mapping for the PCI physical address range
+\ "paddr io? size", returning its virtual address "vaddr". It does so by
+\ first translating the PCI physical base address "paddr io?" to the
+\ corresponding physical address in the parent node's address space (which
+\ is often the primary system bus address space, but in this case is the
+\ VL bus address space), and then calling the parent's "map-in" method.
+\ "io?" is false for PCI memory space, true for PCI I/O space.
+
+: map-pci-phys ( paddr io? phys.hi size -- vaddr )
+ -rot 2drop " map-in" $call-parent
+;
+
+\ >pci-devaddr translates the DMA address "parent-devaddr", which is in the
+\ parent node's physical address space, to the corresponding DMA address
+\ "pci-devaddr" in the PCI physical address space (in PCI memory space; DMA
+\ to PCI I/O space is not possible).
+
+: >pci-devaddr ( parent-devaddr -- pci-devaddr ) h# 0 + ;
+
+\ pci-devaddr> translates the DMA address "pci-devaddr", which is in the
+\ PCI physical address space (in PCI memory space; DMA to PCI I/O space is
+\ not possible), to the corresponding DMA address "parent-devaddr" in the
+\ parent node's physical address space.
+
+: pci-devaddr> ( pci-devaddr -- parent-devaddr ) h# 0 - ;
+headers
+
Added: cpu/mips/bonito/nvram.fth
===================================================================
--- cpu/mips/bonito/nvram.fth (rev 0)
+++ cpu/mips/bonito/nvram.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,51 @@
+purpose: Driver for upper RAM portion of the PC97307
+copyright: Copyright 2001 FirmWorks All Rights Reserved
+
+d# 128 value /nvram
+
+0 instance value nvram-ptr
+
+: nvram-bank-setup ( -- saved-a )
+ a rtc@
+ dup h# 8f and h# 30 or a rtc!
+;
+: nvram-bank-restore ( saved-a -- ) a rtc! ;
+: upper@ ( offset -- n ) 50 rtc! 53 rtc@ ;
+: upper! ( n offset -- ) 50 rtc! 53 rtc! ;
+
+: nvram@ ( offset -- n ) nvram-bank-setup >r upper@ r> nvram-bank-restore ;
+: nvram! ( n offset -- ) nvram-bank-setup >r upper! r> nvram-bank-restore ;
+' nvram@ to nv-c@
+' nvram! to nv-c!
+
+\ headers
+: clip-size ( adr len -- len' adr len' )
+ nvram-ptr + /nvram min nvram-ptr - ( adr len' )
+ tuck
+;
+: update-ptr ( len' adr -- len' )
+ drop dup nvram-ptr + to nvram-ptr
+;
+
+\ external
+: seek ( d.offset -- status )
+ 0<> over /nvram u> or if drop true exit then \ Seek offset too large
+ to nvram-ptr
+ false
+;
+: read ( adr len -- actual )
+ clip-size 0 ?do ( len' adr )
+ i nvram-ptr + nvram@ ( len' adr value )
+ over i + c! ( len' adr )
+ loop ( len' adr )
+ update-ptr
+;
+: write ( adr len -- actual )
+ clip-size 0 ?do ( len' adr )
+ dup i + c@ ( len' adr value )
+ i nvram-ptr + nvram! ( len' adr )
+ loop ( len' adr )
+ update-ptr ( len' )
+;
+: size ( -- d ) /nvram 0 ;
+
Added: cpu/mips/bonito/pcicfg.fth
===================================================================
--- cpu/mips/bonito/pcicfg.fth (rev 0)
+++ cpu/mips/bonito/pcicfg.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,32 @@
+purpose: Configuration space access using "configuration mechanism 1"
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+\ Ostensibly this applies to the PCI bus and thus should be in the PCI node.
+\ However, many of the host bridge registers are accessed via this mechanism,
+\ so it is convenient to make the configuration access words globally-visible.
+\ This mechanism works for several different PCI host bridges.
+
+headerless
+
+defer config-map
+: config-map-bonito ( config-adr -- port )
+ h# 00ff.ffff and dup >r h# 1.0000 < if
+ \ Type 0 cycle
+ 1 r@ h# f800 and d# 11 >> << ( idsel )
+ r> h# 7ff and or ( type0 )
+ lwsplit ( lo hi )
+ else
+ \ Type 1 cycle
+ r> lwsplit h# 1.0000 or ( lo hi )
+ then
+ pcimap_cfg ! pci-cfg-pa +
+;
+' config-map-bonito to config-map
+
+: config-l@ ( config-addr -- l ) config-map rl@ ;
+: config-l! ( l config-addr -- ) config-map rl! ;
+: config-w@ ( config-addr -- w ) config-map rw@ ;
+: config-w! ( w config-addr -- ) config-map rw! ;
+: config-b@ ( config-addr -- c ) config-map rb@ ;
+: config-b! ( c config-addr -- ) config-map rb! ;
+
Added: cpu/mips/bonito/pcinode.fth
===================================================================
--- cpu/mips/bonito/pcinode.fth (rev 0)
+++ cpu/mips/bonito/pcinode.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,79 @@
+purpose: System-specific portions of PCI bus package
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+: init ( -- ) ;
+
+d# 33,333,333 " clock-frequency" integer-property
+
+\ Establish limits for address space allocation
+
+h# 1000.0000 to first-mem \ 1000.0000 - 1bff.ffff
+h# 1c00.0000 to mem-space-top \ Top of area available for PCI memory
+
+h# 0000.1000 to first-io \ Avoid on-board ISA I/O devices
+h# 0000.f000 to io-space-top \ And SouthBridge's SMBUS base address
+
+\ The phys.hi component of the PCI addresses below indicate the
+\ address space type (I/O = 0100.0000, Mem = 0200.0000, etc.)
+
+\ -----------PCI Address--- --Sys Addr-- ------size-----
+\ phys.hi .mid .low phys.hi .hi .lo
+
+0 0 encode-bytes
+ 0000.0000 +i 0+i 0+i bfe8.0000 +i 0+i 8.0000 +i \ PCI Cfg
+ 0100.0000 +i 0+i 0+i bfd0.0000 +i 0+i 0010.0000 +i \ ISA I/O
+ 0200.0000 +i 0+i 0+i 9000.0000 +i 0+i 0c00.0000 +i \ PCI Mem
+" ranges" property
+
+\ These package methods use the global versions of the configuration
+\ access words.
+
+: config-l@ ( config-addr -- l ) config-l@ ;
+: config-l! ( l config-addr -- ) config-l! ;
+: config-w@ ( config-addr -- w ) config-w@ ;
+: config-w! ( w config-addr -- ) config-w! ;
+: config-b@ ( config-addr -- c ) config-b@ ;
+: config-b! ( c config-addr -- ) config-b! ;
+
+fload ${BP}/dev/pci/intmap.fth \ Generic interrupt mapping code
+
+\ This table describes the wiring of PCI interrupt pins at the PCI slots
+\ to ISA IRQs.
+
+create slot-map
+\ Dev# Pin A Pin B Pin C Pin D
+ 18 c, 0 c, 1 c, 2 c, 3 c, \ PCI slot 2 (P9)
+ 19 c, 1 c, 2 c, 3 c, 0 c, \ PCI slot 3 (P10)
+ 1a c, 2 c, 3 c, 0 c, 1 c, \ PCI slot 4 (P11)
+ 1b c, 2 c, ff c, ff c, ff c, \ Ethernet
+ 1c c, 0 c, 1 c, 2 c, 3 c, \ South Bridge
+ 1d c, 3 c, 0 c, 1 c, 2 c, \ PCI slot 1 (P8)
+ ff c, \ End of list
+
+h# f800 encode-int \ Mask of implemented slots
+" PCI1" encode-string encode+
+" PCI2" encode-string encode+
+" PCI3" encode-string encode+
+" PCI4" encode-string encode+
+" slot-names" property
+
+also forth definitions
+" 1b,1d,18,19,1a" dup config-string pci-probe-list
+previous definitions
+
+warning @ warning off
+\ The io-base handling really ought to be in the root node, but
+\ that would require more changes than I'm willing to do at present.
+: map-out ( vaddr size -- )
+ over io-base u>= if 2drop exit then ( vaddr size )
+ map-out ( )
+;
+warning !
+
+: bonito-function-present? ( phys.hi.func -- flag )
+ bonito-cfg-pa 6 + dup w@ over w! \ Clear errors
+ swap " config-l@" $call-self drop
+ w@ h# 2000 and 0= \ Return true if not Master-Abort
+;
+' bonito-function-present? to function-present?
+
Added: cpu/mips/bonito/physaddr.fth
===================================================================
--- cpu/mips/bonito/physaddr.fth (rev 0)
+++ cpu/mips/bonito/physaddr.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,78 @@
+purpose: Physical addresses for the Bonito
+copyright: Copyright 2000 FirmWorks All Rights Reserved
+
+headerless
+
+h# 0000.0000 constant ram-pa
+h# 1000.0000 constant pci-lo0-pa
+h# 1400.0000 constant pci-lo1-pa
+h# 1800.0000 constant pci-lo2-pa
+h# 1c00.0000 constant rom-pa1
+h# 1f80.0000 constant rom-pa0
+h# 1fc0.0000 constant rom-pa
+h# 1fd0.0000 constant pci-io-pa
+h# 1fe0.0000 kseg1 + constant bonito-cfg-pa
+h# 1fe0.0100 kseg1 + constant bonito-reg-pa
+h# 1fe8.0000 kseg1 + constant pci-cfg-pa
+h# 1ff0.0000 constant io0-pa
+h# 1ff4.0000 constant io1-pa
+h# 1ff8.0000 constant io2-pa
+h# 1ffc.0000 constant io3-pa
+
+pci-io-pa kseg1 + constant isa-io-base
+
+h# 0200.0000 constant /ram-bank
+
+h# 400 constant /resetjmp
+[ifdef] ram-image
+h# 20.0000 constant rom-base
+h# 10.0000 constant /rom
+rom-base kseg0 + constant rom-pa
+[else]
+0 constant rom-base
+h# 8.0000 constant /rom
+rom-pa kseg1 + constant rom-pa
+[then]
+rom-pa /resetjmp + constant dropin-base
+
+h# f000 constant smbus-base \ offset into isa-io-base
+
+io2-pa kseg1 + constant ide0-pa
+io3-pa kseg1 + constant ide1-pa
+
+\ Bonito registers
+h# 00 bonito-reg-pa + constant bonponcfg
+h# 04 bonito-reg-pa + constant bongencfg
+h# 08 bonito-reg-pa + constant iodevcfg
+h# 0c bonito-reg-pa + constant sdcfg
+h# 10 bonito-reg-pa + constant pcimap
+h# 14 bonito-reg-pa + constant pcimembasecfg
+h# 18 bonito-reg-pa + constant pcimap_cfg
+h# 1c bonito-reg-pa + constant gpiodata
+h# 20 bonito-reg-pa + constant gpioie
+h# 24 bonito-reg-pa + constant intedge
+h# 28 bonito-reg-pa + constant intsteer
+h# 2c bonito-reg-pa + constant intpol
+h# 30 bonito-reg-pa + constant intenset
+h# 34 bonito-reg-pa + constant intenclr
+h# 38 bonito-reg-pa + constant inten
+h# 3c bonito-reg-pa + constant intisr
+h# 40 bonito-reg-pa + constant pcimail0
+h# 44 bonito-reg-pa + constant pcimail1
+h# 48 bonito-reg-pa + constant pcimail2
+h# 4c bonito-reg-pa + constant pcimail3
+h# 50 bonito-reg-pa + constant pcicachectrl
+h# 54 bonito-reg-pa + constant pcicachetag
+h# 58 bonito-reg-pa + constant pcibadaddr
+h# 5c bonito-reg-pa + constant pcimstat
+h# 100 bonito-reg-pa + constant ldmactrl
+h# 100 bonito-reg-pa + constant ldmastat
+h# 104 bonito-reg-pa + constant ldmaaddr
+h# 108 bonito-reg-pa + constant ldmago
+h# 200 bonito-reg-pa + constant copctrl
+h# 200 bonito-reg-pa + constant copstat
+h# 204 bonito-reg-pa + constant coppaddr
+h# 208 bonito-reg-pa + constant copdaddr
+h# 20c bonito-reg-pa + constant copgo
+
+headers
Added: cpu/mips/bonito/report.fth
===================================================================
--- cpu/mips/bonito/report.fth (rev 0)
+++ cpu/mips/bonito/report.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,30 @@
+also forth definitions
+[ifdef] debug-reset
+: ?report ( char -- )
+ " isa-io-base d# 16 >> t0 lui" evaluate
+ " begin t0 h# 3fd t1 lbu t1 h# 20 t1 andi t1 0 <> until nop" evaluate
+ ( char ) " t1 set t1 t0 h# 3f8 sb " evaluate
+;
+[else]
+: ?report ( char -- ) drop ;
+[then]
+
+: putbyte ( $a0 -- )
+ " $a0 h# f $a0 andi $a0 h# 30 $a0 addi" evaluate
+ " begin t0 h# 3fd t1 lbu t1 h# 20 t1 andi t1 0 <> until nop" evaluate
+ " $a0 t0 h# 3f8 sb " evaluate
+ " begin t0 h# 3fd t1 lbu t1 h# 20 t1 andi t1 0 <> until nop" evaluate
+;
+: dot ( a0 -- )
+ " isa-io-base t0 set $a0 t2 move" evaluate
+ " t2 d# 28 $a0 srl putbyte" evaluate
+ " t2 d# 24 $a0 srl putbyte" evaluate
+ " t2 d# 20 $a0 srl putbyte" evaluate
+ " t2 d# 16 $a0 srl putbyte" evaluate
+ " t2 d# 12 $a0 srl putbyte" evaluate
+ " t2 d# 8 $a0 srl putbyte" evaluate
+ " t2 d# 4 $a0 srl putbyte" evaluate
+ " t2 0 $a0 srl putbyte" evaluate
+;
+previous definitions
+
Added: cpu/mips/bonito/reset.bth
===================================================================
--- cpu/mips/bonito/reset.bth (rev 0)
+++ cpu/mips/bonito/reset.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,448 @@
+purpose: Low-level startup code for MIPS
+copyright: Copyright 1998-2001 Firmworks All Rights Reserved
+
+command: &native &this
+build-now
+
+create debug-reset \ Comment out in order to single step under PMON
+\ create ram-image \ Comment out to build rom image
+
+\needs start-assembling fload ${BP}/cpu/mips/asmtools.fth
+\needs write-dropin fload ${BP}/forth/lib/mkdropin.fth
+
+hex
+
+fload ${BP}/cpu/mips/ksegaddr.fth
+fload ${BP}/cpu/mips/bonito/physaddr.fth
+fload ${BP}/cpu/mips/bonito/report.fth
+
+h# 10.0000 constant /fw-memory
+
+[ifdef] ram-image
+rom-base kseg0 + constant bootrom-pa
+[else]
+rom-pa constant bootrom-pa
+[then]
+
+also forth definitions
+: c$, ( adr len -- )
+ 1+ here swap note-string dup allot move 4 (align)
+;
+previous definitions
+
+also mips-assembler definitions
+: $find-dropin, ( adr len -- )
+[ifdef] notdef
+ tuck 2>r ( len )
+ here + 9 + \ 9 = null(1) + call+delay slot(8)
+ 4 round-up \ pad string end adr to next instr-+
+ ( adr-of-find-di ) asm( $0 bgezal )asm \ jump to find-dropin call below |
+ asm( ra $a0 move )asm \ set string arg for find-dropin |
+ 2r> c$, \ place string |
+ " find-dropin bal" evaluate \ and call find routine <----+
+ asm( nop )asm
+[else]
+ " find-dropin bal nop" evaluate \ call find routine
+ c$, \ place string after delay slot
+[then]
+;
+previous definitions
+
+h# 800e.0000 constant stack-offset
+h# 800f.0000 constant workspace-offset
+h# 8010.0000 constant inflate-offset
+
+start-assembling
+
+/resetjmp h# 20 + to asm-origin \ Skip resetjmp wad and dropin header
+
+label my-entry
+\ **** This is the primary entry point; it will contain a branch instruction
+\ that skips a few subroutines and lands at the startup sequence. That
+\ branch instruction is patched in below. The entry point for this module
+\ is in turn reached from a branch instruction at the beginning of the ROM,
+\ which is created by the file arch/dna/resetvec.bth
+ 0 , \ To be patched later
+ nop
+end-code
+
+\ This subroutine is used by the startup code.
+\ It compares two null-terminated strings, returning zero if they match.
+\ Destroys: r2, r3
+label strcmp ( $a0: str1 $a1: str2 -- v0: 0 if match, nonzero if mismatch )
+ $a0 t0 move
+ begin
+ t0 0 $a2 lbu
+ $a1 0 $a3 lbu
+ $a2 $a3 <> if
+ t0 1 t0 addiu \ (delay)
+ ra jr
+ $a3 $a2 v0 sub \ (delay)
+ then
+ $a2 0 = until
+ $a1 1 $a1 addiu \ (delay)
+
+ ra jr
+ 0 v0 set \ (delay)
+end-code
+
+\ This subroutine is used by the startup code.
+\ It searches the ROM for a dropin module whose name field matches the
+\ null-terminated string that is at the return address.
+\ Destroys: $a0-$a3, t4-t7
+label find-dropin ( -- v0: adr | 0 )
+ ra $a0 move \ address of string
+ begin
+ ra 0 $a1 lbu \ Get string byte
+ $a1 0 = until \ Look for null terminator
+ ra 1 ra addiu \ (delay) Advance to next character
+
+ \ ra now points to the byte after the null character
+ ra 3 ra addiu \ Round up to longword boundard
+ 3 invert $at set
+ ra $at t7 and \ and round
+
+\ h# 4f424d44 t4 set \ "OBMD"
+ h# 444d424f t4 set \ "OBMD" little-endian
+ bootrom-pa /resetjmp + t5 set \ ROM base + (resetjmp wad)
+ begin
+ t5 0 t6 lw
+ t4 t6 = while nop
+
+ strcmp bal \ $a1 = test$, $a0 = sought$
+ t5 h# 10 $a1 addiu \ (delay)point to dropin name in header
+ v0 0 = if nop
+ t7 jr \ return
+ t5 v0 move \ (delay) return value is adr of "OBMD"
+ then
+
+ t5 4 t3 addiu \ offset to size of dropin
+ t3 1 t0 lwr \ get size of dropin (big-endian)
+ t3 3 t0 lwr \ get least significant half word
+ h# ffff t1 set
+ t0 t1 t6 and
+
+ t3 2 t0 lwl \ get most significant half word
+ t3 0 t0 lwl
+ h# ffff.0000 t1 set
+ t0 t1 t0 and
+ t0 t6 t6 or
+
+ t6 h# 23 t6 addiu \ add size + header(20) + roundup(3) to
+ t5 t6 t5 addu \ locate next dropin
+ 3 invert $at set
+ repeat
+ t5 $at t5 and \ (delay) round up
+
+ 0 v0 set \ return value is 0 (failure)
+ t7 jr \ No more dropins; return
+ nop
+end-code
+
+\ This subroutine is used by the startup code.
+\ It copies n (a2) bytes of memory from src (a1) to dst (a0)
+\ Destroys: a0-a3
+label memcpy ( a0: dst a1: src a2: n -- )
+ $a0 $a2 $a2 addu \ Ending address
+
+ $a0 $a2 <> if nop
+ begin
+ $a1 0 $a3 lbu
+ $a1 1 $a1 addiu
+ $a3 $a0 0 sb
+ $a0 $a2 = until
+ $a0 1 $a0 addiu \ (delay)
+ then
+
+ ra jr nop
+end-code
+here memcpy - constant /memcpy
+
+\ Flush the VR4300 Data cache for the first time
+label init-cache ( -- ) \ Destroys: $a0, $a1
+
+ \ Temporarily disable parity and CE
+ d# 12 v0 mfc0
+
+ h# 2.0000 invert t0 set
+ t0 v0 t0 and
+ h# 1.0000 t1 set
+ t0 t1 t0 or
+ d# 12 t0 mtc0
+
+ \ Disable secondary cache
+ d# 16 t0 mfc0
+ h# 103f invert t1 set
+ t0 t1 t0 and
+ d# 16 t0 mtc0
+ t0 h# 33 t0 ori \ CONFIG, k0=write back
+ d# 16 t0 mtc0
+ nop nop nop nop
+
+ \ load valid virtual addresses into the cache tags
+ d# 28 $0 mtc0 \ Set CP0 TAGLO register
+ d# 29 $0 mtc0 \ Set CP0 TAGHI register
+
+ h# 8000.0000 $a0 set
+ d# 1024 d# 32 * $a1 set
+ $a0 $a1 $a1 addu \ Add cache size to give end address
+
+ \ Init Icache
+ begin
+ $a0 0 h# 8 cache \ Index store tag primary icache
+ nop
+ $a0 0 h# 14 cache \ Fill Icache
+ nop
+ $a0 0 h# 8 cache \ Index store tag primary icache
+ nop
+ $a1 $a0 = until
+ $a0 d# 32 $a0 addiu \ Icache line size
+
+ \ Init Dcache
+ h# 8000.0000 $a0 set
+ d# 1024 d# 32 * $a1 set
+ $a0 $a1 $a1 addu \ Add cache size to give end address
+ begin
+ $a0 0 h# 9 cache \ Index store tag primary dcache
+ $a1 $a0 = until
+ $a0 d# 32 $a0 addiu \ Dcache line size
+
+ h# 8000.0000 $a0 set
+ d# 1024 d# 32 * $a1 set
+ $a0 $a1 $a1 addu \ Add cache size to give end address
+ begin
+ $0 $a0 0 sw \ Zero cache
+ $a1 $a0 = until
+ $a0 d# 32 $a0 addiu \ Dcache line size
+
+ h# 8000.0000 $a0 set
+ d# 1024 d# 32 * $a1 set
+ $a0 $a1 $a1 addu \ Add cache size to give end address
+ begin
+ $a0 0 h# 9 cache \ Index store tag primary dcache
+ $a1 $a0 = until
+ $a0 d# 32 $a0 addiu \ Dcache line size
+
+ \ Restore status register
+ d# 12 v0 mtc0
+
+ ra jr nop
+end-code
+
+\ Write-back and invalidate the VR4300 data cache.
+label flush-dcache ( -- ) \ Destroys: $a0, $a1
+ h# 8000.0000 $a1 set
+ d# 1024 d# 32 * $a0 set
+ $a1 $a0 $a0 addu \ Add cache size to give end address
+
+ begin
+\ d# 28 $0 mtc0 \ Set CP0 TAGLO register
+ nop
+ $a1 0 h# 1 cache \ op 0/1(1): index wb&invalidate primary dcache
+ nop
+ $a0 $a1 = until
+ $a1 d# 32 $a1 addiu \ Dcache line size
+
+ ra jr nop
+end-code
+
+\ Invalidate the VR4300 instruction cache.
+label invalidate-icache ( -- ) \ Destroys: $a0, $a1
+ h# 8000.0000 $a1 set
+ d# 1024 d# 32 * $a0 set
+ $a1 $a0 $a0 addu \ Add cache size to give end address
+
+ begin
+\ d# 28 $0 mtc0 \ Set CP0 TAGLO register
+ nop
+ $a1 0 h# 0 cache \ op 0/0(0): index invalidate primary icache
+ nop
+ $a0 $a1 = until
+ $a1 d# 32 $a1 addiu \ Dcache line size
+
+ ra jr nop
+end-code
+
+label sync-cache ( -- ) \ Destroys: $a0, $a1, $a3
+ ra $a3 move
+
+ flush-dcache bal nop
+ invalidate-icache bal nop
+
+ $a3 jr nop
+end-code
+
+[ifndef] ram-image
+fload ${BP}/cpu/mips/bonito/initbon.fth
+fload ${BP}/cpu/mips/bonito/initsb.fth
+fload ${BP}/cpu/mips/bonito/initsio.fth
+fload ${BP}/cpu/mips/bonito/initcom1.fth
+[then]
+
+\ This is the main entry point for this dropin module
+label start
+
+[ifndef] ram-image
+ \ Jump up to KSEG1
+ start asm-base - asm-origin + bootrom-pa + h# 10 + k0 la
+ k0 jr nop
+
+ \ Initialize CP0 registers
+ d# 12 v1 mfc0
+ h# 2041.0000 v0 li \ SR_BEV, disable parity
+ v0 v1 v0 or
+ d# 12 v0 mtc0 \ Set CP0 status register
+ d# 13 $0 mtc0 \ Set CP0 cause register
+ d# 18 $0 mtc0 \ Set CP0 WATCHLO register
+ d# 19 $0 mtc0 \ Set CP0 WATCHHI register
+
+ \ Initialize hardware
+ init-bonito bal nop
+ init-southbridge bal nop
+ init-sio bal nop
+ init-com1 bal nop
+[then]
+
+carret ?report
+linefeed ?report
+
+ascii A ?report
+ " start" $find-dropin, \ Assemble call to find-dropin w/literal arg
+ v0 0 = if
+ nop
+ascii Y ?report
+ begin again nop
+ then
+
+ v0 h# 20 v0 addi
+ v0 ra jalr
+ nop
+
+ v0 s2 move \ Save RAM top
+ /fw-memory h# 20 + s0 set \ Compute firmware RAM base address
+ v0 s0 s0 sub
+
+ init-cache bal nop nop nop nop
+
+ascii B ?report
+ " firmware" $find-dropin, \ Assemble call to find-dropin w/literal arg
+
+ v0 0 = if
+ nop
+ascii Z ?report
+ begin again nop
+ then
+
+ascii C ?report
+
+ v0 s1 move \ Save address of firmware dropin
+ v0 h# c t0 lw \ see if compressed
+ t0 0 <> if
+ nop
+ \ The firmware dropin is compressed, so we load the inflater into RAM
+ \ and use it to inflate the firmware into RAM
+
+ " inflate" $find-dropin,
+
+ascii i ?report
+
+ v0 4 t3 addiu \ offset to length of inflater
+ t3 1 t0 lwr \ get size of dropin (big-endian)
+ t3 3 t0 lwr \ get least significant half word
+ h# ffff t1 set
+ t0 t1 $a2 and
+
+ t3 2 t0 lwl \ get most significant half word
+ t3 0 t0 lwl
+ h# ffff.0000 t1 set
+ t0 t1 t0 and
+ t0 $a2 $a2 or
+
+ v0 h# 20 $a1 addi \ src: Base addr of inflater code in ROM
+ inflate-offset $a0 set \ dst: Base address of inflater
+ memcpy bal \ Copy the inflater
+ nop
+
+ sync-cache bal
+ nop
+
+ascii n ?report
+
+ stack-offset sp set \ stack for inflater
+ s0 $a1 move \ Firmware RAM address
+ workspace-offset $a2 set \ Scratch RAM for inflater
+ inflate-offset t9 set \ RAM address of inflater
+ s1 h# 20 $a0 addi \ Adr of comp'd bits of firmware dropin
+ t9 ra jalr \ inflate the firmware
+ nop
+
+ascii f ?report begin again
+
+ else
+ nop
+
+ascii c ?report
+ \ The firmware dropin isn't compressed, so we just copy it to RAM
+ascii o ?report
+
+ s1 4 t3 addiu \ offset to length of firmware
+ t3 1 t0 lwr \ get size of dropin (big-endian)
+ t3 3 t0 lwr \ get least significant half word
+ h# ffff t1 set
+ t0 t1 $a2 and
+
+ t3 2 t0 lwl \ get most significant half word
+ t3 0 t0 lwl
+ h# ffff.0000 t1 set
+ t0 t1 t0 and
+ t0 $a2 $a2 or
+
+ s1 h# 20 $a1 addi \ src: Skip dropin header
+ s0 $a0 move \ dst: Firmware RAM address
+
+ memcpy bal \ Copy the firmware
+ nop
+
+ascii p ?report
+ascii y ?report
+
+ then
+
+ sync-cache bal nop
+
+ \ Jump to Forth (prom-cold-code)
+ s0 h# 20 s0 addiu
+ s0 $a0 move \ fw-RAM-base
+ s2 $a1 move \ fw-RAM-size
+ s0 0 t0 lw \ Read offset of prom-cold-code
+ s0 t0 s0 addu
+
+ d# 12 t0 mfc0 \ Status
+ t0 4 t0 andi \ ERL=1 if reset exception
+ t0 0 = if
+ nop
+ s0 jr
+ nop
+ else
+ nop
+ d# 30 s0 mtc0 nop nop nop nop nop
+ d# 14 s0 mtc0 nop nop nop nop nop
+ eret
+ nop
+ then
+
+ \ Not reached, in theory
+ begin again
+ nop
+
+end-code
+
+also mips-assembler
+start my-entry put-branch
+previous
+
+end-assembling
+
+writing reset.di
+asm-base here over - 0 " reset" write-dropin
+ofd @ fclose
Added: cpu/mips/bonito/resetjmp.bth
===================================================================
--- cpu/mips/bonito/resetjmp.bth (rev 0)
+++ cpu/mips/bonito/resetjmp.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,92 @@
+purpose: Reset vector handler
+copyright: Copyright 2000-2001 Firmworks All Rights Reserved
+
+command: &native &this
+build-now
+
+\needs start-assembling fload ${BP}/cpu/mips/asmtools.fth
+
+\ The size of this module affects the constant /resetjmp in
+\ physaddr.fth.
+
+create debug-reset
+
+fload ${BP}/cpu/mips/ksegaddr.fth
+fload ${BP}/cpu/mips/bonito/physaddr.fth
+fload ${BP}/cpu/mips/bonito/report.fth
+
+start-assembling
+
+hex
+
+label resetvec
+ \ **** This is the initial entry point (reset vector) for the ROM.
+ \ It just branches past the following copyright string and past the
+ \ dropin module header for the "resetvec" dropin module, landing at
+ \ the entry point for that module. The "resetvec" dropin module
+ \ must appear in the ROM image right after the image that this file
+ \ creates.
+ here /resetjmp + h# 20 + $0 $0 beq
+ nop
+
+end-code
+
+ \ This copyright string will appear in the ROM right after the branch
+ \ instruction.
+ " Copyright 2001 FirmWorks All Rights Reserved" c$,
+
+ \ Locations 56-5b are reserved for a MAC address, for systems
+ \ that wish to store the MAC address in the boot ROM instead of
+ \ in a UID EEPROM.
+ h# 56 pad-to
+ h# ff c, h# ff c, h# ff c, h# ff c, h# ff c, h# ff c,
+
+ \ We reserve ROM locations 5c-5f for the PROMICE AI port and place
+ \ a distinct signature there. If the AI port is present and enabled
+ \ at those locations, it will overlay the ROM contents, thus allowing
+ \ the software to determine whether or not the AI port is present.
+
+ \ The signature should be tested at offset 5c+3 (5f), which is the
+ \ AI port status register. The value d4 is present at both 5c+0
+ \ and 5c+3, in case we ever have to handle big-endian systems that
+ \ byte-swap the ROM in some modes.
+
+ h# 5c pad-to \ Pad to the location reserved for the AI port
+ h# d4 c, h# 5a c, h# 5b c, h# d4 c, \ Signature distinct from AI port
+
+ h# 200 pad-to
+label tlbrefill
+ ascii T ?report ascii L ?report ascii B ?report
+ begin again
+ nop
+end-code
+
+ h# 280 pad-to
+label xtlbrefill
+ ascii X ?report ascii T ?report ascii L ?report ascii B ?report
+ begin again
+ nop
+end-code
+
+ h# 300 pad-to
+label cacheerr
+ ascii C ?report ascii E ?report ascii r ?report ascii r ?report
+ begin again
+ nop
+end-code
+
+ h# 380 pad-to
+label generalexc
+ ascii G ?report ascii e ?report ascii n ?report
+ begin again
+ nop
+end-code
+
+ /resetjmp pad-to
+ \ This module must have a fixed size of /resetjmp
+
+end-assembling
+
+writing resetjmp.img
+asm-base here over - ofd @ fputs
+ofd @ fclose
Added: cpu/mips/bonito/rom.bth
===================================================================
--- cpu/mips/bonito/rom.bth (rev 0)
+++ cpu/mips/bonito/rom.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,31 @@
+purpose: Top-level build script for Bonito ROM
+copyright: Copyright 2001 FirmWorks All Rights Reserved
+
+command: &native &this
+in: resetjmp.img
+in: reset.di
+in: start.di
+in: fw.img
+in: ${BP}/dev/dec21140/build/comet.fc
+in: ${BP}/dev/dec21140/build/netgear.fc
+in: ${BP}/dev/kendin/build/ks8723.fc
+in: ${BP}/dev/usb/ohci/build/ohci.fc
+build-now
+
+\needs $add-dropin fload ${BP}/tools/mkdropin.fth
+
+\ Always re-create the builton.fth file when we make a new rom.img
+fload ${BP}/arch/mips/builton.bth
+
+writing rom.img
+ " resetjmp.img" $add-file \ Branch past initial dropin module header
+ " reset.di" $add-file
+ " start.di" $add-file
+ " fw.img" " firmware" $add-deflated-dropin
+ " ${BP}/cpu/mips/inflate.img" " inflate" $add-dropin
+ " builton.fth" " probe-" $add-dropin
+ " ${BP}/dev/dec21140/build/comet.fc" " pci1317,985" $add-deflated-dropin
+ " ${BP}/dev/dec21140/build/netgear.fc" " pci11ad,2" $add-deflated-dropin
+ " ${BP}/dev/kendin/build/ks8723.fc" " pci1186,1002" $add-deflated-dropin
+ " ${BP}/dev/usb/ohci/build/ohci.fc" " pci1045,c861" $add-deflated-dropin
+ofd @ fclose
Added: cpu/mips/bonito/rootnode.fth
===================================================================
--- cpu/mips/bonito/rootnode.fth (rev 0)
+++ cpu/mips/bonito/rootnode.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,128 @@
+purpose: Methods for the root node using Bonito Kseg address translation
+copyright: Copyright 1998-2001 Firmworks All Rights Reserved
+
+: root-map-in ( phys len -- virt )
+ " /" " map-in" execute-device-method drop
+;
+: root-map-out ( virt len -- )
+ " /" " map-out" execute-device-method drop
+;
+
+dev /
+extend-package
+
+1 encode-int " #address-cells" property
+
+0 0 encode-bytes
+ \ Base address size
+ h# 8000.0000 encode-int encode+ h# 0200.0000 encode-int encode+
+" dma-ranges" property
+
+hex
+headers
+
+\ Static methods
+: decode-unit ( adr len -- phys ) push-hex $number if 0 then pop-base ;
+: encode-unit ( phys -- adr len ) push-hex (u.) pop-base ;
+
+\ Not-necessarily-static methods
+: open ( -- true ) true ;
+: close ( -- ) ;
+
+: map-in ( phys size -- virt )
+ drop dup 1000.0000 u< if
+ bfd0.0000 or
+ else
+ dup 8000.0000 u< if h# b000.0000 or then
+ then
+;
+: map-out ( virtual size -- ) 2drop ;
+
+headerless
+list: dmalist
+listnode
+ /n field >dma-ua \ address obtained from alloc-mem, unaligned
+ /n field >dma-aa \ address passed on to caller, cache-line aligned
+ /n field >dma-len \ original length used to alloc-mem
+nodetype: dmanode
+
+0 dmalist !
+0 dmanode !
+0 value dma-aa
+
+: dma-aa=? ( node -- aa=? )
+ >dma-aa @ dma-aa =
+;
+: find-dmanode? ( -- prev-node this-node | 0 )
+ dmalist ['] dma-aa=? find-node
+;
+: alloc-dmanode ( -- node )
+ dmanode allocate-node dup dmalist last-node insert-after
+;
+: free-dmanode ( prev -- )
+ delete-after dmanode free-node
+;
+
+headers
+
+\ DMA memory is accessed via kseg1 on a cache line boundary in integral # of cache lines
+: dma-alloc ( size -- virt )
+ /cache-line + /cache-line round-up dup ( size' size' )
+ alloc-mem 2dup swap flush-d$-range ( size ua )
+ dup /cache-line round-up kseg1 or ( size ua aa )
+ dup >r ( size ua aa ) ( R: aa )
+ alloc-dmanode ( size ua aa node ) ( R: aa )
+ tuck >dma-aa ! ( size ua node ) ( R: aa )
+ tuck >dma-ua ! ( size node ) ( R: aa )
+ >dma-len ! ( ) ( R: aa )
+ r>
+;
+: dma-free ( virt size -- )
+ over to dma-aa find-dmanode? ?dup if
+ dup >dma-ua @ swap >dma-len @ free-mem
+ free-dmanode 2drop
+ else
+ free-mem
+ then
+;
+: dma-map-in ( virt size cacheable -- devaddr )
+ drop 2dup pcicache-wbinv
+ drop h# 1fff.ffff and
+;
+: dma-map-out ( virt devaddr size -- ) pcicache-wbinv drop ;
+: dma-sync ( virt devaddr size -- ) pcicache-wbinv drop ;
+: dma-push ( virt devaddr size -- ) pcicache-inv drop ;
+: dma-pull ( virt devaddr size -- ) pcicache-wbinv drop ;
+
+finish-device
+
+device-end
+
+headerless
+\ Call this after the system-mac-address is determined, which is typically
+\ done near the end of the probing process.
+: set-system-id ( -- )
+ system-mac-address dup if ( adr 6 )
+ " /" find-device ( adr 6 )
+
+ \ Convert the six bytes of the MAC address into a string of the
+ \ form 0NNNNNNNNNN, where N is an uppercase hex digit.
+ push-hex ( adr 6 )
+
+ <# bounds swap 1- ?do ( )
+ i c@ u# u# drop ( )
+ -1 +loop ( )
+ 0 u# u#> ( adr len )
+
+ 2dup upper ( adr len ) \ Force upper case
+
+ pop-base ( adr len )
+
+ encode-string " system-id" property ( )
+
+ device-end
+ else
+ 2drop
+ then
+;
+headers
Added: cpu/mips/bonito/start.bth
===================================================================
--- cpu/mips/bonito/start.bth (rev 0)
+++ cpu/mips/bonito/start.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,219 @@
+purpose: Low-level startup code for Bonito
+copyright: Copyright 2001 Firmworks. All Rights Reserved.
+
+command: &native &this
+build-now
+
+\needs start-assembling fload ${BP}/cpu/mips/asmtools.fth
+\needs write-dropin fload ${BP}/forth/lib/mkdropin.fth
+
+create debug-reset
+\ create hard-code-memory
+
+fload ${BP}/cpu/mips/ksegaddr.fth
+fload ${BP}/cpu/mips/bonito/physaddr.fth
+fload ${BP}/cpu/mips/bonito/report.fth
+
+start-assembling
+
+label my-entry
+ 0 , \ To be patched later
+ nop
+end-code
+
+label i2creset ( -- )
+ ra jr nop
+end-code
+
+label i2cread ( a0: DIMM# a1: reg# -- v0: value ) \ Destroy t0-t3
+ smbus-base isa-io-base + t0 set
+
+ $a0 1 t1 sll
+ t1 h# a1 t1 ori \ DIMM base address and read bit
+ t1 t0 4 sb
+ $a1 t0 3 sb \ Command
+
+ h# 48 t1 set \ SMB_START SMB_BDRW
+ t1 t0 2 sb
+
+ d# 10000 t3 set
+ begin
+ t0 0 t1 lbu \ Status
+ t1 h# 1e t2 andi \ failed, bus_err, dev_err, interrupt, ok
+ t3 -1 t3 addi
+ t2 0 <> if
+ nop 0 t3 set
+ then
+ t3 0 = until
+ nop
+
+ t1 t0 0 sb \ Clear pending errors/interrupts
+ t1 h# 1c t2 andi
+ -1 v0 set
+ t2 0 = if
+ nop
+ t0 5 v0 lbu
+ then
+
+ ra jr nop
+end-code
+
+transient
+: nodimm ( -- )
+ " nop" evaluate
+ " 0 v0 set" evaluate
+ " h# 40 v1 set" evaluate \ BONITO_SDCFG_AABSENT
+ " $a0 0 <> if nop v1 8 v1 sll then s6 jr nop" evaluate
+;
+resident
+
+label size-dimm ( a0: DIMM# -- v0: size v1: shape )
+ ra s6 move
+
+ 0 t8 set
+ 0 t9 set
+
+ 2 $a1 set
+ i2cread bal nop \ DIMM type
+ 4 t0 set
+ v0 t0 <> if nodimm then
+
+ d# 31 $a1 set
+ i2cread bal nop \ size per side
+ v0 0 = if nodimm then
+ v0 d# 22 t8 sll \ multiply by 4 MB
+
+ 3 $a1 set
+ i2cread bal nop \ # of rows
+ v0 d# -11 v0 addi
+ v0 -4 t0 addi
+ t0 0> if nodimm then
+ v0 03 v0 andi \ arowbits
+ t9 v0 t9 or
+
+ 4 $a1 set
+ i2cread bal nop \ # of columns
+ v0 -8 v0 addi
+ v0 -4 t0 addi
+ t0 0> if nodimm then
+ v0 02 v0 sll
+ v0 h# 0c v0 andi \ acolbits
+ t9 v0 t9 or
+
+ d# 17 $a1 set
+ i2cread bal nop \ blocks/DRAM
+ 4 t0 set
+ v0 t0 = if
+ nop
+ t9 h# 10 t9 ori \ abankbit
+ else
+ nop
+ 2 t0 set
+ v0 t0 <> if nodimm then
+ then
+
+ 5 $a1 set
+ i2cread bal nop \ number of sides
+ 2 t0 set
+ v0 t0 = if
+ nop
+ t9 h# 20 t9 ori \ asides
+ t8 1 t8 sll \ memory size * 2
+ else
+ nop
+ 1 t0 set
+ v0 t0 <> if nodimm then
+ then
+
+ 6 $a1 set
+ i2cread bal nop \ width
+ v0 d# -72 t0 addi
+ t0 0> if nodimm then
+ v0 d# -36 t0 addi
+ t0 0> if
+ nop
+ t9 h# 80 t9 ori \ awidth64
+ then
+
+ $a0 0 <> if nop t9 8 t9 sll then
+ t8 v0 move
+ t9 v1 move
+
+ s6 jr nop
+end-code
+
+label start-memory ( -- v0: RAM size )
+ ra s7 move
+
+ i2creset bal nop
+
+[ifndef] hard-code-memory
+ \ DIMM 0
+ 0 $a0 set
+ size-dimm bal nop
+ v0 s0 move
+ v1 s1 move
+
+ \ DIMM 2
+ 1 $a0 set
+ size-dimm bal nop
+ s0 v0 s0 add \ s0 = size
+ s1 v1 s1 or \ s1 = shape
+[else]
+ h# 200.0000 s0 set
+ h# 4091 s1 set
+[then]
+
+ \ Set various bonito registers
+ bonito-reg-pa t3 set
+ s1 t3 h# 0c sw \ sdcfg
+
+ s0 0 = if
+ nop
+ h# 20.0000 s0 set \ Always assume at least 4MB
+ then
+
+ 0 t1 set \ accumulate pcimembasecfg settings
+
+ \ Set bar0 mask and translation to point to SDRAM
+ $0 s0 t0 subu
+ t0 d# 23 t0 srl
+ t0 h# 1f t0 andi
+ t1 t0 t1 or
+ t1 h# 400 t1 ori \ cached
+
+ \ Set bar1 to minimum size to conserve PCI space
+ -1 t0 set
+ t0 d# 11 t0 srl
+ h# 1.f000 t2 set
+ t0 t2 t0 and
+ t1 t0 t1 or
+ h# 40.0000 t2 set
+ t1 t2 t1 or
+
+ t1 t3 h# 14 sw \ pcimembasecfg
+
+ \ Enable configuration cycles now
+ t3 h# 00 t0 lw
+ h# 20 invert t1 set
+ t0 t1 t0 and
+ t0 t3 h# 00 sw
+
+ \ Return to reset dropin
+ kseg0 t0 set
+ s0 t0 v0 add
+
+ s7 jr
+ nop
+
+end-code
+
+also mips-assembler
+start-memory my-entry put-branch
+previous
+
+end-assembling
+
+writing start.di
+asm-base here over - 0 " start" write-dropin
+ofd @ fclose
Added: cpu/mips/bonito/virtaddr.fth
===================================================================
--- cpu/mips/bonito/virtaddr.fth (rev 0)
+++ cpu/mips/bonito/virtaddr.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,20 @@
+purpose: Virtual addresses for Bonito
+copyright: Copyright 2001 FirmWorks All Rights Reserved
+
+headerless
+
+[ifdef] ram-image
+rom-base kseg0 + value fw-virt-base \ 1 meg of mapping space
+[else]
+0 value fw-virt-base \ Setup later after we know the memory size
+[then]
+h# 10.0000 value fw-virt-size
+
+headers
+
+[ifdef] ram-image
+fw-virt-base fw-virt-size + ' load-base set-config-int-default
+[else]
+kseg0 h# 20.0000 + ' load-base set-config-int-default
+[then]
+0 value load-limit \ Top address of area at load-base (set later)
Added: cpu/mips/boot.fth
===================================================================
--- cpu/mips/boot.fth (rev 0)
+++ cpu/mips/boot.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,183 @@
+\ See license at end of file
+purpose: Low-level startup code for MIPS
+
+\ boot.fth -- Version for running Forth on Q-system
+
+headers
+
+\ Boot code (cold start). The cold start code is executed
+\ when Forth is initially started. Its job is to initialize the Forth
+\ virtual machine registers.
+
+\ r: cause of entry (could = xir-magic)
+\ %i6: base of physical memory (is it phys or virt?)
+\ %i7: size of physical memory
+
+\ MAJC entry assumption: code has been placed where loader wanted it;
+\ Loader passes in physical address of base of ram to use as RAM in r8,
+\ top of RAM in r9
+
+headerless
+defer rom-init-io
+headers \ Debugging is difficult if rom-init-environment is headerless
+defer rom-init-environment
+headerless
+defer rom-cold-hook
+
+: rom-cold (s -- )
+ hex
+ rom-init-io \ Memory allocator and character I/O
+ do-init \ Kernel
+
+ stand-init-debug? case
+ -1 of
+ cr ." Type 'i' to interrupt stand-init sequence" cr
+ d# 500 ms
+ key? if key drop ." Interacting" cr interact then
+ endof
+ 1 of
+ ." Interacting" cr interact
+ endof
+ endcase
+
+ ['] rom-init-environment guarded \ Environmental dependencies
+ ['] rom-cold-hook guarded \ Open Firmware final startup
+
+ title
+ quit
+;
+
+: abs-jal ( adr -- )
+ 2 >> h# 3ff.ffff land h# 0c00.0000 or ,
+;
+
+label rom-cold-code ( a0: fw-RAM-base a1: fw-RAM-size -- )
+
+ \ Find the base address
+[ifndef] rom-based?
+ h# 81f0.0000 $a0 set \ Load address
+ h# 8200.0000 $a1 set \ FW RAMtop
+[then]
+ here 8 + bal
+
+ here origin - 4 + base set \ base = relative address of this instruction
+ ra base base subu \ Base address of Forth kernel
+
+ \ Copy the initial contents of the user area to their final positions
+
+ \ Get the address of the initial contents of the user area
+ base h# -20 t4 addi \ Address of dictionary file header
+ ( base ) t4 d# 1 4* t1 lw \ Size of initial dictionary
+ base t1 t1 addu \ Address of user area image
+
+ user-size t0 set
+ $a1 t0 up subu \ RAM address of user area
+ ( base ) t4 d# 2 4* t2 lw \ Size of user area image
+
+ 'body main-task t3 set \ Allow the exception handler to find the
+ base t3 t3 addu \ user area by storing the address of the
+ up t3 put \ main user area in the "constant" main-task
+
+ \ Copy the initial User Area image to the RAM copy
+ begin
+ t2 -4 t2 addi
+ t1 t2 t3 addu
+ t3 t3 get
+ up t2 t5 addu
+ t3 t5 put
+ t2 0 = until
+ nop
+
+ t4 0 t4 lb \ Get first byte of header
+ h# 10 $at li \ Most significant byte of "branch" instruction
+ t4 $at <> if
+ $0 t4 move \ Delay - set flag to 0 (big-endian)
+ $0 -1 t4 addiu \ Set flag to -1 (little-endian)
+ then
+ t4 'user in-little-endian? sw
+
+ \ The User Area is now initialized
+ $a1 'user memtop sw \ Set memtop
+ up 'user up0 sw \ Set the up0 user variable
+ up rp move \ Set return stack pointer
+ rp 'user rp0 sw \ Set the rp0 user variable
+ rp rs-size negate sp addi \ Set data stack pointer
+ sp 'user sp0 sw \ Set the sp0 user variable
+ sp ps-size negate t3 addi \ Compute limit
+ sp /n sp addi \ Account for the top of stack register
+
+ t3 initial-heap-size negate t3 addi \ Less heap
+ t3 'user limit sw \ Set the limit user variable
+
+[ifdef] global-dictionary
+ 'body dp t5 set
+ base t5 t5 addu
+ t1 t5 put \ Set dp
+[else]
+ t1 'user dp sw \ Set the dp user variable
+[then]
+
+ \ Clear return stack area
+ rp rs-size negate rp addi
+ rs-size t0 set
+ t1 t1 t1 xor
+ begin
+ t0 -4 t0 addi
+ t1 rp put
+ t0 0 = until
+ nop
+ rp rs-size rp addi
+
+ \ Enter Forth
+ np@ origin- np set
+ np base np addu
+
+ 'body rom-cold ip set
+ ip base ip addu
+c;
+
+[ifndef] rom-based?
+: put-jump ( target-adr branch-adr -- )
+ tuck ( 4 - ) - rom-base + h# 20 + 2/ 2/ h# 03ff.ffff and
+ h# 0800.0000 or
+ swap !
+;
+[then]
+
+: install-rom-cold ( -- )
+ " stand-init-io" $find-name is rom-init-io
+ " stand-init" $find-name is rom-init-environment
+ " startup" $find-name is rom-cold-hook
+
+[ifdef] rom-based?
+ rom-cold-code origin- origin !
+[else]
+ rom-cold-code origin put-jump
+[then]
+;
+
+headers
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/broadcom/avx/68kio.fth
===================================================================
--- cpu/mips/broadcom/avx/68kio.fth (rev 0)
+++ cpu/mips/broadcom/avx/68kio.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,12 @@
+purpose: Access to 68K IO space
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+headers
+68k-io-base value io-base
+
+: pc@ ( offset -- n ) io-base + rb@ ;
+: pc! ( n offset -- ) io-base + rb! ;
+: pw@ ( offset -- n ) io-base + rw@ ;
+: pw! ( n offset -- ) io-base + rw! ;
+: pl@ ( offset -- n ) io-base + rl@ ;
+: pl! ( n offset -- ) io-base + rl! ;
Added: cpu/mips/broadcom/avx/bcuart.fth
===================================================================
--- cpu/mips/broadcom/avx/bcuart.fth (rev 0)
+++ cpu/mips/broadcom/avx/bcuart.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,21 @@
+purpose: Diagnostic (before console installation) access to serial port
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+headerless
+
+: uart@ ( reg# -- byte ) uart-base + c@ ; \ Read from a UART register
+: uart! ( byte reg# -- ) uart-base + c! ; \ Write to a UART register
+
+: baud ( baud-rate -- ) drop ;
+
+: inituarts ( -- )
+;
+
+: ukey? ( -- flag ) 3 uart@ 4 and 0<> ; \ Test for rcv character
+: uemit? ( -- flag ) 5 uart@ 1 and 0<> ; \ Test for xmit ready
+: ubreak? ( -- flag ) false ;
+: clear-break ( -- ) ;
+
+: ukey ( -- char ) begin ukey? until 2 uart@ ; \ Receive a character
+: uemit ( char -- ) begin uemit? until 4 uart! ; \ Transmit a character
+headers
Added: cpu/mips/broadcom/avx/boot.fth
===================================================================
--- cpu/mips/broadcom/avx/boot.fth (rev 0)
+++ cpu/mips/broadcom/avx/boot.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,198 @@
+purpose: Low-level startup code for MIPS
+copyright: Copyright 2000-2001, FirmWorks. All Rights Reserved.
+
+\ boot.fth -- Version for running Forth on Q-system
+
+headers
+
+\ Boot code (cold start). The cold start code is executed
+\ when Forth is initially started. Its job is to initialize the Forth
+\ virtual machine registers.
+
+\ r: cause of entry (could = xir-magic)
+\ %i6: base of physical memory (is it phys or virt?)
+\ %i7: size of physical memory
+
+\ MAJC entry assumption: code has been placed where loader wanted it;
+\ Loader passes in physical address of base of ram to use as RAM in r8,
+\ top of RAM in r9
+
+create debug-reset
+fload ${BP}/arch/mips/broadcom/avx/report.fth
+
+headerless
+defer rom-init-io
+headers \ Debugging is difficult if rom-init-environment is headerless
+defer rom-init-environment
+headerless
+defer rom-cold-hook
+
+: rom-cold (s -- )
+begin uart-base h# 3fd + c@ h# 20 and until
+ascii r uart-base h# 3f8 + c!
+ hex
+ rom-init-io \ Memory allocator and character I/O
+begin uart-base h# 3fd + c@ h# 20 and until
+ascii o uart-base h# 3f8 + c!
+ do-init \ Kernel
+begin uart-base h# 3fd + c@ h# 20 and until
+ascii m uart-base h# 3f8 + c!
+[ifdef] notyet
+ stand-init-debug? if
+ cr ." Type 'i' to interrupt stand-init sequence" cr
+ d# 200 ms
+ key? if key drop ." Interacting" cr interact then
+ then
+[then]
+begin uart-base h# 3fd + c@ h# 20 and until
+ascii c uart-base h# 3f8 + c!
+." hello" cr
+ ['] rom-init-environment guarded \ Environmental dependencies
+begin uart-base h# 3fd + c@ h# 20 and until
+ascii d uart-base h# 3f8 + c!
+ ['] rom-cold-hook guarded \ Open Firmware final startup
+
+ title
+ quit
+;
+
+: abs-jal ( adr -- )
+ 2 >> h# 3ff.ffff land h# 0c00.0000 or ,
+;
+
+label rom-cold-code ( a0: fw-RAM-base a1: fw-RAM-size -- )
+
+[ifdef] debug-reset
+carret ?report
+linefeed ?report
+
+$a0 s7 move
+dot
+$a1 $a0 move dot
+s7 $a0 move
+
+ascii C ?report
+[then]
+
+ \ Find the base address
+[ifdef] rom-based?
+ here 8 + bal
+[else]
+ h# 81f0.0000 $a0 set
+ h# 8200.0000 $a1 set
+
+ here origin - 8 + rom-base + abs-jal \ ra = Absolute address of next instruction
+[then]
+ here origin - 4 + base set \ base = relative address of this instruction
+ ra base base subu \ Base address of Forth kernel
+
+ \ Copy the initial contents of the user area to their final positions
+
+ascii O ?report
+ \ Get the address of the initial contents of the user area
+ base h# -20 t4 addi
+ ( base ) t4 d# 1 4* t1 lw \ Size of initial dictionary
+ base t1 t1 addu \ Address of user area image
+
+ user-size t0 set
+ $a1 t0 up subu \ RAM address of user area
+ ( base ) t4 d# 2 4* t2 lw \ Size of user area image
+
+ 'body main-task t3 set \ Allow the exception handler to find the
+ base t3 t3 addu \ user area by storing the address of the
+ up t3 put \ main user area in the "constant" main-task
+
+ \ Copy the initial User Area image to the RAM copy
+ begin
+ t2 -4 t2 addi
+ t1 t2 t3 addu
+ t3 t3 get
+ up t2 t4 addu
+ t3 t4 put
+ t2 0 = until
+ nop
+
+ascii L ?report
+[ifdef] debug-reset
+up 0 $a0 lw dot
+up 4 $a0 lw dot
+[then]
+
+ \ The User Area is now initialized
+ $a1 'user memtop sw \ Set memtop
+ up 'user up0 sw \ Set the up0 user variable
+ up rp move \ Set return stack pointer
+ rp 'user rp0 sw \ Set the rp0 user variable
+ rp rs-size negate sp addi \ Set data stack pointer
+ sp 'user sp0 sw \ Set the sp0 user variable
+ sp ps-size negate t3 addi \ Compute limit
+ sp /n sp addi \ Account for the top of stack register
+
+ t3 initial-heap-size negate t3 addi \ Less heap
+ t3 'user limit sw \ Set the limit user variable
+ t1 'user dp sw \ Set the dp user variable
+
+ \ Clear return stack area
+ rp rs-size negate rp addi
+ rs-size t0 set
+ t1 t1 t1 xor
+ begin
+ t0 -4 t0 addi
+ t1 rp put
+ t0 0 = until
+ nop
+ rp rs-size rp addi
+
+ascii D ?report
+ \ Enter Forth
+ np@ origin- np set
+ np base np addu
+
+ 'body rom-cold ip set
+ ip base ip addu
+
+[ifdef] debug-reset
+carret ?report
+linefeed ?report
+np $a0 move dot
+base $a0 move dot
+up $a0 move dot
+tos $a0 move dot
+ip $a0 move dot
+rp $a0 move dot
+sp $a0 move dot
+carret ?report
+linefeed ?report
+np 0 $a0 lw dot
+np 4 $a0 lw dot
+np 8 $a0 lw dot
+np h# c $a0 lw dot
+np h# 10 $a0 lw dot
+np h# 14 $a0 lw dot
+carret ?report
+linefeed ?report
+ip 0 $a0 lw dot
+[then]
+
+c;
+
+: put-jump ( target-adr branch-adr -- )
+ tuck ( 4 - ) - rom-base + ( h# 20 + ) 2/ 2/ h# 03ff.ffff and
+ h# 0800.0000 +
+ swap !
+;
+
+: install-rom-cold ( -- )
+ " stand-init-io" $find-name is rom-init-io
+ " stand-init" $find-name is rom-init-environment
+ " startup" $find-name is rom-cold-hook
+
+[ifdef] rom-based?
+ rom-cold-code origin- origin !
+[else]
+ rom-cold-code origin put-jump
+[then]
+;
+
+headers
+
Added: cpu/mips/broadcom/avx/broadcom.fth
===================================================================
--- cpu/mips/broadcom/avx/broadcom.fth (rev 0)
+++ cpu/mips/broadcom/avx/broadcom.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,12 @@
+purpose: Access to Broadcom spaces
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+hex
+headers
+
+: bcl@ ( idx -- val ) bc-reg-base + l@ ;
+: bcl! ( val idx -- ) bc-reg-base + l! ;
+
+: bc-cfg@ ( idx -- value ) pci-reg-base + l@ ;
+: bc-cfg! ( value idx -- ) pci-reg-base + l! ;
+
Added: cpu/mips/broadcom/avx/devalias.fth
===================================================================
--- cpu/mips/broadcom/avx/devalias.fth (rev 0)
+++ cpu/mips/broadcom/avx/devalias.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,4 @@
+devalias com1 /serial@bc002000
+devalias com2 /serial@bc002800
+devalias net /ethernet
+
Added: cpu/mips/broadcom/avx/devices.fth
===================================================================
--- cpu/mips/broadcom/avx/devices.fth (rev 0)
+++ cpu/mips/broadcom/avx/devices.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,53 @@
+purpose: Load device drivers for AVX settop box
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+hex
+
+create use-flash-nvram
+
+fload ${BP}/cpu/mips/broadcom/avx/pcicfg.fth
+
+0 0 " " " /" begin-package
+ fload ${BP}/cpu/mips/broadcom/avx/mappci.fth \ Map PCI to root
+ fload ${BP}/dev/pcibus.fth \ Generic PCI bus package
+ fload ${BP}/cpu/mips/broadcom/avx/pcinode.fth \ System-specific words for PCI
+end-package
+stand-init: PCI host bridge
+ " /pci" " init" execute-device-method drop
+;
+
+fload ${BP}/dev/pciprobe.fth \ Generic PCI probing
+
+fload ${BP}/dev/isa/irq.fth
+
+0 0 uart-pa kseg1 + <# u#s u#> " /" begin-package
+ 4 encode-int " interrupts" property
+ fload ${BP}/dev/16550pkg/ns16550p.fth
+ d# 14318000 encode-int " clock-frequency" property
+ fload ${BP}/dev/16550pkg/isa-int.fth
+end-package
+: com1 ( -- adr len ) " com1" ; ' com1 to fallback-device
+: use-com1 ( -- )
+ " com1" " input-device" $setenv
+ " com1" " output-device" $setenv
+;
+
+0 0 uart2-base <# u#s u#> " /" begin-package
+ 4 encode-int " interrupts" property
+ fload ${BP}/dev/16550pkg/ns16550p.fth
+ d# 14318000 encode-int " clock-frequency" property
+ fload ${BP}/dev/16550pkg/isa-int.fth
+end-package
+: com2 ( -- adr len ) " com2" ;
+
+support-package: 16550
+fload ${BP}/dev/16550pkg/16550.fth \ Serial port support package
+end-support-package
+
+fload ${BP}/dev/flashpkg.fth
+fload ${BP}/dev/am29lv008b.fth \ Low-level FLASH programming driver
+fload ${BP}/cpu/mips/broadcom/loadvpd.fth \ VPD manager
+fload ${BP}/cpu/mips/broadcom/avx/flash.fth \ Platform-specific FLASH interface
+
+: ll ( idx -- ) dup f and 0= if cr u. ." " else drop then ;
+: dump-pci ( cfg-adr len -- ) bounds do i ll i config-l@ 8 u.r space 4 +loop ;
Added: cpu/mips/broadcom/avx/excption.fth
===================================================================
--- cpu/mips/broadcom/avx/excption.fth (rev 0)
+++ cpu/mips/broadcom/avx/excption.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,83 @@
+purpose: Exception handlers
+copyright: Copyright 2001 FirmWorks All Rights Reserved
+
+headers
+hex
+
+defer exception-hook ' noop to exception-hook
+
+: .dis1 ( addr -- ) [ also disassembler ] pc l! [ previous ] dis1 ;
+
+: .epc ( -- )
+ epc@
+ cause@ h# 8000.0000 and if la1+ then
+ .dis1
+;
+
+: .badvaddr ( -- )
+ ." Bad virtual address = " badvaddr@ u. cr reset-all
+;
+
+: (exception-handler) ( exception# -- )
+ base @ >r hex
+ exception-hook
+ dup (.exception)
+ .epc
+ case
+ 4 of .badvaddr endof
+ 5 of .badvaddr endof
+ endcase
+ r> base !
+;
+' (exception-handler) to dispatch-exceptions
+
+: ?report ( char -- )
+ " uart-base d# 16 >> t0 lui" evaluate
+ " begin t0 h# 3fd t1 lbu t1 h# 20 t1 andi t1 0 <> until nop" evaluate
+ ( char ) " t1 set t1 t0 h# 3f8 sb " evaluate
+;
+
+label (tlb-handler)
+ carret ?report linefeed ?report
+ ascii T ?report ascii L ?report ascii B ?report bl ?report
+ ascii R ?report ascii e ?report ascii f ?report ascii i ?report
+ ascii l ?report ascii l ?report bl ?report
+ ascii E ?report ascii x ?report ascii c ?report ascii e ?report
+ ascii p ?report ascii t ?report ascii i ?report ascii o ?report
+ ascii n ?report
+ carret ?report linefeed ?report
+ begin again
+ nop
+end-code
+' (tlb-handler) to tlb-handler
+
+label (xtlb-handler)
+ carret ?report linefeed ?report
+ ascii X ?report ascii T ?report ascii L ?report ascii B ?report bl ?report
+ ascii R ?report ascii e ?report ascii f ?report ascii i ?report
+ ascii l ?report ascii l ?report bl ?report
+ ascii E ?report ascii x ?report ascii c ?report ascii e ?report
+ ascii p ?report ascii t ?report ascii i ?report ascii o ?report
+ ascii n ?report
+ carret ?report linefeed ?report
+ begin again
+ nop
+end-code
+' (xtlb-handler) to xtlb-handler
+
+label (cache-handler)
+ carret ?report linefeed ?report
+ ascii C ?report ascii a ?report ascii c ?report ascii h ?report
+ ascii e ?report bl ?report
+ ascii E ?report ascii r ?report ascii r ?report ascii o ?report
+ ascii r ?report bl ?report
+ ascii E ?report ascii x ?report ascii c ?report ascii e ?report
+ ascii p ?report ascii t ?report ascii i ?report ascii o ?report
+ ascii n ?report
+ carret ?report linefeed ?report
+ begin again
+ nop
+end-code
+' (cache-handler) to cache-handler
+
+headers
Added: cpu/mips/broadcom/avx/flash.fth
===================================================================
--- cpu/mips/broadcom/avx/flash.fth (rev 0)
+++ cpu/mips/broadcom/avx/flash.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,277 @@
+purpose: Setup for Flash ROM access
+copyright: Copyright 1995-2001 Firmworks. All Rights Reserved.
+
+h# 10.0000 to /flash
+
+\ Flash usage:
+\ bfc0.0000-bfc5.ffff backup ofw (hardware protected)
+\ bfc7.0000-bfc7.ffff fixed VPD (hardware protected)
+\ bfc8.0000-bfcd.ffff new ofw
+\ bfcf.0000-bfcf.ffff variable VPD
+\ bfce.0000-bfce.ffff temp nvram (hardware protected eventually)
+
+h# 0.0000 constant ofw-b-offset
+h# 8.0000 constant ofw-offset
+h# 7.0000 constant vpd-f-offset
+h# f.0000 constant vpd-v-offset
+
+/rom constant /ofw
+[ifdef] use-flash-nvram
+h# 1.0000 constant /nvram
+h# e.0000 constant nvram-offset
+/nvram to config-size
+[then]
+h# 1.0000 constant /vpd
+/vpd to vpd-size
+
+0 value flashbase
+0 value fixed-vpd-node
+0 value var-vpd-node
+
+headerless
+: (fctl!) ( n a -- ) flashbase + rb! ; ' (fctl!) to fctl!
+: (fdata!) ( n a -- ) flashbase + rb! ; ' (fdata!) to fdata!
+: (fc@) ( a -- n ) flashbase + rb@ ; ' (fc@) to fc@
+
+headers
+: open-flash ( -- )
+ rom-pa /flash root-map-in to flashbase
+;
+: close-flash ( -- )
+ flashbase /flash root-map-out 0 to flashbase
+;
+' open-flash to enable-flash-writes
+
+\ flash update words
+0 value flash-offset
+0 value /max-image
+: ?partial-programmable ( len -- len )
+ dup /max-image > if
+ collect(
+ ." Image is too big." cr
+ )collect alert
+ abort
+ then
+ flash-offset over ['] ?partial-protected catch throw
+;
+: partial-erase-flash ( len -- len ) flash-offset over partial-erase ;
+: partial-program-flash ( adr len -- ) flash-offset swap write-bytes ;
+: partial-verify-flash ( adr offset len -- ) nip flash-offset swap verify-bytes ;
+
+' ?partial-programmable to ?programmable
+' partial-erase-flash to erase-flash
+' partial-program-flash to program-flash
+' partial-verify-flash to verify-flash
+
+\ OFW update words
+: use-ofw ( -- ) \ Update primary OFW
+ ofw-offset to flash-offset
+ /ofw to /max-image
+;
+
+: use-backup-ofw ( -- ) \ Update backup OFW, R/O on AVX product
+ ofw-b-offset to flash-offset
+ /ofw to /max-image
+;
+
+\ VPD update words
+: use-var-vpd ( -- ) \ Update variable VPD
+ vpd-v-offset to flash-offset
+ /vpd to /max-image
+;
+
+: use-fixed-vpd ( -- ) \ Update fixed VPD, R/O on AVX product
+ vpd-f-offset to flash-offset
+ /vpd to /max-image
+;
+
+[ifdef] use-flash-nvram
+: use-nvram ( -- ) \ Update backup flash-based nvram
+ nvram-offset to flash-offset
+ /nvram to /max-image
+;
+[then]
+
+0 0 rom-pa <# u#s u#> " /" begin-package
+ " flash" device-name
+ /flash value /device
+ my-address my-space /device reg
+ 1 " #address-cells" integer-property
+
+ : decode-unit ( adr len -- phys ) push-hex $number if 0 then pop-base ;
+ : encode-unit ( phys -- adr len ) push-hex (u.) pop-base ;
+
+ : map-in ( offset size -- virt )
+ >r >r my-address my-space r> + r> " map-in" $call-parent
+ ;
+ : map-out ( virt size -- ) " map-out" $call-parent ;
+ : open ( -- flag ) true ;
+ : close ( -- ) ;
+
+new-device
+ 0 0 vpd-f-offset <# u#s u#> set-args
+ " vpd-fixed" device-name
+ my-address my-space /vpd reg
+ /vpd value /device
+ fload ${BP}/cpu/mips/broadcom/avx/vpdflash.fth
+
+ : write ( adr len -- )
+ use-fixed-vpd clip-size (flash)
+ ;
+finish-device
+
+new-device
+ 0 0 vpd-v-offset <# u#s u#> set-args
+ " vpd-var" device-name
+ my-address my-space /vpd reg
+ /vpd value /device
+ fload ${BP}/cpu/mips/broadcom/avx/vpdflash.fth
+
+ : write ( adr len -- )
+ use-var-vpd clip-size (flash)
+ ;
+finish-device
+
+[ifdef] use-flash-nvram
+new-device
+ 0 0 nvram-offset <# u#s u#> set-args
+ " flash-nvram" device-name
+ /nvram value /device
+ my-address my-space /nvram reg
+ fload ${BP}/cpu/mips/broadcom/avx/vpdflash.fth
+
+ 0 value nvram-buf
+ : write ( adr len -- len )
+ use-nvram
+ clip-size ( len' adr len' )
+ seek-ptr >r ( len adr len ) ( R: offset )
+ /device alloc-mem >r ( len adr len ) ( R: offset buf )
+ 0 0 seek drop ( len adr len ) ( R: offset buf )
+ r@ /device read drop ( len adr len ) ( R: offset buf )
+ r@ -rot r> r> + swap move ( len buf )
+ dup /device (flash) ( len buf )
+ /device free-mem ( len )
+ ;
+finish-device
+[then]
+
+new-device
+ 0 0 ofw-b-offset <# u#s u#> set-args
+ " ofw" device-name
+ /rom value /device
+ my-address my-space /device reg
+ 1 " #address-cells" integer-property
+
+ : decode-unit ( adr len -- phys ) push-hex $number if 0 then pop-base ;
+ : encode-unit ( phys -- adr len ) push-hex (u.) pop-base ;
+
+ : map-in ( offset size -- virt )
+ >r >r my-address my-space r> + r> " map-in" $call-parent
+ ;
+ : map-out ( virt size -- ) " map-out" $call-parent ;
+ : open ( -- flag ) true ;
+ : close ( -- ) ;
+
+ new-device
+ 0 0 /resetjmp <# u#s u#> set-args
+ " dropins" device-name
+ /rom /resetjmp - value /device
+ my-address my-space /device reg
+ fload ${BP}/dev/flashpkg.fth
+ finish-device
+
+finish-device
+
+new-device
+ 0 0 ofw-offset <# u#s u#> set-args
+ " ofw" device-name
+ /rom value /device
+ my-address my-space /device reg
+ 1 " #address-cells" integer-property
+
+ : decode-unit ( adr len -- phys ) push-hex $number if 0 then pop-base ;
+ : encode-unit ( phys -- adr len ) push-hex (u.) pop-base ;
+
+ : map-in ( offset size -- virt )
+ >r >r my-address my-space r> + r> " map-in" $call-parent
+ ;
+ : map-out ( virt size -- ) " map-out" $call-parent ;
+ : open ( -- flag ) true ;
+ : close ( -- ) ;
+
+ new-device
+ 0 0 /resetjmp <# u#s u#> set-args
+ " dropins" device-name
+ /rom /resetjmp - value /device
+ my-address my-space /device reg
+ fload ${BP}/dev/flashpkg.fth
+ finish-device
+
+finish-device
+
+end-package
+
+0 value ofw-b-node ' ofw-b-node " ofw-backup" chosen-value
+0 value ofw-a-node ' ofw-a-node " ofw-active" chosen-value
+0 value fixed-vpd-node ' fixed-vpd-node " vpd-fixed" chosen-value
+0 value var-vpd-node ' var-vpd-node " vpd-var" chosen-value
+
+stand-init: rom chosen
+ ofw-b-offset <# u#s " /ofw@" hold$ u#> open-dev to ofw-b-node
+ push-hex
+ " rom" myrombase rom-pa - <# " /dropins" hold$ u#s " /ofw@" hold$ u#> $devalias
+ pop-base
+ myrombase rom-pa = if
+ ofw-b-node
+ else
+ ofw-offset <# u#s " /ofw@" hold$ u#> open-dev
+ then
+ to ofw-a-node
+;
+
+[ifdef] use-flash-nvram
+stand-init: NVRAM
+ flash-type 1 = swap h# 37 = and if
+ ." NVRAM in flash" cr
+ " /flash-nvram" open-dev to nvram-node
+ nvram-node 0= if
+ ." The flash-based NVRAM is not working." cr
+ then
+ ['] init-config-vars catch drop
+ else
+ 0 to config-size
+ ." No NVRAM" cr
+ then
+;
+[then]
+
+stand-init: VPDs
+ flash-type 1 = swap h# 37 = and if
+ ." VPDs in flash" cr
+ " /vpd-var" open-dev dup to var-vpd-node to vpd-node
+ vpd-node 0= if
+ ." The variable VPD is not working." cr
+ then
+ ['] init-vpd-buffer catch drop
+ " /vpd-fixed" open-dev dup to fixed-vpd-node to vpd-node
+ vpd-node 0= if
+ ." The fixed VPD is not working." cr
+ then
+ ['] init-vpd-buffer catch drop
+ else
+ 0 to vpd-size
+ ." No VPDs" cr
+ then
+;
+
+\ Words to toggle the view between the two VPDs.
+: select-fixed-vpd ( -- )
+ fixed-vpd-node to vpd-node
+ init-vpd-buffer
+;
+
+: select-var-vpd ( -- )
+ var-vpd-node to vpd-node
+ init-vpd-buffer
+;
+
Added: cpu/mips/broadcom/avx/fw.bth
===================================================================
--- cpu/mips/broadcom/avx/fw.bth (rev 0)
+++ cpu/mips/broadcom/avx/fw.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,278 @@
+purpose: Load file for AVX settop box
+copyright: Copyright 2000-2001 FirmWorks All Rights Reserved
+
+dictionary: ${BP}/cpu/mips/build/basefw.dic
+command: &mipsfth &dictionary &this
+build-now
+
+create rom-based?
+\ create ram-image
+
+\ ' $report-name is include-hook
+true to stand-init-debug?
+
+" dhcp" ' ip-address set-config-string-default
+false ' auto-boot? set-config-int-default
+true ' fcode-debug? set-config-int-default
+" com1" ' output-device set-config-string-default
+" com1" ' input-device set-config-string-default
+
+fload ${BP}/cpu/mips/ksegaddr.fth
+fload ${BP}/cpu/mips/broadcom/avx/physaddr.fth
+fload ${BP}/cpu/mips/broadcom/avx/virtaddr.fth
+
+h# 1.0000 constant initial-heap-size
+0 value myrombase
+fload ${BP}/cpu/mips/boot.fth \ Low-level startup code
+\ fload ${BP}/cpu/mips/broadcom/avx/boot.fth \ Testing only
+
+: rl@ l@ ; : rl! l! ;
+: rw@ w@ ; : rw! w! ;
+: rb@ c@ ; : rb! c! ;
+
+fload ${BP}/cpu/mips/broadcom/avx/68kio.fth \ 68K I/O space access
+fload ${BP}/cpu/mips/broadcom/avx/broadcom.fth \ Broadcom space access
+
+[ifdef] for-bcm93730
+fload ${BP}/cpu/mips/broadcom/avx/bcuart.fth \ BCM97370 uart
+[else]
+fload ${BP}/arch/prep/diaguart.fth \ Diagnostic driver for serial port
+d# 14318000 to uart-clock-frequency
+h# 2000 is uart-base
+[then]
+
+fload ${BP}/os/stand/sysuart.fth \ Plug UART routines into key and emit
+\ ' ukey is diag-key \ Feed UART input to "dl"
+
+h# 1000 to pagesize
+d# 12 to pageshift
+
+defer pcicache-inv ' 2drop to pcicache-inv
+defer pcicache-wbinv ' 2drop to pcicache-wbinv
+
+fload ${BP}/cpu/mips/cache.fth \ Cache synchronization/flushing
+fload ${BP}/cpu/mips/broadcom/avx/rootnode.fth \ Root node mapping
+dev /
+ " AVX" model
+ " AVX" encode-string " architecture" property
+ d# 27,000,000 " clock-frequency" integer-property
+device-end
+d# 81,000,000 to cpu-clock-speed \ CPU clock in Hz
+
+: (cpu-arch ( -- adr len )
+ " architecture" ['] root-node get-package-property drop
+ get-encoded-string
+;
+' (cpu-arch to cpu-arch
+
+[ifdef] notyet
+0 config-int next-xid
+stand-init: Next xid
+ next-xid h# 10.0000 + dup to next-xid to rpc-xid
+;
+[then]
+
+\ Memory management services
+[ifdef] virtual-mode
+fload ${BP}/ofw/core/clntmem1.fth \ client services for memory
+[else]
+fload ${BP}/ofw/core/clntphy1.fth \ client services for memory
+[then]
+fload ${BP}/ofw/core/memlist.fth \ Resource list common routines
+fload ${BP}/ofw/core/showlist.fth \ Linked list display tool
+fload ${BP}/ofw/core/allocph1.fth \ S Physical memory allocator
+fload ${BP}/ofw/core/availpm.fth \ Available memory list
+fload ${BP}/ofw/core/allocmor.fth \ S Allow alloc-mem to use more memory
+
+: (initial-heap) ( -- adr len ) sp0 @ ps-size - limit tuck - ;
+['] (initial-heap) to initial-heap
+
+\ fload ${BP}/fm/lib/dumballo.fth \ Rudimentary memory allocator
+
+variable bank-mask
+1 bank-mask !
+fload ${BP}/cpu/mips/probemem.fth \ Memory probing
+stand-init: Probing memory
+ " probe" memory-node @ $call-method
+;
+
+\ Load file format handlers
+
+: call32 ; defer .subname
+fload ${BP}/ofw/core/allocsym.fth \ Allocate memory for symbol table
+fload ${BP}/ofw/core/symcif.fth
+fload ${BP}/ofw/core/symdebug.fth
+: release-load-area ( boundary-adr -- ) drop ;
+fload ${BP}/ofw/elf/elf.fth
+fload ${BP}/ofw/elf/elfdebug.fth
+' 2drop is elf-map-in
+
+\ File system
+fload ${BP}/cpu/mips/zipcrc.fth \ Assembly portion of CRC calculation
+fload ${BP}/forth/lib/crc32.fth \ High-level portion of CRC calculation
+
+fload ${BP}/ofw/fs/fatfs/fdisk2.fth \ Partition map administration
+
+[ifdef] resident-packages
+support-package: fat-file-system
+ fload ${BP}/ofw/fs/fatfs/loadpkg.fth \ FAT file system reader
+end-support-package
+
+support-package: iso9660-file-system
+ fload ${BP}/ofw/fs/cdfs/loadpkg.fth \ ISO 9660 CD-ROM file system reader
+end-support-package
+
+support-package: disk-label
+ fload ${BP}/ofw/disklabl/loadpkg.fth \ Disk label package
+end-support-package
+
+[ifdef] use-ufs
+support-package: ufs-file-system
+ fload ${BP}/ofw/fs/ufs/ufs.fth \ Unix file system
+end-support-package
+[then]
+
+support-package: ext2-file-system
+ fload ${BP}/ofw/fs/ext2fs/ext2fs.fth \ Linux file system
+end-support-package
+
+support-package: dropin-file-system
+ fload ${BP}/ofw/fs/dropinfs.fth \ Dropin file system
+end-support-package
+
+support-package: nfs
+ fload ${BP}/ofw/fs/nfs/loadpkg.fth
+end-support-package
+[then]
+
+\ Device Tree
+fload ${BP}/cpu/mips/broadcom/avx/devices.fth
+fload ${BP}/cpu/mips/broadcom/avx/devalias.fth
+
+: stand-init-io ( -- )
+[ifdef] stand-init-io
+ stand-init-io
+[then]
+\ install-dumb-alloc
+ install-uart-io
+;
+
+fload ${BP}/cpu/mips/broadcom/avx/excption.fth
+fload ${BP}/cpu/mips/broadcom/avx/intr.fth
+
+[ifdef] notyet
+warning @ warning off
+: init
+\ initial-heap add-memory
+ init
+
+ standalone? if
+ stand-init-debug? if
+ cr ." Type 'i' to interrupt stand-init sequence" cr
+ d# 500 ms
+ key? if
+ key drop ." Interacting" cr
+ hex interact
+ then
+ then
+ then
+;
+warning !
+[then]
+
+fload ${BP}/cpu/mips/broadcom/avx/vpd.fth
+
+: (.firmware) ( -- )
+ ." Open Firmware " .built cr
+ ." Copyright 2001 FirmWorks All Rights Reserved" cr
+;
+' (.firmware) to .firmware
+
+headerless
+6 buffer: 'system-mac-address
+headers
+: get-mac-address ( -- )
+ (get-vpd-mac#) 0= if
+ 6 0 do 'system-mac-address i + c! loop
+ else
+ rom-pa h# 56 + 'system-mac-address 6 move
+ 'system-mac-address @ h# ffff.ffff = if
+ 'system-mac-address 0 over c! 1+ 6 over c! 1+ 7f over c!
+ 1+ 0 over c! 1+ 0 over c! 1+ 0 swap c!
+ then
+ then
+;
+headerless
+: (system-mac-address) ( -- addr len ) 'system-mac-address 6 ;
+' (system-mac-address) is system-mac-address
+headers
+
+: .mac-address ( -- )
+ mac-address 0 do
+ dup i + c@ (.2) type
+ i 5 <> if ascii : emit then
+ loop drop
+;
+
+: probe-all ( -- )
+ " probe-" do-drop-in
+ probe-pci
+ get-mac-address
+ set-system-id
+ " probe+" do-drop-in
+;
+
+: copy-reboot-info ( -- ) ;
+defer user-interface ' quit to user-interface
+
+kseg0 to vector-base
+fload ${BP}/ofw/core/startup.fth
+: avx-banner-basics
+ cr
+ ?spaces " AVX Media Center" type cr
+ ?spaces cpu-model type ." , " (.vpd-serial$) ." , "
+ .mac-address ." , " .memory cr ?spaces
+ .firmware
+;
+' avx-banner-basics to banner-basics
+
+: bye ( -- )
+ h# 10 bcl@ h# ffff.fffb and h# 10 bcl!
+ 4 h# 10 bcl! \ cold reset
+ begin again
+;
+' bye to reset-all
+
+defer linux-argc
+: ((linux-argc) ( adr len -- argc )
+ 0 >r begin
+ bl left-parse-string nip 0<> while
+ r> 1+ >r
+ repeat 2drop
+ r>
+;
+: (linux-argc) ( adr len -- argc ) 2drop 2 ;
+' (linux-argc) to linux-argc
+
+defer linux-argv
+: (linux-argv) ( adr len -- 'argv )
+ 3 /n * over + dup alloc-mem dup >r
+ swap erase
+ r@ 3 na+ r@ na1+ !
+ tuck $cstr swap 1+ r@ 3 na+ swap cmove
+ r>
+;
+' (linux-argv) to linux-argv
+
+: linux-setup ( -- )
+ disable-interrupts
+ kseg0 0 sync-cache
+ boot-file linux-argc to $a0
+ boot-file linux-argv to $a1
+ 0 to $a2
+;
+' linux-setup to go-hook
+
+install-rom-cold
+
+.( --- Saving fw.img ...) "" fw.img save-forth cr
Added: cpu/mips/broadcom/avx/initbc.fth
===================================================================
--- cpu/mips/broadcom/avx/initbc.fth (rev 0)
+++ cpu/mips/broadcom/avx/initbc.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,139 @@
+purpose: Initialize Broadcom BCM7030RKPB1 for startup
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+transient
+: bcl! ( data idx -- )
+ bc-reg-base + " t0 set" evaluate
+ " t1 set" evaluate
+ " t1 t0 0 sw" evaluate
+;
+: bc-cfg! ( data idx -- )
+ pci-reg-base + " t0 set" evaluate
+ " t1 set" evaluate
+ " t1 t0 0 sw" evaluate
+;
+: pci-cfg! ( data adr -- )
+ pci-cf8 " t0 set" evaluate
+ ( adr ) h# 8000.0000 or " t1 set t1 t0 0 sw" evaluate
+ pci-cfc " t0 set" evaluate
+ ( data ) " t1 set t1 t0 0 sw" evaluate
+;
+: pci-cfg@ ( adr -- t1: data )
+ pci-cf8 " t0 set" evaluate
+ ( adr ) h# 8000.0000 or " t1 set t1 t0 0 sw" evaluate
+ pci-cfc " t0 set" evaluate
+ " t0 0 t1 lw" evaluate
+;
+: delay-ms ( ms -- )
+ d# 100.0000 * d# 830 + d# 1660 / " t0 set" evaluate
+ " begin t0 0 = until t0 -1 t0 addi" evaluate
+;
+
+resident
+
+label init-broadcom ( -- ) \ Destroys: t0 and t1
+ pci-reg-base t0 set \ Enable Broadcom PCI memory and I/O
+ t0 0 t1 lw
+ t0 4 t1 lw
+ t1 7 t1 ori
+ t1 t0 4 sw
+
+[ifdef] for-bcm93730
+ h# f800.e000 h# 200 bcl! \ ROM address range
+ h# c000.8000 h# 204 bcl! \ Flash address range
+ h# 0400.0000 h# 208 bcl! \ HPNA address range
+ h# 0800.0400 h# 20c bcl! \ VOIP address range
+ h# 0c00.0800 h# 210 bcl! \ 1394 address range
+ h# 1000.0c00 h# 214 bcl! \ POD address range
+ h# 1560.1163 h# 230 bcl! \ 68K bus I/O termination
+
+ \ Setup Broadcom PCI host bridge
+ pci-reg-base t0 set \ Enable Broadcom PCI memory and I/O
+ t0 0 t1 lw
+ t0 4 t1 lw
+ t1 7 t1 ori
+ t1 t0 4 sw
+ h# 1400.0000 h# 58 bc-cfg! \ Setup PCI MEM window BARs. Use only win 0 now.
+ h# 1400.0000 h# 5c bc-cfg!
+ h# 1400.0000 h# 60 bc-cfg!
+ h# 1400.0000 h# 64 bc-cfg!
+ h# 1300.0000 h# 68 bc-cfg! \ Setup PCI IO window BAR. Use only win 0 now.
+ h# 0000.0000 h# 10 bc-cfg! \ Setup PCI SDRAM win 0.
+ h# 0000.0006 h# 50 bc-cfg! \ Setup SDRAM win0 size to 64MB
+ h# 0000.0000 h# 74 bc-cfg! \ Setup SDRAM endianness
+ h# bfa0.0000 t0 set
+ $0 t0 0 sb
+
+ \ Setup BCM93730 PCI devices
+ 0 pci-cfg@
+ h# 1501.0000 h# 10 pci-cfg! \ BCM4413
+ h# 0000.0006 h# 04 pci-cfg!
+
+ h# 1501.1000 h# 110 pci-cfg! \ BCM4423 CODEC
+ h# 0000.0006 h# 104 pci-cfg!
+
+ h# 1501.2000 h# 210 pci-cfg! \ BCM4413 ENET
+ h# 0000.0006 h# 204 pci-cfg!
+
+ h# 1500.0000 h# 810 pci-cfg! \ BCM3250
+ h# 1400.0000 h# 814 pci-cfg!
+ h# 0000.0002 h# 804 pci-cfg!
+
+ \ Setup BCM3250
+ h# b500.0000 t0 set
+ h# f8 t1 set t1 t0 h# c6 sb
+ h# 05 t1 set t1 t0 h# ce sb
+ t0 h# 43 t1 lbu t1 h# 1f t1 ori t1 t0 h# 43 sb
+ t0 h# f7 t1 lbu t1 h# 9f t1 ori t1 t0 h# f7 sb
+ $0 t0 h# 50 sh
+
+ h# 27 t1 set t1 t0 h# 791 sb \ LED
+ h# 10 t1 set t1 t0 h# 790 sb
+ h# 01 t1 set t1 t0 h# 797 sb
+ h# 04 t1 set t1 t0 h# 796 sb
+ h# 20 t1 set t1 t0 h# 799 sb
+ h# b0 t1 set t1 t0 h# 794 sb \ 3730
+ h# f8 t1 set t1 t0 h# 795 sb
+ h# b0 t1 set t1 t0 h# 79a sb
+ h# c0 t1 set t1 t0 h# 79b sb
+ $0 t0 h# 798 sb
+ $0 t0 h# 79e sb
+
+ h# 17 t1 set t1 t0 h# 7b0 sb \ UART
+ h# 00 t1 set t1 t0 h# 7b7 sb
+ h# af t1 set t1 t0 h# 7b6 sb
+ h# 17 t1 set t1 t0 h# 7c0 sb \ UART
+ h# 00 t1 set t1 t0 h# 7c7 sb
+ h# af t1 set t1 t0 h# 7c6 sb
+
+ 1 delay-ms
+ d# 12 t0 mfc0 nop nop
+ h# 3400.0000 t1 set
+ t0 t1 t0 or
+ d# 12 t0 mtc0
+ 1 delay-ms
+ h# bfa0.0000 t0 set
+ 1 t1 set t1 t0 0 sb
+ 1 delay-ms
+ h# bfa0.0000 t0 set
+ 2 t1 set t1 t0 0 sb
+ 1 delay-ms
+ h# bfa0.0000 t0 set
+ 4 t1 set t1 t0 0 sb
+ 1 delay-ms
+
+ h# b500.0000 t0 set
+ h# 89 t1 set t1 t0 h# 794 sb \ HELP
+ h# 86 t1 set t1 t0 h# 795 sb
+ h# c7 t1 set t1 t0 h# 79a sb
+ h# 8c t1 set t1 t0 h# 79b sb
+[else]
+ h# f800.e000 h# 200 bcl! \ ROM address range
+ h# 0007.0004 h# 204 bcl! \ ATMEL uP address range
+ h# 000b.0008 h# 208 bcl! \ COM ports address range
+ h# 000c.000c h# 20c bcl! \ LED address range
+ h# 2aa3.3333 h# 230 bcl! \ 68K bus I/O termination
+[then]
+ ra jr nop
+end-code
+
Added: cpu/mips/broadcom/avx/initcom1.fth
===================================================================
--- cpu/mips/broadcom/avx/initcom1.fth (rev 0)
+++ cpu/mips/broadcom/avx/initcom1.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,24 @@
+purpose: Initialize COM1 for startup messages
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+transient
+: isa-c! ( data isa-adr -- ) \ t0: uart-base
+ swap " t1 set" evaluate
+ " t1 t0 rot sb" evaluate
+;
+resident
+
+\ Initialize the 16552 COM1 serial port with 14.318MHz clock
+label init-com1 ( -- ) \ Destroys t0 and t1
+
+[ifndef] for-bcm93730
+ uart-base t0 set
+ h# 3 h# 3fc isa-c! \ RTS and DTR on
+ h# 80 h# 3fb isa-c! \ Enable divisor latch
+ h# 5d h# 3f8 isa-c! \ Baud rate divisor low - 9600 baud
+ h# 0 h# 3f9 isa-c! \ Baud rate divisor high - 9600 baud
+ h# 3 h# 3fb isa-c! \ 8 bits, no parity
+[then]
+
+ ra jr nop
+end-code
Added: cpu/mips/broadcom/avx/intr.fth
===================================================================
--- cpu/mips/broadcom/avx/intr.fth (rev 0)
+++ cpu/mips/broadcom/avx/intr.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,19 @@
+purpose: Interrupt handlers
+copyright: Copyright 2001 FirmWorks All Rights Reserved
+
+headers
+hex
+
+: .intr-sw ( intr# -- ) ." Software Interrupt " u. cr ;
+: (intr-sw0) ( -- ) 0 .intr-sw ; ' (intr-sw0) to intr-sw0
+: (intr-sw1) ( -- ) 1 .intr-sw ; ' (intr-sw1) to intr-sw1
+
+: .intr-hw ( intr# -- ) ." Hardware Interrupt " u. cr ;
+' dispatch-interrupt to intr-hw0
+' dispatch-interrupt to intr-hw1
+: (intr-hw2) ( -- ) 2 .intr-hw ; ' (intr-hw2) to intr-hw2
+: (intr-hw3) ( -- ) 3 .intr-hw ; ' (intr-hw3) to intr-hw3
+: (intr-hw4) ( -- ) 4 .intr-hw ; ' (intr-hw4) to intr-hw4
+
+headers
+
Added: cpu/mips/broadcom/avx/mappci.fth
===================================================================
--- cpu/mips/broadcom/avx/mappci.fth (rev 0)
+++ cpu/mips/broadcom/avx/mappci.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,34 @@
+purpose: PCI physical address mapping to root node
+copyright: Copyright 1994-2001 FirmWorks All Rights Reserved
+
+hex
+
+headerless
+
+\ map-pci-phys creates a virtual mapping for the PCI physical address range
+\ "paddr io? size", returning its virtual address "vaddr". It does so by
+\ first translating the PCI physical base address "paddr io?" to the
+\ corresponding physical address in the parent node's address space (which
+\ is often the primary system bus address space, but in this case is the
+\ VL bus address space), and then calling the parent's "map-in" method.
+\ "io?" is false for PCI memory space, true for PCI I/O space.
+
+: map-pci-phys ( paddr io? phys.hi size -- vaddr )
+ -rot 2drop " map-in" $call-parent
+;
+
+\ >pci-devaddr translates the DMA address "parent-devaddr", which is in the
+\ parent node's physical address space, to the corresponding DMA address
+\ "pci-devaddr" in the PCI physical address space (in PCI memory space; DMA
+\ to PCI I/O space is not possible).
+
+: >pci-devaddr ( parent-devaddr -- pci-devaddr ) h# 0 + ;
+
+\ pci-devaddr> translates the DMA address "pci-devaddr", which is in the
+\ PCI physical address space (in PCI memory space; DMA to PCI I/O space is
+\ not possible), to the corresponding DMA address "parent-devaddr" in the
+\ parent node's physical address space.
+
+: pci-devaddr> ( pci-devaddr -- parent-devaddr ) h# 0 - ;
+headers
+
Added: cpu/mips/broadcom/avx/ofwfind.fth
===================================================================
--- cpu/mips/broadcom/avx/ofwfind.fth (rev 0)
+++ cpu/mips/broadcom/avx/ofwfind.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,87 @@
+purpose: Start redundant OFW code
+copyright: Copyright 2001 Firmworks. All Rights Reserved.
+
+transient
+: delay-ms ( ms -- )
+ d# 100.0000 * d# 830 + d# 1660 / " t0 set" evaluate
+ " begin t0 0 = until t0 -1 t0 addi" evaluate
+;
+resident
+
+label compute-chksum ( v0: ofw base -- v1: chksum )
+ /rom t3 set
+ 0 v1 set
+
+ begin
+ t3 -1 t3 addi
+ v0 t3 t2 add
+ t2 0 t0 lbu
+ t0 v1 v1 add
+ t3 0 = until
+ nop
+
+ ra jr nop
+end-code
+
+label new-ofw-ok? ( v0: current ofw base -- v0: 0 | new ofw base )
+ ra t7 move \ Save return address
+
+carret ?report
+linefeed ?report
+ascii c ?report
+ascii h ?report
+ascii k ?report
+ascii s ?report
+ascii u ?report
+ascii m ?report
+ascii . ascii . ascii . ?report ?report ?report
+
+ h# 8.0000 t0 set
+ v0 t0 v0 or \ new ofw base
+
+ compute-chksum bal nop
+ v1 h# ff v1 andi
+ h# a5 t0 set
+ v1 t0 <> if nop
+ 0 v0 set
+ then
+
+ t7 jr nop
+end-code
+
+\ If currently running from backup OFW and new OFW is found sanguine,
+\ ?jump-to-new-ofw will not return to the caller. Instead, control
+\ will be transferred to the new OFW reset entry point. Otherwise,
+\ ?jump-to-new-ofw will return to the caller to continue OFW startup.
+
+\ Preserve ra in case we return to the caller.
+
+label ?jump-to-new-ofw ( -- )
+ ra t8 move \ Save return address
+
+ here 4 + bal nop
+ ra t1 move \ Address of instruction
+
+ h# 8.0000 t0 set
+ t1 t0 t1 and
+
+ t1 0 = if nop \ Running from backup OFW now
+ h# fff0.0000 t0 set
+ ra t0 v0 and \ Current ofw base
+ new-ofw-ok? bal nop \ Check if new ofw is ok
+ v0 0 = if nop \ No good new ofw found, use backup
+ ascii O ?report
+ ascii L ?report
+ ascii D ?report
+ else nop
+ ascii N ?report
+ ascii E ?report
+ ascii W ?report
+ d# 10 delay-ms
+ v0 jr nop \ Jump to new ofw
+ then
+ then
+
+ t8 jr nop \ Return to caller
+end-code
+
Added: cpu/mips/broadcom/avx/pcicfg.fth
===================================================================
--- cpu/mips/broadcom/avx/pcicfg.fth (rev 0)
+++ cpu/mips/broadcom/avx/pcicfg.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,22 @@
+purpose: Configuration space access using "configuration mechanism 1"
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+\ Ostensibly this applies to the PCI bus and thus should be in the PCI node.
+\ However, many of the host bridge registers are accessed via this mechanism,
+\ so it is convenient to make the configuration access words globally-visible.
+\ This mechanism works for several different PCI host bridges.
+
+headerless
+
+: config-map ( config-adr -- port )
+ dup h# ffff.fffc and h# 8000.0000 or pci-cf8 rl!
+ 3 and pci-cfc +
+;
+
+: config-l@ ( config-addr -- l ) config-map rl@ ;
+: config-l! ( l config-addr -- ) config-map rl! ;
+: config-w@ ( config-addr -- w ) config-map rw@ ;
+: config-w! ( w config-addr -- ) config-map rw! ;
+: config-b@ ( config-addr -- c ) config-map rb@ ;
+: config-b! ( c config-addr -- ) config-map rb! ;
+
Added: cpu/mips/broadcom/avx/pcinode.fth
===================================================================
--- cpu/mips/broadcom/avx/pcinode.fth (rev 0)
+++ cpu/mips/broadcom/avx/pcinode.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,60 @@
+purpose: System-specific portions of PCI bus package
+copyright: Copyright 2001 Firmworks All Rights Reserved
+
+: init ( -- ) ;
+
+d# 33,333,333 " clock-frequency" integer-property
+
+\ Establish limits for address space allocation
+
+pci-mem-pa to first-mem \ 1400.0000-17ff.ffff
+first-mem h# 400.0000 + to mem-space-top
+
+pci-io-pa to first-io \ 1300.0000-131f.ffff
+first-io h# 20.0000 + to io-space-top
+
+\ The phys.hi component of the PCI addresses below indicate the
+\ address space type (I/O = 0100.0000, Mem = 0200.0000, etc.)
+
+\ -----------PCI Address--- --Sys Addr-- ------size-----
+\ phys.hi .mid .low phys.hi .hi .lo
+
+0 0 encode-bytes
+ 0100.0000 +i 0+i 0+i pci-io-base +i 0+i 0020.0000 +i \ PCI I/O
+ 0200.0000 +i 0+i 0+i pci-mem-base +i 0+i 0400.0000 +i \ PCI Mem
+" ranges" property
+
+\ These package methods use the global versions of the configuration
+\ access words.
+
+: config-l@ ( config-addr -- l ) config-l@ ;
+: config-l! ( l config-addr -- ) config-l! ;
+: config-w@ ( config-addr -- w ) config-w@ ;
+: config-w! ( w config-addr -- ) config-w! ;
+: config-b@ ( config-addr -- c ) config-b@ ;
+: config-b! ( c config-addr -- ) config-b! ;
+
+fload ${BP}/dev/pci/intmap.fth \ Generic interrupt mapping code
+
+\ This table describes the wiring of PCI interrupt pins at the PCI slots
+\ to ISA IRQs.
+
+create slot-map
+\ Dev# Pin A Pin B Pin C Pin D
+ e c, 2 c, ff c, ff c, ff c, \ Ethernet
+ f c, 1 c, ff c, ff c, ff c, \ Card bus
+ ff c, \ End of list
+
+also forth definitions
+" e,f" dup config-string pci-probe-list
+previous definitions
+
+warning @ warning off
+\ The io-base handling really ought to be in the root node, but
+\ that would require more changes than I'm willing to do at present.
+: map-out ( vaddr size -- )
+ over io-base u>= if 2drop exit then ( vaddr size )
+ map-out ( )
+;
+warning !
+
Added: cpu/mips/broadcom/avx/physaddr.fth
===================================================================
--- cpu/mips/broadcom/avx/physaddr.fth (rev 0)
+++ cpu/mips/broadcom/avx/physaddr.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,46 @@
+purpose: Physical addresses for AVX
+copyright: Copyright 2001 FirmWorks All Rights Reserved
+
+headerless
+
+\ create for-bcm93730 \ Comment this out for AVX board
+
+h# 0000.0000 constant ram-pa \ 0000.0000-03ff.ffff
+h# 1000.0000 constant bc-reg-pa \ 1000.0000-1000.4fff
+
+h# 1300.0000 constant pci-io-pa \ 1300.0000-131f.ffff
+h# 13c0.0000 constant bc-pci-reg-pa \ 13c0.0000-13c0.00ff
+h# 13e0.0cf8 constant bc-pci-cf8
+h# 13e0.0cfc constant bc-pci-cfc
+h# 1400.0000 constant pci-mem-pa \ 1400.0000-17ff.ffff
+h# 1c00.0000 constant 68k-io-pa \ 1c00.0000-1fff.ffff
+h# 1c00.1000 constant atmel-pa \ 1c00.1000-1c00.13ff
+[ifdef] for-bcm93730
+h# 1500.07b0 constant uart-pa \ COM1 on BCM93730
+[else]
+h# 1c00.2000 constant uart-pa \ COM1
+[then]
+h# 1c00.2800 constant uart2-pa \ COM2
+h# 1c00.3000 constant led-pa
+h# 1fc0.0000 constant rom-pa
+
+68k-io-pa kseg1 + constant 68k-io-base
+pci-io-pa kseg1 + constant pci-io-base
+pci-mem-pa kseg1 + constant pci-mem-base
+uart-pa kseg1 + constant uart-base
+uart2-pa kseg1 + constant uart2-base
+bc-pci-reg-pa kseg1 + constant pci-reg-base
+bc-reg-pa kseg1 + constant bc-reg-base
+bc-pci-cf8 kseg1 + constant pci-cf8
+bc-pci-cfc kseg1 + constant pci-cfc
+
+h# 0400.0000 constant /ram-bank
+
+h# 400 constant /resetjmp
+
+0 constant rom-base
+h# 6.0000 constant /rom
+rom-pa kseg1 + constant rom-pa
+rom-pa /resetjmp + constant dropin-base
+
+headers
Added: cpu/mips/broadcom/avx/report.fth
===================================================================
--- cpu/mips/broadcom/avx/report.fth (rev 0)
+++ cpu/mips/broadcom/avx/report.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,41 @@
+also forth definitions
+[ifdef] debug-reset
+[ifdef] for-bcm93730
+: ?report ( char -- )
+ " uart-base d# 16 >> t0 lui" evaluate
+ " begin t0 h# 7b5 t1 lbu t1 1 t1 andi t1 0 <> until nop" evaluate
+ ( char ) " t1 set t1 t0 h# 7b4 sb" evaluate
+;
+[else]
+: ?report ( char -- )
+ " uart-base d# 16 >> t0 lui" evaluate
+ " begin t0 h# 23fd t1 lbu t1 h# 20 t1 andi t1 0 <> until nop" evaluate
+ ( char ) " t1 set t1 t0 h# 23f8 sb " evaluate
+;
+[then]
+[else]
+: ?report ( char -- ) drop ;
+[then]
+
+: putbyte ( $a0 -- )
+\ " $a0 h# f $a0 andi $a0 h# 30 $a0 addi" evaluate
+ " $a0 h# f $a0 andi $a0 d# -10 t1 addi" evaluate
+ " t1 0< if nop $a0 h# 30 $a0 addi else nop $a0 h# 57 $a0 addi then" evaluate
+ " begin t0 h# 3fd t1 lbu t1 h# 20 t1 andi t1 0 <> until nop" evaluate
+ " $a0 t0 h# 3f8 sb " evaluate
+ " begin t0 h# 3fd t1 lbu t1 h# 20 t1 andi t1 0 <> until nop" evaluate
+;
+: dot ( a0 -- )
+ " uart-base t0 set $a0 t2 move" evaluate
+ " t2 d# 28 $a0 srl putbyte" evaluate
+ " t2 d# 24 $a0 srl putbyte" evaluate
+ " t2 d# 20 $a0 srl putbyte" evaluate
+ " t2 d# 16 $a0 srl putbyte" evaluate
+ " t2 d# 12 $a0 srl putbyte" evaluate
+ " t2 d# 8 $a0 srl putbyte" evaluate
+ " t2 d# 4 $a0 srl putbyte" evaluate
+ " t2 0 $a0 srl putbyte" evaluate
+ bl ?report
+;
+previous definitions
+
Added: cpu/mips/broadcom/avx/reset.bth
===================================================================
--- cpu/mips/broadcom/avx/reset.bth (rev 0)
+++ cpu/mips/broadcom/avx/reset.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,625 @@
+purpose: Low-level startup code for Intreon AVX
+copyright: Copyright 1998-2001 Firmworks All Rights Reserved
+
+command: &native &this
+build-now
+
+create debug-reset \ Comment out in order to single step under PMON
+\ create debug-memory
+\ create debug-memory-test
+
+\needs start-assembling fload ${BP}/cpu/mips/asmtools.fth
+\needs write-dropin fload ${BP}/forth/lib/mkdropin.fth
+
+hex
+
+fload ${BP}/cpu/mips/ksegaddr.fth
+fload ${BP}/cpu/mips/broadcom/avx/physaddr.fth
+fload ${BP}/cpu/mips/broadcom/avx/report.fth
+
+create broadcom
+h# 10.0000 constant /fw-memory
+
+rom-pa constant bootrom-pa
+
+also forth definitions
+: c$, ( adr len -- )
+ 1+ here swap note-string dup allot move 4 (align)
+;
+previous definitions
+
+also mips-assembler definitions
+: $find-dropin, ( adr len -- )
+[ifdef] notdef
+ tuck 2>r ( len )
+ here + 9 + \ 9 = null(1) + call+delay slot(8)
+ 4 round-up \ pad string end adr to next instr-+
+ ( adr-of-find-di ) asm( $0 bgezal )asm \ jump to find-dropin call below |
+ asm( ra $a0 move )asm \ set string arg for find-dropin |
+ 2r> c$, \ place string |
+ " find-dropin bal" evaluate \ and call find routine <----+
+ asm( nop )asm
+[else]
+ " find-dropin bal nop" evaluate \ call find routine
+ c$, \ place string after delay slot
+[then]
+;
+previous definitions
+
+h# 800e.0000 constant stack-offset
+h# 800f.0000 constant workspace-offset
+h# 8010.0000 constant inflate-offset
+
+start-assembling
+
+/resetjmp h# 20 + to asm-origin \ Skip resetjmp wad and dropin header
+
+label my-entry
+\ **** This is the primary entry point; it will contain a branch instruction
+\ that skips a few subroutines and lands at the startup sequence. That
+\ branch instruction is patched in below. The entry point for this module
+\ is in turn reached from a branch instruction at the beginning of the ROM,
+\ which is created by the file arch/dna/resetvec.bth
+ 0 , \ To be patched later
+ nop
+end-code
+
+[ifdef] for-bcm93730
+transient
+create n2c h# c0 c, h# f9 c, h# a4 c, h# b0 c, h# 99 c, h# 92 c, h# 82 c, h# f8 c,
+ h# 80 c, h# 90 c, h# 88 c, h# 83 c, h# c6 c, h# a1 c, h# 86 c, h# 8e c,
+: nibble2char ( t1: nibble -- t1: led-char )
+ " t1 h# f t1 andi" evaluate
+ " t1 0 = if nop h# c0 t1 set nop then" evaluate
+ " 1 t0 set t0 t1 = if nop h# f9 t1 set nop then" evaluate
+ " 2 t0 set t0 t1 = if nop h# a4 t1 set nop then" evaluate
+ " 3 t0 set t0 t1 = if nop h# b0 t1 set nop then" evaluate
+ " 4 t0 set t0 t1 = if nop h# 99 t1 set nop then" evaluate
+ " 5 t0 set t0 t1 = if nop h# 92 t1 set nop then" evaluate
+ " 6 t0 set t0 t1 = if nop h# 82 t1 set nop then" evaluate
+ " 7 t0 set t0 t1 = if nop h# f8 t1 set nop then" evaluate
+ " 8 t0 set t0 t1 = if nop h# 80 t1 set nop then" evaluate
+ " 9 t0 set t0 t1 = if nop h# 90 t1 set nop then" evaluate
+ " d# 10 t0 set t0 t1 = if nop h# 88 t1 set nop then" evaluate
+ " d# 11 t0 set t0 t1 = if nop h# 83 t1 set nop then" evaluate
+ " d# 12 t0 set t0 t1 = if nop h# c6 t1 set nop then" evaluate
+ " d# 13 t0 set t0 t1 = if nop h# a1 t1 set nop then" evaluate
+ " d# 14 t0 set t0 t1 = if nop h# 86 t1 set nop then" evaluate
+ " d# 15 t0 set t0 t1 = if nop h# 8e t1 set nop then" evaluate
+;
+: led0! ( t1: 16-bit -- )
+ " t1 d# 12 t1 srl" evaluate
+ nibble2char
+ " h# b500.0000 t0 set" evaluate
+ " t1 t0 h# 794 sb" evaluate
+;
+: led1! ( t1: 16-bit -- )
+ " t1 8 t1 srl" evaluate
+ nibble2char
+ " h# b500.0000 t0 set" evaluate
+ " t1 t0 h# 795 sb" evaluate
+;
+: led2! ( t1: 16-bit -- )
+ " t1 4 t1 srl" evaluate
+ nibble2char
+ " h# b500.0000 t0 set" evaluate
+ " t1 t0 h# 79a sb" evaluate
+;
+: led3! ( t1: 16-bit -- )
+ nibble2char
+ " h# b500.0000 t0 set" evaluate
+ " t1 t0 h# 79b sb" evaluate
+;
+resident
+[then]
+
+\ This subroutine is used by the startup code.
+\ It compares two null-terminated strings, returning zero if they match.
+\ Destroys: r2, r3
+label strcmp ( $a0: str1 $a1: str2 -- v0: 0 if match, nonzero if mismatch )
+ $a0 t0 move
+ begin
+ t0 0 $a2 lbu
+ $a1 0 $a3 lbu
+ $a2 $a3 <> if
+ t0 1 t0 addiu \ (delay)
+ ra jr
+ $a3 $a2 v0 sub \ (delay)
+ then
+ $a2 0 = until
+ $a1 1 $a1 addiu \ (delay)
+
+ ra jr
+ 0 v0 set \ (delay)
+end-code
+
+\ This subroutine is used by the startup code.
+\ It searches the ROM for a dropin module whose name field matches the
+\ null-terminated string that is at the return address.
+\ Destroys: $a0-$a3, t4-t7
+label find-dropin ( s3: rom-pa -- v0: adr | 0 )
+ ra $a0 move \ address of string
+ begin
+ ra 0 $a1 lbu \ Get string byte
+ $a1 0 = until \ Look for null terminator
+ ra 1 ra addiu \ (delay) Advance to next character
+
+ \ ra now points to the byte after the null character
+ ra 3 ra addiu \ Round up to longword boundard
+ 3 invert $at set
+ ra $at t7 and \ and round
+
+\ h# 4f424d44 t4 set \ "OBMD"
+ h# 444d424f t4 set \ "OBMD" little-endian
+\ bootrom-pa /resetjmp + t5 set \ ROM base + (resetjmp wad)
+ /resetjmp t5 set
+ t5 s3 t5 add \ active ROM base + (resetjmp wad)
+ begin
+ t5 0 t6 lw
+ t4 t6 = while nop
+
+ strcmp bal \ $a1 = test$, $a0 = sought$
+ t5 h# 10 $a1 addiu \ (delay)point to dropin name in header
+ v0 0 = if nop
+ t7 jr \ return
+ t5 v0 move \ (delay) return value is adr of "OBMD"
+ then
+
+ t5 4 t3 addiu \ offset to size of dropin
+
+[ifdef] broadcom
+ t3 0 t1 lbu
+ t1 d# 24 t6 sll
+ t3 1 t1 lbu
+ t1 d# 16 t1 sll t6 t1 t6 or
+ t3 2 t1 lbu
+ t1 d# 8 t1 sll t6 t1 t6 or
+ t3 3 t1 lbu
+ t6 t1 t6 or
+[else]
+ t3 1 t0 lwr \ get size of dropin (big-endian)
+ t3 3 t0 lwr \ get least significant half word
+ h# ffff t1 set
+ t0 t1 t6 and
+
+ t3 2 t0 lwl \ get most significant half word
+ t3 0 t0 lwl
+ h# ffff.0000 t1 set
+ t0 t1 t0 and
+ t0 t6 t6 or
+[then]
+
+ t6 h# 23 t6 addiu \ add size + header(20) + roundup(3) to
+ t5 t6 t5 addu \ locate next dropin
+ 3 invert $at set
+ repeat
+ t5 $at t5 and \ (delay) round up
+
+ 0 v0 set \ return value is 0 (failure)
+ t7 jr \ No more dropins; return
+ nop
+end-code
+
+\ This subroutine is used by the startup code.
+\ It copies n (a2) bytes of memory from src (a1) to dst (a0)
+\ Destroys: a0-a3
+label memcpy ( a0: dst a1: src a2: n -- )
+ $a0 $a2 $a2 addu \ Ending address
+
+ $a0 $a2 <> if nop
+ begin
+ $a1 0 $a3 lbu
+ $a1 1 $a1 addiu
+ $a3 $a0 0 sb
+ $a0 $a2 = until
+ $a0 1 $a0 addiu \ (delay)
+ then
+
+ ra jr nop
+end-code
+here memcpy - constant /memcpy
+
+\ Flush the VR4300 Data cache for the first time
+label init-cache ( -- ) \ Destroys: $a0, $a1
+
+ \ Temporarily disable parity and CE
+ d# 12 v0 mfc0
+
+ h# 2.0000 invert t0 set
+ t0 v0 t0 and
+ h# 1.0000 t1 set
+ t0 t1 t0 or
+ d# 12 t0 mtc0
+
+ascii c ?report
+
+ \ Disable secondary cache
+ d# 16 t0 mfc0
+ h# 1007 invert t1 set
+ t0 t1 t0 and
+ d# 16 t0 mtc0
+\ t0 3 t0 ori \ CONFIG, k0=write back
+\ t0 2 t0 ori \ CONFIG, k0=uncached
+ t0 1 t0 ori \ CONFIG, k0=write thru, write allocate
+ d# 16 t0 mtc0
+ nop nop nop nop
+
+ascii a ?report
+
+ \ load valid virtual addresses into the cache tags
+ d# 28 $0 mtc0 \ Set CP0 TAGLO register
+ d# 29 $0 mtc0 \ Set CP0 TAGHI register
+
+ h# 8000.0000 $a0 set
+ d# 1024 d# 32 * $a1 set
+ $a0 $a1 $a1 addu \ Add cache size to give end address
+
+ascii c ?report
+
+ \ Init Icache
+ begin
+ $a0 0 h# 8 cache \ Index store tag primary icache
+ nop
+ $a0 0 h# 14 cache \ Fill Icache
+ nop
+ $a0 0 h# 8 cache \ Index store tag primary icache
+ nop
+ $a1 $a0 = until
+ $a0 d# 32 $a0 addiu \ Icache line size
+
+ascii h ?report
+
+ \ Init Dcache
+ h# 8000.0000 $a0 set
+ d# 1024 d# 32 * $a1 set
+ $a0 $a1 $a1 addu \ Add cache size to give end address
+ begin
+ $a0 0 h# 9 cache \ Index store tag primary dcache
+ $a1 $a0 = until
+ $a0 d# 32 $a0 addiu \ Dcache line size
+
+ h# 8000.0000 $a0 set
+ d# 1024 d# 32 * $a1 set
+ $a0 $a1 $a1 addu \ Add cache size to give end address
+ begin
+ $0 $a0 0 sw \ Zero cache
+ $a1 $a0 = until
+ $a0 d# 32 $a0 addiu \ Dcache line size
+
+ h# 8000.0000 $a0 set
+ d# 1024 d# 32 * $a1 set
+ $a0 $a1 $a1 addu \ Add cache size to give end address
+ begin
+ $a0 0 h# 9 cache \ Index store tag primary dcache
+ $a1 $a0 = until
+ $a0 d# 32 $a0 addiu \ Dcache line size
+
+ascii e ?report
+
+ \ Restore status register
+ d# 12 v0 mtc0
+
+ ra jr nop
+end-code
+
+\ Write-back and invalidate the VR4300 data cache.
+label flush-dcache ( -- ) \ Destroys: $a0, $a1
+ h# 8000.0000 $a1 set
+ d# 1024 d# 32 * $a0 set
+ $a1 $a0 $a0 addu \ Add cache size to give end address
+
+ begin
+\ d# 28 $0 mtc0 \ Set CP0 TAGLO register
+ nop
+ $a1 0 h# 1 cache \ op 0/1(1): index wb&invalidate primary dcache
+ nop
+ $a0 $a1 = until
+ $a1 d# 32 $a1 addiu \ Dcache line size
+
+ ra jr nop
+end-code
+
+\ Invalidate the VR4300 instruction cache.
+label invalidate-icache ( -- ) \ Destroys: $a0, $a1
+ h# 8000.0000 $a1 set
+ d# 1024 d# 32 * $a0 set
+ $a1 $a0 $a0 addu \ Add cache size to give end address
+
+ begin
+\ d# 28 $0 mtc0 \ Set CP0 TAGLO register
+ nop
+ $a1 0 h# 0 cache \ op 0/0(0): index invalidate primary icache
+ nop
+ $a0 $a1 = until
+ $a1 d# 32 $a1 addiu \ Dcache line size
+
+ ra jr nop
+end-code
+
+label sync-cache ( -- ) \ Destroys: $a0, $a1, $a3
+ ra $a3 move
+
+ flush-dcache bal nop
+ invalidate-icache bal nop
+
+ $a3 jr nop
+end-code
+
+fload ${BP}/cpu/mips/broadcom/avx/initbc.fth
+fload ${BP}/cpu/mips/broadcom/avx/initcom1.fth
+fload ${BP}/cpu/mips/broadcom/avx/ofwfind.fth
+
+\ This is the main entry point for this dropin module
+label start
+
+ \ Jump up to KSEG1
+\ start asm-base - asm-origin + bootrom-pa + h# 10 + k0 la
+\ k0 jr nop
+
+ \ Initialize CP0 registers
+[ifdef] for-bcm93730
+ h# 0040.0000 v0 li
+ d# 12 v0 mtc0 \ Status
+ d# 13 $0 mtc0 \ Set CP0 cause register
+ d# 18 $0 mtc0 \ Set CP0 WATCHLO register
+ d# 19 $0 mtc0 \ Set CP0 WATCHHI register
+ d# 16 t1 mfc0
+ h# 00f6.66f0 t0 set
+ t1 t0 t1 and
+ t1 3 t1 ori
+ d# 16 t1 mtc0 \ Config
+[else]
+ d# 12 v1 mfc0
+ h# 3441.0000 v0 li \ SR_BEV, disable parity
+ v0 v1 v0 or
+ d# 12 v0 mtc0 \ Set CP0 status register
+ d# 13 $0 mtc0 \ Set CP0 cause register
+ d# 18 $0 mtc0 \ Set CP0 WATCHLO register
+ d# 19 $0 mtc0 \ Set CP0 WATCHHI register
+[then]
+
+ \ Initialize hardware
+ init-broadcom bal nop
+ init-com1 bal nop
+
+ \ If currently running from backup OFW and new OFW is found sanguine,
+ \ ?jump-to-new-ofw will not return here. Otherwise, control will
+ \ come back here for further OFW startup.
+
+ ?jump-to-new-ofw bal nop
+
+ here 4 + bal
+ h# fff8.0000 t0 set
+ ra t0 s3 and \ Active ROM base
+
+[ifdef] testled
+h# cdef t1 set led0!
+h# cdef t1 set led1!
+h# cdef t1 set led2!
+h# cdef t1 set led3!
+begin again
+[then]
+
+carret ?report
+linefeed ?report
+
+ascii A ?report
+ " start" $find-dropin, \ Assemble call to find-dropin w/literal arg
+ v0 0 = if
+ nop
+ascii n ?report
+ascii o ?report
+bl ?report
+ascii s ?report
+ascii t ?report
+ascii a ?report
+ascii r ?report
+ascii t ?report
+ begin again nop
+ then
+
+ v0 h# 20 v0 addi
+ v0 ra jalr
+ nop
+
+ v0 s2 move \ Save RAM top
+ /fw-memory h# 20 + s0 set \ Compute firmware RAM base address
+ v0 s0 s0 sub
+
+ascii B ?report
+ init-cache bal nop nop nop nop
+
+ascii C ?report
+[ifdef] debug-memory-test
+ " test" $find-dropin,
+[else]
+ " firmware" $find-dropin, \ Assemble call to find-dropin w/literal arg
+[then]
+
+ v0 0 = if
+ nop
+ascii n ?report
+ascii o ?report
+bl ?report
+ascii o ?report
+ascii f ?report
+ascii w ?report
+ begin again nop
+ then
+
+ascii D ?report
+
+ v0 s1 move \ Save address of firmware dropin
+ v0 h# c t0 lw \ see if compressed
+ t0 0 <> if
+ nop
+ \ The firmware dropin is compressed, so we load the inflater into RAM
+ \ and use it to inflate the firmware into RAM
+
+ " inflate" $find-dropin,
+
+ascii i ?report
+
+ v0 4 t3 addiu \ offset to length of inflater
+
+[ifdef] broadcom
+ t3 0 t1 lbu
+ t1 d# 24 $a2 sll
+ t3 1 t1 lbu
+ t1 d# 16 t1 sll $a2 t1 $a2 or
+ t3 2 t1 lbu
+ t1 d# 8 t1 sll $a2 t1 $a2 or
+ t3 3 t1 lbu
+ $a2 t1 $a2 or
+[else]
+ t3 1 t0 lwr \ get size of dropin (big-endian)
+ t3 3 t0 lwr \ get least significant half word
+ h# ffff t1 set
+ t0 t1 $a2 and
+
+ t3 2 t0 lwl \ get most significant half word
+ t3 0 t0 lwl
+ h# ffff.0000 t1 set
+ t0 t1 t0 and
+ t0 $a2 $a2 or
+[then]
+
+ v0 h# 20 $a1 addi \ src: Base addr of inflater code in ROM
+ inflate-offset $a0 set \ dst: Base address of inflater
+ memcpy bal \ Copy the inflater
+ nop
+
+ascii n ?report
+
+ sync-cache bal
+ nop
+
+ascii f ?report
+
+ stack-offset sp set \ stack for inflater
+ s0 $a1 move \ Firmware RAM address
+ workspace-offset $a2 set \ Scratch RAM for inflater
+ inflate-offset t9 set \ RAM address of inflater
+ s1 h# 20 $a0 addi \ Adr of comp'd bits of firmware dropin
+ t9 ra jalr \ inflate the firmware
+ nop
+
+ascii l ?report
+
+ else
+ nop
+
+ascii c ?report
+ \ The firmware dropin isn't compressed, so we just copy it to RAM
+ascii o ?report
+
+ s1 4 t3 addiu \ offset to length of firmware
+
+[ifdef] broadcom
+ t3 0 t1 lbu
+ t1 d# 24 $a2 sll
+ t3 1 t1 lbu
+ t1 d# 16 t1 sll $a2 t1 $a2 or
+ t3 2 t1 lbu
+ t1 d# 8 t1 sll $a2 t1 $a2 or
+ t3 3 t1 lbu
+ $a2 t1 $a2 or
+[else]
+ t3 1 t0 lwr \ get size of dropin (big-endian)
+ t3 3 t0 lwr \ get least significant half word
+ h# ffff t1 set
+ t0 t1 $a2 and
+
+ t3 2 t0 lwl \ get most significant half word
+ t3 0 t0 lwl
+ h# ffff.0000 t1 set
+ t0 t1 t0 and
+ t0 $a2 $a2 or
+[then]
+
+ s1 h# 20 $a1 addi \ src: Skip dropin header
+ s0 $a0 move \ dst: Firmware RAM address
+ memcpy bal \ Copy the firmware
+ nop
+
+ascii p ?report
+ascii y ?report
+
+ then
+
+ sync-cache bal nop
+
+ascii E ?report
+
+ \ Jump to Forth (prom-cold-code)
+ s0 h# 20 s0 addiu
+ s0 $a0 move \ fw-RAM-base
+
+[ifdef] debug-memory
+carret ?report
+linefeed ?report
+$a0 s7 move
+dot
+s7 $a0 move
+[then]
+
+ s2 $a1 move \ fw-RAM-size
+
+[ifdef] debug-memory
+$a0 s7 move
+$a1 $a0 move dot
+s0 0 $a0 lw dot
+s0 4 $a0 lw dot
+s0 8 $a0 lw dot
+s0 h# c $a0 lw dot
+s0 h# 10 $a0 lw dot
+s0 h# 14 $a0 lw dot
+s0 h# 18 $a0 lw dot
+s0 h# 1c $a0 lw dot
+s7 $a0 move
+[then]
+
+[ifndef] debug-memory-test
+ s0 0 t0 lw \ Read offset of prom-cold-code
+ s0 t0 s0 addu
+[then]
+
+[ifdef] debug-memory
+$a0 s7 move
+s0 $a0 move dot
+s7 $a0 move
+[then]
+
+ here 4 + bal
+ h# fff8.0000 t0 set
+ ra t0 $a2 and \ Active ROM base
+
+ d# 12 t0 mfc0 \ Status
+ t0 4 t0 andi \ ERL=1 if reset exception
+ t0 0 = if
+ nop
+ s0 jr
+ nop
+ else
+ nop
+ d# 30 s0 mtc0 nop nop nop nop nop
+ d# 14 s0 mtc0 nop nop nop nop nop
+ eret
+ nop
+ then
+
+ \ Not reached, in theory
+ begin again
+ nop
+
+end-code
+
+also mips-assembler
+start my-entry put-branch
+previous
+
+end-assembling
+
+writing reset.di
+asm-base here over - 0 " reset" write-dropin
+ofd @ fclose
Added: cpu/mips/broadcom/avx/resetjmp.bth
===================================================================
--- cpu/mips/broadcom/avx/resetjmp.bth (rev 0)
+++ cpu/mips/broadcom/avx/resetjmp.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,92 @@
+purpose: Reset vector handler
+copyright: Copyright 2000-2001 Firmworks All Rights Reserved
+
+command: &native &this
+build-now
+
+\needs start-assembling fload ${BP}/cpu/mips/asmtools.fth
+
+\ The size of this module affects the constant /resetjmp in
+\ physaddr.fth.
+
+create debug-reset
+
+fload ${BP}/cpu/mips/ksegaddr.fth
+fload ${BP}/cpu/mips/broadcom/avx/physaddr.fth
+fload ${BP}/cpu/mips/broadcom/avx/report.fth
+
+start-assembling
+
+hex
+
+label resetvec
+ \ **** This is the initial entry point (reset vector) for the ROM.
+ \ It just branches past the following copyright string and past the
+ \ dropin module header for the "resetvec" dropin module, landing at
+ \ the entry point for that module. The "resetvec" dropin module
+ \ must appear in the ROM image right after the image that this file
+ \ creates.
+ here /resetjmp + h# 20 + $0 $0 beq
+ nop
+
+end-code
+
+ \ This copyright string will appear in the ROM right after the branch
+ \ instruction.
+ " Copyright 2001 FirmWorks All Rights Reserved" c$,
+
+ \ Locations 56-5b are reserved for a MAC address, for systems
+ \ that wish to store the MAC address in the boot ROM instead of
+ \ in a UID EEPROM.
+ h# 56 pad-to
+ h# ff c, h# ff c, h# ff c, h# ff c, h# ff c, h# ff c,
+
+ \ We reserve ROM locations 5c-5f for the PROMICE AI port and place
+ \ a distinct signature there. If the AI port is present and enabled
+ \ at those locations, it will overlay the ROM contents, thus allowing
+ \ the software to determine whether or not the AI port is present.
+
+ \ The signature should be tested at offset 5c+3 (5f), which is the
+ \ AI port status register. The value d4 is present at both 5c+0
+ \ and 5c+3, in case we ever have to handle big-endian systems that
+ \ byte-swap the ROM in some modes.
+
+ h# 5c pad-to \ Pad to the location reserved for the AI port
+ h# d4 c, h# 5a c, h# 5b c, h# d4 c, \ Signature distinct from AI port
+
+ h# 200 pad-to
+label tlbrefill
+ ascii T ?report ascii L ?report ascii B ?report
+ begin again
+ nop
+end-code
+
+ h# 280 pad-to
+label xtlbrefill
+ ascii X ?report ascii T ?report ascii L ?report ascii B ?report
+ begin again
+ nop
+end-code
+
+ h# 300 pad-to
+label cacheerr
+ ascii C ?report ascii E ?report ascii r ?report ascii r ?report
+ begin again
+ nop
+end-code
+
+ h# 380 pad-to
+label generalexc
+ ascii G ?report ascii e ?report ascii n ?report
+ begin again
+ nop
+end-code
+
+ /resetjmp pad-to
+ \ This module must have a fixed size of /resetjmp
+
+end-assembling
+
+writing resetjmp.img
+asm-base here over - ofd @ fputs
+ofd @ fclose
Added: cpu/mips/broadcom/avx/rom.bth
===================================================================
--- cpu/mips/broadcom/avx/rom.bth (rev 0)
+++ cpu/mips/broadcom/avx/rom.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,23 @@
+purpose: Top-level build script for Intreon AVX ROM
+copyright: Copyright 2001 FirmWorks All Rights Reserved
+
+command: &native &this
+in: romraw.img
+build-now
+
+\needs $add-dropin fload ${BP}/tools/mkdropin.fth
+
+\ Always re-create the builton.fth file when we make a new rom.img
+fload ${BP}/arch/mips/builton.bth
+
+: compute-chksum ( adr len -- chksum )
+ bounds 0 -rot ?do i c@ + loop
+;
+
+writing rom.img
+ " romraw.img" $read-file ( adr len )
+ 2dup compute-chksum -rot ( chksum adr len )
+ 2dup ofd @ fputs free-mem ( chksum )
+ h# ff and h# a5 swap - ofd @ fputc
+ofd @ fclose
+
Added: cpu/mips/broadcom/avx/romraw.bth
===================================================================
--- cpu/mips/broadcom/avx/romraw.bth (rev 0)
+++ cpu/mips/broadcom/avx/romraw.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,37 @@
+purpose: Top-level build script for Intreon AVX ROM
+copyright: Copyright 2001 FirmWorks All Rights Reserved
+
+command: &native &this
+in: resetjmp.img
+in: reset.di
+in: start.di
+in: test.di
+in: fw.img
+in: ${BP}/dev/kendin/build/ks8723.fc
+build-now
+
+\needs $add-dropin fload ${BP}/tools/mkdropin.fth
+
+\ Always re-create the builton.fth file when we make a new rom.img
+fload ${BP}/arch/mips/builton.bth
+
+h# 6.0000 constant rom-size
+: pad-file ( location -- )
+ ofd @ fsize
+ 2dup u< abort" The ROM image is too large"
+ 2dup - ." Unused memory = " .d cr
+ ?do h# ff ofd @ fputc loop
+;
+
+writing romraw.img
+ " resetjmp.img" $add-file \ Branch past initial dropin module header
+ " reset.di" $add-file
+ " start.di" $add-file
+ " test.di" $add-file
+ " fw.img" " firmware" $add-deflated-dropin
+\ " fw.img" " firmware" $add-dropin
+ " ${BP}/cpu/mips/inflate.img" " inflate" $add-dropin
+ " builton.fth" " probe-" $add-dropin
+ " ${BP}/dev/kendin/build/ks8723.fc" " pci13f0,201" $add-deflated-dropin
+ rom-size 1- pad-file \ reserve one byte as chksum byte
+ofd @ fclose
Added: cpu/mips/broadcom/avx/rootnode.fth
===================================================================
--- cpu/mips/broadcom/avx/rootnode.fth (rev 0)
+++ cpu/mips/broadcom/avx/rootnode.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,128 @@
+purpose: Methods for the root node using Broadcom Kseg address translation
+copyright: Copyright 1998-2001 Firmworks All Rights Reserved
+
+: root-map-in ( phys len -- virt )
+ " /" " map-in" execute-device-method drop
+;
+: root-map-out ( virt len -- )
+ " /" " map-out" execute-device-method drop
+;
+
+dev /
+extend-package
+
+1 encode-int " #address-cells" property
+
+0 0 encode-bytes
+ \ Base address size
+ h# 8000.0000 encode-int encode+ /ram-bank encode-int encode+
+" dma-ranges" property
+
+hex
+headers
+
+\ Static methods
+: decode-unit ( adr len -- phys ) push-hex $number if 0 then pop-base ;
+: encode-unit ( phys -- adr len ) push-hex (u.) pop-base ;
+
+\ Not-necessarily-static methods
+: open ( -- true ) true ;
+: close ( -- ) ;
+
+: map-in ( phys size -- virt )
+ drop dup 1400.0000 u< if
+ pci-io-base or
+ else
+ dup 8000.0000 u< if pci-mem-base or then
+ then
+;
+: map-out ( virtual size -- ) 2drop ;
+
+headerless
+list: dmalist
+listnode
+ /n field >dma-ua \ address obtained from alloc-mem, unaligned
+ /n field >dma-aa \ address passed on to caller, cache-line aligned
+ /n field >dma-len \ original length used to alloc-mem
+nodetype: dmanode
+
+0 dmalist !
+0 dmanode !
+0 value dma-aa
+
+: dma-aa=? ( node -- aa=? )
+ >dma-aa @ dma-aa =
+;
+: find-dmanode? ( -- prev-node this-node | 0 )
+ dmalist ['] dma-aa=? find-node
+;
+: alloc-dmanode ( -- node )
+ dmanode allocate-node dup dmalist last-node insert-after
+;
+: free-dmanode ( prev -- )
+ delete-after dmanode free-node
+;
+
+headers
+
+\ DMA memory is accessed via kseg1 on a cache line boundary in integral # of cache lines
+: dma-alloc ( size -- virt )
+ /cache-line + /cache-line round-up dup ( size' size' )
+ alloc-mem 2dup swap flush-d$-range ( size ua )
+ dup /cache-line round-up kseg1 or ( size ua aa )
+ dup >r ( size ua aa ) ( R: aa )
+ alloc-dmanode ( size ua aa node ) ( R: aa )
+ tuck >dma-aa ! ( size ua node ) ( R: aa )
+ tuck >dma-ua ! ( size node ) ( R: aa )
+ >dma-len ! ( ) ( R: aa )
+ r>
+;
+: dma-free ( virt size -- )
+ over to dma-aa find-dmanode? ?dup if
+ dup >dma-ua @ swap >dma-len @ free-mem
+ free-dmanode 2drop
+ else
+ free-mem
+ then
+;
+: dma-map-in ( virt size cacheable -- devaddr )
+ drop 2dup pcicache-wbinv
+ drop h# 1fff.ffff and
+;
+: dma-map-out ( virt devaddr size -- ) pcicache-wbinv drop ;
+: dma-sync ( virt devaddr size -- ) pcicache-wbinv drop ;
+: dma-push ( virt devaddr size -- ) pcicache-inv drop ;
+: dma-pull ( virt devaddr size -- ) pcicache-wbinv drop ;
+
+finish-device
+
+device-end
+
+headerless
+\ Call this after the system-mac-address is determined, which is typically
+\ done near the end of the probing process.
+: set-system-id ( -- )
+ system-mac-address dup if ( adr 6 )
+ " /" find-device ( adr 6 )
+
+ \ Convert the six bytes of the MAC address into a string of the
+ \ form 0NNNNNNNNNN, where N is an uppercase hex digit.
+ push-hex ( adr 6 )
+
+ <# bounds swap 1- ?do ( )
+ i c@ u# u# drop ( )
+ -1 +loop ( )
+ 0 u# u#> ( adr len )
+
+ 2dup upper ( adr len ) \ Force upper case
+
+ pop-base ( adr len )
+
+ encode-string " system-id" property ( )
+
+ device-end
+ else
+ 2drop
+ then
+;
+headers
Added: cpu/mips/broadcom/avx/start.bth
===================================================================
--- cpu/mips/broadcom/avx/start.bth (rev 0)
+++ cpu/mips/broadcom/avx/start.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,199 @@
+purpose: Low-level startup code for Broadcom BCM7030RKPB1 memory controller
+copyright: Copyright 2001 Firmworks. All Rights Reserved.
+
+command: &native &this
+build-now
+
+\needs start-assembling fload ${BP}/cpu/mips/asmtools.fth
+\needs write-dropin fload ${BP}/forth/lib/mkdropin.fth
+
+create debug-reset
+
+fload ${BP}/cpu/mips/ksegaddr.fth
+fload ${BP}/cpu/mips/broadcom/avx/physaddr.fth
+fload ${BP}/cpu/mips/broadcom/avx/report.fth
+
+: bc-cfg! ( data idx -- )
+ pci-reg-base + " t0 set" evaluate
+ " t1 set" evaluate
+ " t1 t0 0 sw" evaluate
+;
+: bcl! ( data idx -- )
+ bc-reg-base + " t0 set" evaluate
+ " t1 set" evaluate
+ " t1 t0 0 sw" evaluate
+;
+: bcl-and! ( bits idx -- )
+ bc-reg-base + " t0 set" evaluate
+ " t0 0 t2 lw" evaluate
+ " t1 set" evaluate
+ " t1 t2 t1 and" evaluate
+ " t1 t0 0 sw" evaluate
+;
+: bcl-or! ( bits idx -- )
+ bc-reg-base + " t0 set" evaluate
+ " t0 0 t2 lw" evaluate
+ " t1 set" evaluate
+ " t1 t2 t1 or" evaluate
+ " t1 t0 0 sw" evaluate
+;
+: bcl-t1! ( t1: val idx -- )
+ bc-reg-base + " t0 set" evaluate
+ " t1 t0 0 sw" evaluate
+;
+: client! ( val client -- )
+ h# 2014 bcl! \ RB_TMC_CLIENT_INDEX_REG
+ h# 2018 bcl! \ RB_TMC_INDX_DATA_WR_REG
+;
+: tvrcp! ( val idx -- )
+ h# 20e0 bcl! \ RB_TVRCP_INDEX_ADDRS_REG
+ h# 20e4 bcl! \ RB_TVRCP_INDEX_DATA_REG
+ 1 h# 20e8 bcl! \ RB_TVRCP_INDEX_CNTL_REG, command write
+;
+
+: delay-ms ( ms -- )
+ d# 100.0000 * d# 830 + d# 1660 / " t0 set" evaluate
+ " begin t0 0 = until t0 -1 t0 addi" evaluate
+;
+
+start-assembling
+
+label my-entry
+ 0 , \ To be patched later
+ nop
+end-code
+
+label start-memory ( -- v0: RAM size )
+ ra s7 move
+
+ascii s ?report
+ h# 0000.0000 h# 2254 bcl! \ RB_TS1_X_TX_MAX_REG, primary display feeder tile hori size reg
+ h# 0000.0000 h# a0 bcl! \ Clear DISP_CTRL, display control reg
+ h# 0000.0000 h# 5c bcl! \ Clear CAP_CTRL, capture control reg
+ h# fff7.ffff h# 4 bcl-and! \ PM_CTRL, enable SDRAM clock 0, undocumented bit
+ h# 0000.0000 h# 0 bcl! \ MEM_BASE, SDRAM base at 0
+ h# 0000.0040 h# 8 bcl! \ MEM_CTRL, set SDRAM memory size to 64MB
+ h# 0000.0000 h# c bcl! \ GP_CTRL, GPIO reg
+ h# 0000.0001 h# 20 bcl-or! \ CPU_CTRL, allow chip to ack illegal read/write
+
+ascii d ?report
+ h# 0000.efff h# 20ac bcl! \ RB_TVRCP_SOFT_RESET_APPLY_REG1
+ h# 0000.efff h# 20b0 bcl! \ RB_TVRCP_SOFT_RESET_WITHDRAW_REG1
+ h# 0000.001f h# 20b4 bcl! \ RB_TVRCP_SOFT_RESET_APPLY_REG2
+ h# 0000.1000 h# 20ac bcl! \ RB_TVRCP_SOFT_RESET_APPLY_REG1
+[ifdef] for-bcm93730
+ h# 0000.8030 h# 2004 bcl! \ RB_TMC_MODE_CONTROL_REG, tRAS, CAS latency, burst len
+[else]
+ h# 0000.8020 h# 2004 bcl! \ RB_TMC_MODE_CONTROL_REG, tRAS, CAS latency, burst len
+[then]
+ h# 0000.00bc h# 2024 bcl! \ RB_TMC_DELAY_REG, memory controller timer 2 reg
+ h# 0000.1402 h# 2000 bcl! \ RB_TMC_CNTRL_CONFIG_REG, 4x2Mx16
+ h# 0000.0000 h# 2038 bcl! \ RB_TMC_MSA_MODE_REG
+ h# 0000.1000 h# 20b0 bcl! \ RB_TVRCP_SOFT_RESET_WITHDRAW_REG1
+
+ascii r ?report
+ h# f020 h# 00 client! \ CPU read, wraparound-cache-reads
+ h# f021 h# 01 client! \ CPU write, linear writes
+ h# 08a5 h# 02 client! \ Video win display #1, linear reads
+ h# 08a2 h# 03 client! \ Graphics display, linear reads
+ h# fff8 h# 04 client! \ Pirhanan 3D, linear read/writes
+ h# fff5 h# 05 client! \ Mem-to-mem DMA, linear read/writes
+ h# fff6 h# 06 client! \ PCI, linear read/writes
+ h# fff7 h# 07 client! \ Local 68k bus I/O, linear read/writes
+ h# 003e h# 08 client! \ Reserved
+ h# 003c h# 09 client! \ DMA command, linear read/writes
+ h# 003d h# 0a client! \ Paxel, linear read/writes
+ h# 000e h# 0b client! \ VBI write, linear writes
+ h# 000f h# 0c client! \ VBI read #1, linear read
+ h# 0010 h# 0d client! \ VBI read #2, linear read
+ h# 000b h# 0e client! \ Video win capture #1, linear writes
+ h# 0006 h# 0f client! \ Video win display #2, linear read
+ h# 001f h# 10 client! \ Video win capture #2, reserved
+ h# 0013 h# 11 client! \ PCM audio, linear read
+ h# 000a h# 12 client! \ Data transport, linear read/writes
+ h# 0011 h# 13 client! \ Audio read #1, linear read
+ h# 0012 h# 14 client! \ Audio read #2, linear read
+ h# 0008 h# 15 client! \ Audio write #1, linear writes
+ h# 0009 h# 16 client! \ Audio write #2, linear writes
+ h# 08a3 h# 17 client! \ Video scan feeder #1, video image raster reads
+ h# 08a4 h# 18 client! \ Video scan feeder #2, video image raster reads
+ h# 0019 h# 19 client! \ Row engine #1, video image MB accesses
+ h# 001a h# 1a client! \ Row engine #2, video image MB accesses
+ h# 000c h# 1b client! \ T-proc compr write, linear writes
+ h# 0014 h# 1c client! \ T-proc DMA, linear read/writes
+ h# 000d h# 1d client! \ V-proc DMA, linear read/writes
+ h# 001b h# 1e client! \ DMA soft access, linear/MPEG read-writes
+ h# 0007 h# 1f client! \ DRAM refresh
+
+ascii a ?report
+ h# 0000.0011 h# 0600 bcl-or! \ CPU_RAH_CTRL, enable read-ahead cache
+ h# 608 bcl-t1! \ CPU_RAH_INV_ALL
+
+ h# 0300 h# 0044 tvrcp! \ Init PCR clock to 27Mhz
+ h# 7fff h# 0042 tvrcp!
+ h# 3000 h# 0043 tvrcp!
+ h# 0800 h# 008c tvrcp! \ Expand the VBV buffer
+ h# 0000 h# 008d tvrcp!
+
+ \ Setup Broadcom PCI host bridge
+ h# 1400.0000 h# 58 bc-cfg! \ Setup PCI MEM window BARs. Use only win 0 now.
+ h# 1400.0000 h# 5c bc-cfg!
+ h# 1400.0000 h# 60 bc-cfg!
+ h# 1400.0000 h# 64 bc-cfg!
+ h# 1300.0000 h# 68 bc-cfg! \ Setup PCI IO window BAR. Use only win 0 now.
+ h# 0000.0000 h# 10 bc-cfg! \ Setup PCI SDRAM win 0.
+ h# 0000.0006 h# 50 bc-cfg! \ Setup SDRAM win0 size to 64MB
+ h# 0000.0000 h# 74 bc-cfg! \ Setup SDRAM endianness
+
+ascii m ?report
+
+ \ Rudimentary memory test
+ h# 5555.aaaa t1 set
+ h# a000.0000 t0 set
+ t1 t0 0 sw
+
+ h# a000.0000 t0 set
+ h# 10.0000 t3 set
+ /ram-bank kseg1 + h# 10.0000 - t2 set
+ h# 3333.cccc t1 set
+
+ begin
+ t0 t3 t0 add
+ t1 t0 0 sw
+ t0 t2 = until nop
+
+ h# a000.0000 t0 set
+ h# 5555.aaaa t2 set
+ t0 0 t1 lw
+
+ t1 t2 = if
+ nop
+ascii G ?report
+ascii o ?report
+ascii o ?report
+ascii d ?report
+ else
+ nop
+ascii B ?report
+ascii a ?report
+ascii d ?report
+begin again nop
+ then
+
+ \ Return to reset dropin
+ /ram-bank kseg0 + v0 set
+
+ s7 jr
+ nop
+
+end-code
+
+also mips-assembler
+start-memory my-entry put-branch
+previous
+
+end-assembling
+
+writing start.di
+asm-base here over - 0 " start" write-dropin
+ofd @ fclose
Added: cpu/mips/broadcom/avx/test.bth
===================================================================
--- cpu/mips/broadcom/avx/test.bth (rev 0)
+++ cpu/mips/broadcom/avx/test.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,34 @@
+purpose: A test program to run in memory
+copyright: Copyright 2001 Firmworks. All Rights Reserved.
+
+command: &native &this
+build-now
+
+\needs start-assembling fload ${BP}/cpu/mips/asmtools.fth
+\needs write-dropin fload ${BP}/tools/mkdropin.fth
+
+create debug-reset
+
+fload ${BP}/cpu/mips/ksegaddr.fth
+fload ${BP}/cpu/mips/broadcom/avx/physaddr.fth
+fload ${BP}/cpu/mips/broadcom/avx/report.fth
+
+start-assembling
+
+label my-entry
+h# 20 pad-to
+carret ?report
+linefeed ?report
+ascii H ?report
+ascii e ?report
+ascii l ?report
+ascii l ?report
+ascii o ?report
+begin again nop
+end-code
+
+end-assembling
+
+writing test.di
+asm-base here over - 0 " test" write-dropin
+ofd @ fclose
Added: cpu/mips/broadcom/avx/virtaddr.fth
===================================================================
--- cpu/mips/broadcom/avx/virtaddr.fth (rev 0)
+++ cpu/mips/broadcom/avx/virtaddr.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,12 @@
+purpose: Virtual addresses for AVX
+copyright: Copyright 2001 FirmWorks All Rights Reserved
+
+headerless
+
+0 value fw-virt-base \ Setup later after we know the memory size
+h# 10.0000 value fw-virt-size
+
+headers
+
+kseg0 h# 20.0000 + ' load-base set-config-int-default
+0 value load-limit \ Top address of area at load-base (set later)
Added: cpu/mips/broadcom/avx/vpd.fth
===================================================================
--- cpu/mips/broadcom/avx/vpd.fth (rev 0)
+++ cpu/mips/broadcom/avx/vpd.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,44 @@
+purpose: Specific name=value VPD variable manager
+copyright: Copyright 2001 FirmWorks All Rights Reserved
+
+hex
+
+\ Serial number words
+: (get-vpd-serial$) ( -- $ )
+ " serial-num" $getvpd if
+ " serial-num not found"
+ then
+;
+: get-vpd-serial$ ( -- $ ) select-fixed-vpd (get-vpd-serial$) ;
+: (.vpd-serial$) ( -- ) (get-vpd-serial$) type ;
+: .vpd-serial$ ( -- ) select-fixed-vpd (.vpd-serial$) ;
+
+\ Ethernet mac address words
+0 value mac-cnt
+: (get-vpd-mac$) ( -- true | mac$ false ) " eth-mac-addr" $getvpd ;
+: get-vpd-mac$ ( -- true | mac$ false ) select-fixed-vpd (get-vpd-mac$) ;
+: (get-vpd-mac#) ( -- true | m6 m5 m4 m3 m2 m1 false )
+ (get-vpd-mac$) ?dup if exit then
+ 0 to mac-cnt
+ ( mac$ ) 6 0 do
+ ascii : left-parse-string
+ $number ?leave
+ dup d# 255 > if drop leave then
+ -rot
+ mac-cnt 1+ to mac-cnt
+ loop
+ ( rem-mac$ ) nip
+ mac-cnt 6 <> or if
+ mac-cnt 0 ?do drop loop true
+ else
+ swap 2swap swap 2>r 2swap swap 2r> 2swap false
+ then
+;
+: get-vpd-mac# ( -- true | m6 m5 m4 m3 m2 m1 false )
+ select-fixed-vpd (get-vpd-mac#)
+;
+: (.vpd-mac) ( -- )
+ (get-vpd-mac$) if " eth-mac-addr not found" then
+ type
+;
+: .vpd-mac ( -- ) select-fixed-vpd (.vpd-mac) ;
Added: cpu/mips/build/build
===================================================================
--- cpu/mips/build/build (rev 0)
+++ cpu/mips/build/build 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,2 @@
+#!/bin/sh
+qemu-mipsel ../Linux/build $@
Property changes on: cpu/mips/build/build
___________________________________________________________________
Added: svn:executable
+ *
Added: cpu/mips/builder.bth
===================================================================
--- cpu/mips/builder.bth (rev 0)
+++ cpu/mips/builder.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,35 @@
+purpose: Builder load file for MIPS
+\ See license at end of file
+
+dictionary: ${BP}/cpu/mips/build/tools.dic
+command: &mipsfth &dictionary &this
+build-now
+
+fload ${BP}/ofw/tokenizer/tokenize.fth \ Tokenizer
+fload ${BP}/forth/lib/builder.fth \ Builder
+
+.( --- Saving builder.dic --- ) " builder.dic" $save-forth cr
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/builton.bth
===================================================================
--- cpu/mips/builton.bth (rev 0)
+++ cpu/mips/builton.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,69 @@
+purpose: Create "builton.fth" file containing the current date
+\ See license at end of file
+
+command: &native &this
+build-now
+
+\needs today fload ${BP}/forth/lib/date.fth
+
+: put$ ( adr len -- ) ofd @ fputs ;
+
+\ Creates a "builton.fth" file indicating the current date and time.
+\ It contains, for example:
+\ : build-date " December 17, 1996 18:26:50" ;
+\ d# 19961217 constant built-date-int
+\ dev /openprom
+\ built-date-int encode-int " built-on" property
+\ device-end
+
+writing builton.fth
+" \ Defines build-date"n" put$
+" : build-date "" " put$ today date$ put$ bl ofd @ fputc
+now time$ put$ " "" ;"n" put$
+
+" d# " put$
+base @ decimal
+today (.) put$ <# u# u# u#> put$ <# u# u# u#> put$
+base !
+" constant built-date-int"n" put$
+
+" d# " put$
+base @ decimal
+now (.) put$ <# u# u# u#> put$ <# u# u# u#> put$
+base !
+" constant built-time-int"n" put$
+
+" dev /openprom"n" put$
+" built-date-int encode-int "" built-on"" property"n" put$
+" device-end"n" put$
+
+ofd @ fclose
+
+\ We don't want to log the creation of this file, because doing so
+\ tends to cause double-recompiles in some cases.
+" builton.log" delete-file drop
+
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cache.fth
===================================================================
--- cpu/mips/cache.fth (rev 0)
+++ cpu/mips/cache.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,133 @@
+purpose: Cache operations for MIPS
+\ See license at end of file
+
+h# 8000 constant /dcache
+h# 8000 constant /icache
+
+d# 32 constant /cache-line
+: cache-bounds ( adr len -- end start )
+ bounds swap /cache-line round-up swap /cache-line round-down
+;
+
+\ TLB cache operations
+\ XXX secondary cache operations depends on processor
+code invalidate-i$-entry ( adr -- )
+ tos 0 h# 12 cache \ Invalidate secondary I$
+ tos 0 h# 10 cache \ Invalidate primary I$
+ sp tos pop
+c;
+code write-d$-entry ( adr -- )
+ tos 0 h# 19 cache \ WriteBack primary D$
+ tos 0 h# 1b cache \ WriteBack secondary D$
+ sp tos pop
+c;
+code flush-d$-entry ( adr -- )
+ tos 0 h# 15 cache \ WriteBack&Invalidate primary D$
+ tos 0 h# 17 cache \ WriteBack&Invalidate secondary D$
+ sp tos pop
+c;
+
+\ KSEG0 cache operations
+code invalidate-i$-index ( -- )
+ kseg0 t0 set
+ /icache t1 set
+ t0 t1 t1 addu
+
+ begin
+ t0 0 0 cache \ Index Invalidate primary I$
+ nop
+ t0 /cache-line t0 addiu
+ t0 t1 = until
+ nop
+c;
+code flush-d$-index ( -- )
+ kseg0 t0 set
+ /dcache t1 set
+ t0 t1 t1 addu
+
+ begin
+ t0 0 1 cache \ Index WriteBack&Invalidate primary D$
+ nop
+ t0 /cache-line t0 addiu
+ t0 t1 = until
+ nop
+c;
+
+
+
+: flush-d$-range ( adr len -- )
+ over h# f000.0000 and dup
+ kseg1 = if 3drop exit then
+ kseg0 = if
+ 2drop flush-d$-index
+ else
+ cache-bounds ?do i flush-d$-entry /cache-line +loop
+ then
+;
+
+: stand-sync-cache ( adr len -- )
+ over h# f000.0000 and dup
+ kseg1 = if 3drop exit then
+ kseg0 = if
+ 2drop flush-d$-index invalidate-i$-index
+ else
+ cache-bounds ?do
+ i write-d$-entry
+ i invalidate-i$-entry
+ /cache-line +loop
+ then
+;
+: stand-init-io ( -- )
+ stand-init-io
+ ['] stand-sync-cache to sync-cache
+;
+
+code get-dtag ( index -- )
+ tos 0 5 cache
+ sp tos pop
+c;
+code get-itag ( index -- )
+ tos 0 4 cache
+ sp tos pop
+c;
+
+: (.tag) ( -- )
+ taglo@ h# c0 and if taglo@ h# ffff.ff00 and 4 << u. then
+;
+defer .tag ' (.tag) to .tag
+: .dtags ( -- )
+ kseg0 /dcache bounds do
+ i get-dtag .tag
+ /cache-line +loop
+;
+: .itags ( -- )
+ kseg0 /icache bounds do
+ i get-itag .tag
+ /cache-line +loop
+;
+
+
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/call.fth
===================================================================
--- cpu/mips/call.fth (rev 0)
+++ cpu/mips/call.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,55 @@
+purpose: C subroutine call interface for MIPS
+\ See license at end of file
+
+code sp-call ( [ arg5 .. arg0 ] adr sp -- [ arg5 .. arg0 ] result )
+
+ sp t0 pop \ Get the subroutine address
+
+ sp 'user saved-sp sw \ Save for callbacks
+ rp 'user saved-rp sw \ Save for callbacks
+
+ tos h# -10 /n* t1 addiu \ Point to the new stack, leaving some extra
+ \ room since the compiler preamble stores
+ \ things above the stack pointer
+
+ \ Pass up to 6 arguments (first 0-3 in registers, 4 and 5 on the stack)
+ sp 0 /n* $a0 lw
+ sp 1 /n* $a1 lw
+ sp 2 /n* $a2 lw
+ sp 3 /n* $a3 lw
+ sp 4 /n* t2 lw t2 t1 0 /n* sw
+ sp 5 /n* t2 lw t2 t1 1 /n* sw
+
+ t1 sp move \ Switch to the new stack
+
+ t0 ra jalr nop \ Call the subroutine
+
+ 'user saved-rp rp lw \ Restore the return stack pointer
+ 'user saved-sp sp lw \ Restore the stack pointer
+ v0 tos move \ Return subroutine result
+c;
+: call ( [ arg5 .. arg0 ] adr -- [ arg5 .. arg0 ] result ) sp@ sp-call ;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/catchexc.fth
===================================================================
--- cpu/mips/catchexc.fth (rev 0)
+++ cpu/mips/catchexc.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,338 @@
+purpose: Exception handling for MIPS
+\ See license at end of file
+
+defer enterforth-hook ' noop is enterforth-hook
+
+only forth also hidden also forth definitions
+headerless
+
+: enterforth ( -- )
+ state-valid on
+ my-self to %saved-my-self
+ enterforth-hook
+ handle-breakpoint
+;
+
+: (breakpoint-trap?) exception# 3 = ;
+' (breakpoint-trap?) to breakpoint-trap?
+
+: .go-message ( -- )
+ \ Restarting is only possible if the state that was first saved
+ \ is from a restartable exception.
+ state-valid @ -1 = already-go? and if
+ restartable? on
+ ." Type 'go' to resume" cr
+ then
+;
+
+: .entry ( -- )
+ [ also hidden ]
+ talign \ ... in case dp is misaligned
+
+ aborted? @ if
+ aborted? off hex cr ." Keyboard interrupt" cr .go-message exit
+ then
+ [ previous ]
+;
+' .entry is .exception
+
+\ create debug-break
+[ifdef] debug-break
+: ?report ( char -- )
+ " h# bfd0.0000 v0 set" evaluate
+ " begin v0 h# 3fd v1 lbu v1 h# 20 v1 andi v1 0 <> until nop" evaluate
+ ( char ) " v1 set v1 v0 h# 3f8 sb " evaluate
+ " begin v0 h# 3fd v1 lbu v1 h# 20 v1 andi v1 0 <> until nop" evaluate
+;
+
+: putbyte ( $a0 -- )
+ " $a0 h# f $a0 andi $a0 h# 30 $a0 addi" evaluate
+ " begin v0 h# 3fd v1 lbu v1 h# 20 v1 andi v1 0 <> until nop" evaluate
+ " $a0 v0 h# 3f8 sb " evaluate
+ " begin v0 h# 3fd v1 lbu v1 h# 20 v1 andi v1 0 <> until nop" evaluate
+;
+: dot ( a0 -- )
+ " h# bfd0.0000 v0 set $a0 t2 move" evaluate
+ " t2 d# 28 $a0 srl putbyte" evaluate
+ " t2 d# 24 $a0 srl putbyte" evaluate
+ " t2 d# 20 $a0 srl putbyte" evaluate
+ " t2 d# 16 $a0 srl putbyte" evaluate
+ " t2 d# 12 $a0 srl putbyte" evaluate
+ " t2 d# 8 $a0 srl putbyte" evaluate
+ " t2 d# 4 $a0 srl putbyte" evaluate
+ " t2 0 $a0 srl putbyte" evaluate
+;
+[else]
+: ?report ( char -- ) drop ;
+[then]
+
+0 value (restart-loc
+code (restart ( -- )
+
+ \ Restore the Forth stacks.
+ \ Establish the Data and Return stacks
+ 'user rp0 rp lw
+ 'user sp0 sp lw
+ \ Account for the presence of the top of stack register
+ sp /n sp addiu
+
+ \ Restore the Forth Data and Return stacks from the save area.
+
+ \ Data Stack
+ 'user sp0 t3 lw
+ 'user pssave t0 lw \ Address of data stack save area
+ ps-size t1 set \ Size of data stack area
+ t0 t1 t1 add \ End address of data stack save area
+ begin
+ t1 -4 t1 addiu \ Advance save area pointer
+ t1 t2 get \ Read word from save area
+ t3 -4 t3 addiu \ Advance stack pointer
+ t1 t0 = until
+ t2 t3 put \ Write word to stack
+
+ \ Return Stack
+ 'user rp0 t3 lw
+ 'user rssave t0 lw \ Address of return stack save area
+ rs-size t1 set \ Size of return stack area
+ t0 t1 t1 add \ End address of stack save area
+ begin
+ t1 -4 t1 addiu \ Advance save area pointer
+ t1 t2 get \ Read word from save area
+ t3 -4 t3 addiu \ Advance stack pointer
+ t1 t0 = until
+ t2 t3 put \ Write word to stack
+
+ \ Have to turn off interrupts temporarily until we are done with
+ \ using k0 and k1 because interrupt handling needs them too.
+
+ d# 12 t0 mfc0
+ h# ffff.fffe t1 set
+ t1 t0 t1 and
+ d# 12 t1 mtc0
+ nop nop nop nop
+
+ \ Now it's safe to use k0 and k1
+
+ \ Restore registers
+ here origin- to (restart-loc
+ 1.0001 k1 set \ Will be address of cpu-state (force 2 instructions)
+
+ $0 k1 addr %state-valid cpu-state - sd \ Unlock cpu-state
+
+ k1 addr $lo cpu-state - t0 ld t0 mtlo
+ k1 addr $hi cpu-state - t0 ld t0 mthi
+
+ d# 12 t0 mfc0 \ Get status register
+ t0 d# 28 t0 srl \ Shift coprocessor status bits down
+ t0 h# 02 t0 andi \ Mask bit 1 (coprocessor 1 - Floating point)
+ t0 $0 <> if \ Skip if coprocessor disabled
+ nop
+ k1 addr $fcsr cpu-state - t0 ld d# 31 t0 ctc1
+ then
+
+ d# 26 0 do
+ k1 i 3 + /x* ( offset ) $0 i + ( reg# ) ld
+ loop
+ d# 4 0 do
+ k1 i 3 + d# 28 + /x* ( offset ) $0 i d# 28 + + ( reg# ) ld
+ loop
+
+ k1 addr $sr cpu-state - k0 ld
+ k1 addr $pc cpu-state - k1 ld
+
+[ifdef] debug-break
+bl ?report
+k1 $a0 move dot
+bl ?report
+[then]
+
+ k1 jr
+ d# 12 k0 mtc0 \ Restore Status Register
+ nop
+
+end-code
+' (restart is restart
+' (restart is restart-step
+
+headerless
+0 value save-state-loc
+headers
+
+label reenter ( base -- )
+ascii ~ ?report
+
+ 'body main-task up li \ User pointer address
+ base up up addu
+ up 0 up lw
+
+ \ Establish the Data and Return stacks
+ \ Copy the entire Forth Data and Return stacks areas to a save area.
+ \ Data Stack
+ 'user sp0 sp lw
+ sp t3 move
+ 'user pssave t0 lw \ Address of data stack save area
+ ps-size t1 set \ Size of data stack area
+ t0 t1 t1 add \ End address of data stack save area
+ begin
+ t3 -4 t3 addiu \ Advance data stack pointer
+ t1 -4 t1 addiu \ Advance save area pointer
+ t3 t2 get \ Read word from stack
+ t1 t0 = until
+ t2 t1 put \ Write word to save area
+
+ \ Account for the presence of the top of stack register
+ sp /n sp addiu
+
+ \ Return Stack
+ 'user rp0 rp lw
+
+ rp t3 move
+ 'user rssave t0 lw \ Address of return stack save area
+ rs-size t1 set \ Size of return stack area
+ t0 t1 t1 add \ End address of data stack save area
+ begin
+ t3 -4 t3 addiu \ Advance data stack pointer
+ t1 -4 t1 addiu \ Advance save area pointer
+ t3 t2 get \ Read word from stack
+ t1 t0 = until
+ t2 t1 put \ Write word to save area
+
+ascii ! ?report
+
+ \ Reenter forth
+ np@ origin- np set
+ np base np addu
+
+[ifdef] debug-break
+carret ?report
+linefeed ?report
+sp $a0 move dot bl ?report
+rp $a0 move dot bl ?report
+up $a0 move dot bl ?report
+base $a0 move dot bl ?report
+np $a0 move dot bl ?report
+[then]
+
+ 'body enterforth ip set
+ ip base ip addu
+
+[ifdef] debug-break
+ip $a0 move dot
+[then]
+c;
+
+\ exception# = -1 if entered from interrupt-return
+\ 3 if breakpoint exception
+label save-state ( k0: exception# -- )
+ here origin- to save-state-loc
+ 1.0001 k1 set \ Will be address of cpu-state (force 2 instructions)
+ k0 k1 addr exception# cpu-state - sd \ Save exception#
+
+ k1 addr %state-valid cpu-state - k0 ld
+ k0 0 = if \ Save only if we don't already have valid state
+ nop
+
+ \ Save general registers
+ d# 32 0 do
+ $0 i + ( reg# ) k1 i 3 + /x* ( offset ) sd
+ loop
+
+ascii X ?report
+
+ d# 12 k0 mfc0 \ Get status register
+ k0 d# 28 k0 srl \ Shift coprocessor status bits down
+ k0 h# 02 k0 andi \ Mask bit 1 (coprocessor 1 - Floating point)
+ k0 $0 <> if \ Skip if coprocessor disabled
+ nop
+ \ Save floating point registers
+ d# 32 0 do
+ i ( freg# ) k0 mfc1
+ k0 k1 i d# 36 + /x* ( offset ) sd
+ loop
+
+ d# 31 t0 cfc1 nop t0 k1 addr $fcsr cpu-state - sd
+ then
+
+ \ Save special registers
+ t0 mflo nop t0 k1 addr $lo cpu-state - sd
+ t0 mfhi nop t0 k1 addr $hi cpu-state - sd
+
+ \ Save CP0 registers
+ d# 13 t0 mfc0 t0 k1 addr $cause cpu-state - sd
+ d# 8 t0 mfc0 t0 k1 addr $badvaddr cpu-state - sd
+ d# 26 t0 mfc0 t0 k1 addr $badpaddr cpu-state - sd
+ d# 14 t0 mfc0 t0 k1 addr $pc cpu-state - sd
+
+ \ Clear the EXL bit in the status register because we're going
+ \ back to exception level 0.
+ d# 12 t0 mfc0 $0 2 t1 addiu $0 t1 t1 nor t0 t1 t0 and
+ t0 k1 addr $sr cpu-state - sd
+ then
+
+ascii Y ?report
+
+ \ Find the base address
+ here 8 + bal \ ra = Absolute address of next instruction
+ here origin - 4 + base set \ base = relative address of this instruction
+ ra base base subu \ Base address of Forth kernel
+
+[ifdef] debug-break
+bl ?report
+base $a0 move dot
+bl ?report
+[then]
+
+ 'body reenter t0 set
+ t0 base t0 addu
+ d# 14 t0 mtc0 \ Set EPC
+ nop nop nop nop \ Delay before eret
+
+[ifdef] debug-break
+t0 $a0 move dot
+bl ?report
+d# 14 $a0 mfc0 dot
+[then]
+
+ eret
+ nop
+
+end-code
+
+hidden also
+stand-init: Fixup save-state; Allocate save stacks
+ uasave drop
+ ps-size alloc-mem to pssave
+ rs-size alloc-mem to rssave
+ cpu-state save-state-loc origin+ fix-set32
+ cpu-state (restart-loc origin+ fix-set32
+
+ restartable? off
+;
+only forth also definitions
+
+
+
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/ccalls.fth
===================================================================
--- cpu/mips/ccalls.fth (rev 0)
+++ cpu/mips/ccalls.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,198 @@
+purpose: C subroutine and Unix system call interfaces for MIPS
+\ See license at end of file
+
+\ Defining words to construct Forth interfaces to C subroutines
+\ and Unix system calls. This is strongly implementation dependent, and will
+\ require EXTENSIVE modifications for other Forth systems, other CPU's,
+\ and other operating systems.
+\
+\ Defines:
+\
+\ syscall: ( syscall# -- ) ( Input Stream: name arg-spec )
+\ subroutine: ( adr -- ) ( Input Stream: name arg-spec )
+\
+\ This version is for MIPS Unix systems where ints, longs, and addresses
+\ are all the same size. Under this assumption, the only thing we have to
+\ do to the stack arguments is to convert Forth strings to C strings.
+
+decimal
+only forth assembler also forth also hidden also definitions
+
+variable #args variable #results variable arg#
+
+: system-call ( syscall# -- )
+ asm(
+ ( call# ) v0 li
+ syscall
+ $a3 $0 <> if
+ $0 up ['] errno >user# sw \ Delay slot
+ v0 up ['] errno >user# sw
+ -1 v0 li
+ then
+ )asm
+;
+: subroutine-call ( subroutine-adr -- )
+ asm( jal nop )asm
+;
+: wrapper-call ( call# -- )
+ asm(
+ 'user syscall-vec t0 lw \ Get address of system call table
+ bubble
+ ( call# ) t0 swap t0 lw \ Address of routine
+ bubble
+ t0 ra jalr nop
+ )asm
+;
+
+: sys: \ name ( call# -- )
+ code
+;
+: $a# ( -- reg ) arg# @ asm( $a0 )asm + ;
+: ?dec ( -- )
+ arg# @ 4 = if asm( sp adec )asm then
+;
+: arg ( -- )
+ arg# @ if
+ ?dec
+ \ If the argument number is 4 or greater, we leave it on the stack
+ arg# @ 4 < if
+ asm( sp arg# @ 1- /l* $a# lw )asm
+ then
+ else
+ asm( tos $a0 move )asm
+ then
+ 1 arg# +!
+;
+: str ( -- )
+ arg# @ if
+ ?dec
+ arg# @ 4 < if
+ asm(
+ sp arg# @ 1- /l* $a# lw
+ bubble
+ $a# 1 $a# addiu
+ )asm
+ else
+ asm(
+ sp arg# @ 1- /l* $at lw
+ bubble
+ $at 1 $at addiu
+ $at sp arg# @ 1- /l* sw
+ )asm
+ then
+ else
+ asm( tos 1 $a0 addiu )asm
+ then
+ 1 arg# +!
+;
+: res ( -- ) 1 #results +! ;
+: } ( -- )
+ #results @ if
+ #args @ 0= if
+ asm(
+ tos sp push
+ )asm
+ then
+
+ #args @ 3 > if
+ asm(
+ sp #args @ /l* sp addiu
+ )asm
+ else #args @ 1 > if
+ asm(
+ sp #args @ 1- /l* sp addiu
+ )asm
+ then then
+
+ asm( v0 tos move )asm
+ else \ No results
+ #args @ 3 > if
+ asm(
+ sp #args @ /l* tos lw
+ sp #args @ 1+ /l* sp addiu
+ )asm
+ else #args @ if
+ asm(
+ sp #args @ 1- /l* tos lw
+ sp #args @ /l* sp addiu
+ )asm
+ then then
+ then
+;
+: scan-args ( -- )
+ #args off
+ 0 ( marker )
+ begin
+ bl word 1+ c@
+ case
+ ascii l of ['] arg true endof
+ ascii i of ['] arg true endof
+ ascii a of ['] arg true endof
+ ascii s of ['] str true endof
+ ascii - of false endof
+ ascii } of ." Where's the -- ?" abort endof
+ ( default ) ." Bad type specifier: " dup emit abort
+ endcase
+ while
+ 1 #args +!
+ repeat
+ arg# off
+ begin ?dup while execute repeat
+;
+: do-call ( ??? 'call-assembler -- ) \ ??? is args specific to the call type
+ execute
+;
+: scan-results ( -- )
+ #results off
+ begin
+ bl word 1+ c@
+ case
+ ascii l of true endof
+ ascii i of true endof
+ ascii a of true endof
+ ascii s of ." Can't return strings yet" abort true endof
+ ascii } of false endof
+ ( default ) ." Bad type specifier: " dup emit
+ endcase
+ while
+ 1 #results +!
+ repeat
+ }
+;
+only forth hidden also forth assembler also forth definitions
+: { \ args -- results } ( -- )
+ scan-args do-call scan-results next
+;
+: syscall: \ name ( syscall# -- syscall# 'system-call )
+ ['] system-call
+ code current @ context ! \ don't want to be in assembler voc
+;
+: subroutine: \ name ( adr -- adr 'subroutine-call )
+ ['] subroutine-call code current @ context !
+;
+
+only forth also definitions
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/centry.fth
===================================================================
--- cpu/mips/centry.fth (rev 0)
+++ cpu/mips/centry.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,123 @@
+purpose: Client interface handler code
+\ See license at end of file
+
+d# 12 /n* buffer: cif-reg-save
+
+\ Patch the following constants as needed in architecture-dependent code
+ 0 constant sr-or-mask \ For turning on Status Register bits
+-1 constant sr-and-mask \ For turning off Status Register bits
+
+headerless
+code cif-return
+ tos v0 move \ Return value
+ 'user cif-reg-save $at lw \ Address of register save area in $at
+ $at 0 /n* s0 lw
+ $at 1 /n* s1 lw
+ $at 2 /n* s2 lw
+ $at 3 /n* s3 lw
+ $at 4 /n* s4 lw
+ $at 5 /n* s5 lw
+ $at 6 /n* s6 lw
+ $at 7 /n* s7 lw
+ $at 8 /n* s8 lw
+ $at 9 /n* ra lw
+ $at d# 11 /n* t0 lw d# 12 t0 mtc0 \ Status register
+
+ ra $0 jalr
+ $at d# 10 /n* sp lw
+end-code
+
+: cif-exec ( args ... -- )
+ sr@ sr-and-mask and sr-or-mask or sr!
+ do-cif
+ cif-return
+;
+
+headers
+: cif-caller ( -- adr ) cif-reg-save 9 na+ @ ;
+
+headerless
+label cif-handler
+ \ Registers:
+ \ a0 argument array pointer
+ \ s0-s8,sp,ra must be preserved
+ \ k0,k1 Don't touch
+ \ others scratch
+
+
+ ra $a3 move \ Save ra
+ here 8 + bal \ ra = Absolute address of next instruction
+ here origin - 4 + $a2 set \ a2 = relative address of this instruction
+ ra $a2 $a2 subu \ a2 = address of Forth kernel
+ $a3 ra move \ Restore ra
+
+
+ 'body main-task $a1 li \ a1: main-task-pfa (relative)
+ $a1 $a2 $a1 addu \ a1: main-task-pfa (absolute)
+
+ $a1 0 $a1 lw \ a1: user area
+ $a1 'user# cif-reg-save $at lw \ at: register save area address
+ s0 $at 0 /n* sw \ Save registers
+ s1 $at 1 /n* sw
+ s2 $at 2 /n* sw
+ s3 $at 3 /n* sw
+ s4 $at 4 /n* sw
+ s5 $at 5 /n* sw
+ s6 $at 6 /n* sw
+ s7 $at 7 /n* sw
+ s8 $at 8 /n* sw
+ ra $at 9 /n* sw
+ sp $at d# 10 /n* sw
+ d# 12 t0 mfc0 t0 $at d# 11 /n* sw \ Status register
+
+ $a2 base move
+ $a1 up move \ Set user pointer
+ $a0 tos move \ Set top of stack register to arg
+
+ 'user rp0 rp lw \ Set return stack pointer
+ 'user sp0 sp lw \ Set data stack pointer
+ \ Don't adjust the stack pointer to account for the top of stack register,
+ \ because the stack (actually the TOS register) contains one entry, the
+ \ cif-struct pointer.
+
+ np@ origin- np set \ Set the NEXT pointer
+ np base np addu
+
+ 'body cif-exec ip li \ Set interpreter pointer
+ ip base ip addu \ Relocate it to an absolute address
+c;
+
+0 value callback-stack
+
+headers
+: callback-call ( args vector -- ) callback-stack sp-call 2drop ;
+
+\ Force allocation of buffer
+stand-init: CIF buffers
+ cif-reg-save drop
+ h# 1000 dup alloc-mem + to callback-stack
+;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cobalt/devalias.fth
===================================================================
--- cpu/mips/cobalt/devalias.fth (rev 0)
+++ cpu/mips/cobalt/devalias.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,9 @@
+devalias com1 /serial:115200
+
+devalias net /ethernet
+
+devalias rom /dropins
+
+devalias scsi /scsi
+devalias disk /ide@0/disk@0
+
Added: cpu/mips/cobalt/devices.fth
===================================================================
--- cpu/mips/cobalt/devices.fth (rev 0)
+++ cpu/mips/cobalt/devices.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,88 @@
+purpose: Load file for I/O devices
+\ See license at end of file
+
+fload ${BP}/dev/flashpkg.fth
+
+0 0 " 1c80.03f8" " /" begin-package \ UART 0
+ alias enable-interrupt drop
+ alias disable-interrupt drop
+ alias interrupt-handler@ 0
+ alias interrupt-handler! drop
+ fload ${BP}/dev/ns16550a.fth
+ d# 18432000 to clock-frequency \ 10 times the normal PC clock frequency!
+ d# 115200 to default-baudrate
+end-package
+
+
+0 0 " " " /" begin-package \ Access to FLASH
+ " dropins" device-name
+
+ create eprom-va " dropins.img" $file,
+ here eprom-va - constant /device
+ /device constant /device-phys
+
+ " rom" encode-string
+ " compatible" property
+
+ fload ${BP}/cpu/mips/cobalt/flashpkg.fth
+end-package
+
+\ The first sector in the ROM is a FLASH burner program
+\ Define these words outside of the PCI bus node for convenience in debugging
+h# b400.0000 constant io-base
+: pl! ( l offset -- ) io-base + rl! ;
+fload ${BP}/dev/pci/configm1.fth
+
+0 0 " " " /" begin-package
+ \ Redefine these words inside the PCI bus node so they can be accessed
+ \ as device methods
+ alias config-l@ config-l@ alias config-l! config-l!
+ alias config-w@ config-w@ alias config-w! config-w!
+ alias config-b@ config-b@ alias config-b! config-b!
+
+ fload ${BP}/cpu/mips/cobalt/mappci.fth \ Map PCI to root
+ fload ${BP}/dev/pcibus.fth \ Generic PCI bus package
+
+ fload ${BP}/cpu/mips/cobalt/pciinit.fth
+
+end-package
+stand-init: PCI host bridge
+ " /pci" " init" execute-device-method drop
+;
+
+fload ${BP}/dev/pciprobe.fth \ PCI probing
+fload ${BP}/dev/scsi/probscsi.fth \ SCSI probing
+
+0 0 " " " /" begin-package
+ " clock" device-name
+ : open true ;
+ : close ;
+ : get-time ( -- s m h d m y ) 0 0 d# 12 d# 27 d# 11 d# 2001 ;
+end-package
+stand-init: Clock node
+ " /clock" open-dev clock-node !
+;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cobalt/diaguart.fth
===================================================================
--- cpu/mips/cobalt/diaguart.fth (rev 0)
+++ cpu/mips/cobalt/diaguart.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,57 @@
+purpose: Driver for the 16550-style UART on the Cobalt Raq2
+\ See license at end of file
+
+hex
+
+h# 1c8003f8 kseg1 + constant uart
+
+: uart! ( val reg# -- ) uart + rb! ;
+: uart@ ( reg# -- val ) uart + rb@ ;
+
+: line-stat@ ( -- n ) 5 uart@ ;
+
+\ Test for rcv character.
+: ukey? ( -- flag ) line-stat@ 1 and 0<> ;
+: uemit? ( -- flag ) line-stat@ h# 20 and 0<> ; \ Test for xmit ready
+
+: ukey ( -- char ) begin ukey? until 0 uart@ ; \ Receive a character
+: uemit ( char -- ) begin uemit? until 0 uart! ; \ Transmit a character
+
+: ubreak? ( -- false ) ;
+: clear-break ( -- ) ; \ Clear break indication
+
+: inituarts ( -- )
+[ifdef] notdef
+ 3 3 uart! \ 8 bits, no parity
+ 7 2 uart! \ Clear and enable FIFOs
+\ d# 9600 baud
+\ d# 19200 baud
+\ d# 38400 baud
+ d# 115200 baud
+[then]
+;
+
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cobalt/dropins.bth
===================================================================
--- cpu/mips/cobalt/dropins.bth (rev 0)
+++ cpu/mips/cobalt/dropins.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,45 @@
+purpose: Top-level build script for ROM
+\ See license at end of file
+
+command: &native &this
+in: inflate.img
+in: ${BP}/dev/ide/build/piolhier.fc
+in: ${BP}/dev/dec21140/build/dec21143.fc
+build-now
+
+\needs $add-dropin fload ${BP}/tools/mkdropin.fth
+
+\ Always re-create the builton.fth file when we make a new rom.img
+fload ${BP}/cpu/mips/builton.bth
+
+writing dropins.img
+ " builton.fth" " probe-" $add-dropin
+ " inflate.img" " inflate" $add-dropin
+ " ${BP}/dev/dec21140/build/dec21143.fc" " pci1011,19" $add-dropin
+ " ${BP}/dev/ide/build/piolhier.fc" " class01018a" $add-dropin
+ " ${BP}/ofw/inet/telnetd.fth" " telnetd" $add-dropin
+ofd @ fclose
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cobalt/fixexc.fth
===================================================================
--- cpu/mips/cobalt/fixexc.fth (rev 0)
+++ cpu/mips/cobalt/fixexc.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,98 @@
+purpose: Personalize the exception handler for this environment
+\ See license at end of file
+
+stand-init:
+ kseg0 to vector-base
+;
+
+\ Disable exponential backoff for DHCP. We are running on point-to-point
+\ links, so there is no need to avoid flooding the net.
+dev /obp-tftp
+decimal patch 1000 8000 init-backoff hex \ Initially 1 second instead of 8
+decimal patch 1 5000 ?try-broadcast hex \ Waiting stops REL "Hello" packets
+-1 to tftp-retries \ Close enough to forever
+patch noop 2* next-backoff \ Don't double the interval
+dend
+
+0 value trapped?
+
+\ Set aborted? so save-state will be called, instead of re-executing the
+\ instruction. Set trapped? so "Keyboard interrupt" won't be displayed.
+: (.exception1) ( exc-code -- )
+ (.exception) 1 aborted? ! true to trapped?
+;
+
+\ Suppress the display of "Keyboard interrupt" if trapped? is set
+: .entry1 ( -- ) trapped? if false to trapped? else .entry then ;
+
+: bpon bpon state-valid off ;
+
+: (init-dispatcher) ( -- )
+ ['] getmsecs is get-msecs
+ sr@ h# 200.00000 or sr! \ Enable CP1
+;
+' (init-dispatcher) to init-dispatcher
+\ base @
+\ decimal patch cpu-clock-frequency 33333333 calibrate-ticker
+\ base !
+
+' (.exception1) to dispatch-exceptions
+' .entry1 to .exception
+' ge-preamble to tlb-handler
+' ge-preamble to xtlb-handler
+' ge-preamble to cache-handler
+
+defer user-interface ' quit to user-interface
+also client-services definitions
+: exit ( -- )
+ \ Reinstate our exception handlers
+ h# 2000.8080 sr! \ CP1 on, enable tick interrupt, enable XKseg
+ disable-interrupts
+ catch-exceptions
+ ms/tick set-tick-limit
+
+ [ also hidden ] breakpoints-installed off [ previous ]
+ [ifdef] vector vector off [then]
+
+ " restore" stdout @ ['] $call-method catch if 3drop then
+ " restore" stdin @ ['] $call-method catch if 3drop then
+ enable-interrupts
+
+ user-interface
+;
+: enter ( -- )
+ sr@ >r disable-interrupts
+ ." Type 'resume' to return to the operating system." cr
+ interact
+ r> sr!
+;
+previous definitions
+
+: (lock[) ( -- r: inten ) r> sr@ >r >r disable-interrupts ;
+: (]unlock) ( r: inten -- ) r> r> sr! >r ;
+' (lock[) to lock[
+' (]unlock) to ]unlock
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cobalt/flashpkg.fth
===================================================================
--- cpu/mips/cobalt/flashpkg.fth (rev 0)
+++ cpu/mips/cobalt/flashpkg.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,152 @@
+purpose: Package for FLASH ROM device
+\ See license at end of file
+
+headerless
+0 instance value base-adr
+0 instance value image-size
+0 value device-base
+0 value open-count
+false value written?
+0 instance value seek-ptr
+
+: clip-size ( adr len -- len' adr len' )
+ seek-ptr + image-size min seek-ptr - ( adr len' )
+ tuck
+;
+: update-ptr ( len' -- len' ) dup seek-ptr + to seek-ptr ;
+: 'base-adr ( -- adr )
+ seek-ptr
+[ifdef] select-flash
+ /device-phys /mod select-flash
+[then]
+ base-adr +
+;
+
+headers
+external
+: seek ( d.offset -- status )
+ 0<> over image-size u> or if drop true exit then \ Seek offset too big
+ to seek-ptr
+ false
+;
+
+: open ( -- flag )
+ \ This lets us open the node during compilation
+ standalone? 0= if true exit then
+ open-count dup 1+ to open-count 0= if ( )
+[ifdef] eprom-va
+ eprom-va
+[else]
+ my-address my-space /device-phys " map-in" $call-parent
+[then]
+ to device-base
+ then ( )
+ 0 to seek-ptr ( )
+ my-args dup if ( adr len )
+ 2dup " \" $= 0= if ( adr len )
+ over c@ [char] \ = if 1 /string then ( adr' len' )
+ find-drop-in dup if ( di-adr di-len true )
+ -rot to image-size to base-adr ( true )
+ then ( flag )
+ exit ( flag )
+ then ( adr len )
+ then ( adr len )
+ 2drop ( )
+ /device to image-size ( )
+ device-base to base-adr ( )
+ true ( true )
+;
+: close ( -- )
+ \ This lets us open the node during compilation
+ standalone? 0= if exit then
+
+ base-adr device-base <> if base-adr image-size release-dropin then
+ open-count dup 1- 0 max to open-count ( old-count )
+[ifdef] eprom-va
+ drop
+[else]
+ 1 = if device-base /device-phys " map-out" $call-parent then
+[then]
+;
+: size ( -- d.size )
+ base-adr device-base <> if image-size else /device then 0
+;
+: read ( adr len -- actual )
+ clip-size tuck ( len' len' adr len' )
+ begin
+ /device-phys seek-ptr /device-phys mod - min ( len' len' adr len'' )
+ 2dup 'base-adr -rot move ( len' len' adr len'' )
+ update-ptr ( len' len' adr len'' )
+ rot over - -rot + over ( len' len'-len'' adr+len'' len'-len'' )
+ ?dup 0= until ( len' len'-len'' adr+len'' len'-len'' )
+ 2drop
+;
+: load ( adr -- len )
+ 0 0 seek drop ( adr )
+ image-size read ( len )
+;
+: next-file-info ( id -- false | id' s m h d m y len attributes name$ true )
+ ?dup 0= if open-drop-in then ( id )
+ another-dropin? if ( id )
+ " built-time-int" $find if ( id s m h xt )
+ execute ( id s m h packed-date )
+ d# 100 /mod d# 100 /mod ( id s m h d m y )
+ else ( id s m h adr len )
+ 2drop 0 0 0 ( id s m h d m y )
+ then ( id s m h d m y )
+ " built-date-int" $find if ( id s m h xt )
+ execute ( id s m h packed-date )
+ d# 100 /mod d# 100 /mod ( id s m h d m y )
+ else ( id s m h adr len )
+ 2drop 0 0 0 ( id s m h d m y )
+ then ( id s m h d m y )
+ di-expansion be-l@ ( id s m h d m y size )
+ ?dup 0= if di-size be-l@ then ( id s m h d m y size )
+ o# 100444 ( id s m h d m y size attributes )
+ di-name$ ( id s m h d m y size attr name$ )
+ true ( id s m h d m y size attr name$ true )
+ else ( )
+ close-drop-in false ( false )
+ then
+;
+
+: free-bytes ( -- d.#bytes )
+ open-drop-in 0 ( high-water )
+ 0 begin another-dropin? while ( high-water id )
+ nip di-size be-l@ 4 round-up ( id size )
+ over + swap ( high-water' id )
+ repeat ( high-water )
+ size rot 0 d- ( d.#bytes )
+;
+
+\ These allow us to sub-address the FLASH device to access the PROMICE AI port
+1 " #address-cells" integer-property
+
+: decode-unit ( adr len -- phys ) push-hex $number if 0 then pop-base ;
+: encode-unit ( phys -- adr len ) push-hex (u.) pop-base ;
+: map-in ( offset size -- virt ) drop device-base + ;
+: map-out ( virt size -- virt ) 2drop ;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cobalt/fw.bth
===================================================================
--- cpu/mips/cobalt/fw.bth (rev 0)
+++ cpu/mips/cobalt/fw.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,253 @@
+purpose: Load file for Open Firware on Cobalt Raq2
+\ See license at end of file
+
+dictionary: ${BP}/cpu/mips/build/basefw.dic
+in: dropins.img
+command: &mipsfth &dictionary &this
+build-now
+
+\ create rom-based?
+h# 81f0.0000 constant rom-base
+create ram-image
+
+\ ' $report-name is include-hook
+\ true to stand-init-debug?
+false to stand-init-debug?
+
+true ' auto-boot? set-config-int-default
+true ' fcode-debug? set-config-int-default
+true ' local-mac-address? set-config-int-default
+
+" com1" ' output-device set-config-string-default
+" com1" ' input-device set-config-string-default
+" dhcp" ' ip-address set-config-string-default
+" net" ' boot-device set-config-string-default
+
+fload ${BP}/cpu/mips/ksegaddr.fth
+fload ${BP}/cpu/mips/physaddr.fth
+fload ${BP}/cpu/mips/virtaddr.fth
+
+: cpu-clock-frequency ( -- hz ) d# 200,000,000 ;
+fload ${BP}/cpu/mips/cobalt/regacc.fth
+
+0 value last-count
+0 value ticker
+: hw-get-ms ( -- n )
+ count@ d# 400,000 u/mod nip ( msecs )
+ dup last-count <> if ( msecs )
+ to last-count
+ ticker 1+ to ticker
+ else
+ drop
+ then
+ ticker
+;
+' hw-get-ms is get-msecs
+
+fload ${BP}/cpu/mips/cobalt/diaguart.fth \ Diagnostic driver for serial port
+fload ${BP}/forth/lib/sysuart.fth \ Plug UART routines into key and emit
+\ ' ukey is diag-key \ Feed UART input to "dl"
+
+h# 1000 to pagesize
+d# 12 to pageshift
+
+fload ${BP}/cpu/mips/cache.fth \ Cache synchronization/flushing
+
+[ifdef] 2-cell-rootnode
+: pcicache-wbinv ( devadr len -- ) 3drop ;
+: pcicache-inv ( devadr len -- ) 3drop ;
+[else]
+: pcicache-wbinv ( devadr len -- ) 2drop ;
+: pcicache-inv ( devadr len -- ) 2drop ;
+[then]
+
+fload ${BP}/cpu/mips/rootnode.fth \ Root node mapping
+
+dev /
+extend-package
+ " /tftpboot/Cobalt-MIPS" encode-string " architecture" property
+ " Cobalt,Raq2" encode-string " model" property
+\ d# 33,333,333 " clock-frequency" integer-property
+finish-device
+device-end
+
+: (cpu-arch ( -- adr len )
+ " architecture" ['] root-node get-package-property drop
+ get-encoded-string
+;
+' (cpu-arch to cpu-arch
+
+h# 1.0000 constant initial-heap-size
+fload ${BP}/cpu/mips/boot.fth \ Low-level startup code
+
+\ Memory management services
+[ifdef] virtual-mode
+fload ${BP}/ofw/core/clntmem1.fth \ client services for memory
+[else]
+fload ${BP}/ofw/core/clntphy1.fth \ client services for memory
+[then]
+fload ${BP}/ofw/core/memlist.fth \ Resource list common routines
+fload ${BP}/ofw/core/showlist.fth \ Linked list display tool
+fload ${BP}/ofw/core/allocph1.fth \ S Physical memory allocator
+fload ${BP}/ofw/core/availpm.fth \ Available memory list
+fload ${BP}/ofw/core/allocmor.fth \ S Allow alloc-mem to use more memory
+
+: (initial-heap) ( -- adr len ) sp0 @ ps-size - limit tuck - ;
+\ : (initial-heap) ( -- adr len )
+\ h# 80000000 h# 20000
+\ \ sp0 @ ps-size - initial-heap-size - initial-heap-size
+\ ;
+['] (initial-heap) to initial-heap
+
+\ fload ${BP}/forth/lib/dumballo.fth \ Rudimentary memory allocator
+
+h# 1000.0000 constant /segment
+
+alias memsize-loc kseg0
+fload ${BP}/cpu/mips/cobalt/probemem.fth \ Memory probing
+stand-init: Probing memory
+ " probe" memory-node @ $call-method
+;
+
+\ File system
+[ifdef] resident-packages
+support-package: disk-label
+ fload ${BP}/ofw/disklabl/loadpkg.fth \ Disk label package
+end-support-package
+
+support-package: ext2-file-system
+ fload ${BP}/ofw/fs/ext2fs/ext2fs.fth \ Linux file system
+end-support-package
+
+support-package: dropin-file-system
+ fload ${BP}/ofw/fs/dropinfs.fth \ Dropin file system
+end-support-package
+
+support-package: nfs
+ fload ${BP}/ofw/fs/nfs/loadpkg.fth
+end-support-package
+[then]
+fload ${BP}/ofw/fs/fatfs/fdisk2.fth \ Partition map administration
+
+\ Load file format handlers
+
+: call32 ; defer .subname
+fload ${BP}/ofw/core/allocsym.fth \ Allocate memory for symbol table
+fload ${BP}/ofw/core/symcif.fth
+fload ${BP}/ofw/core/symdebug.fth
+: release-load-area ( boundary-adr -- ) drop ;
+fload ${BP}/ofw/elf/elf.fth
+fload ${BP}/ofw/elf/elfdebug.fth
+' 2drop is elf-map-in
+true ' client-symbols? set-config-int-default
+
+\ Device Tree
+fload ${BP}/cpu/mips/cobalt/devices.fth
+fload ${BP}/cpu/mips/cobalt/devalias.fth
+
+\ Turn on RTS and DTR for the benefit of systems that are configured
+\ for hardware handshaking
+dev com1
+: ron inituart rts-dtr-on ;
+patch ron inituart open
+dend
+
+
+: stand-init-io ( -- )
+[ifdef] stand-init-io
+ stand-init-io
+[then]
+\ install-dumb-alloc
+ inituarts
+ install-uart-io
+ calibrate-ticker
+\ ." Open Firmware starting..." cr cr
+
+ ['] reset-all to bye
+;
+
+: com1 ( -- adr len ) " com1" ;
+' com1 to fallback-device
+
+: probe-all ( -- )
+ " probe-" do-drop-in
+[ifdef] probe-pci
+ probe-pci
+[then]
+ " probe+" do-drop-in
+;
+
+\ Perform a full system reset
+: (reset-all) ( -- ) h# f h# bc00.0000 rb! ;
+' (reset-all) to reset-all
+
+fload ${BP}/cpu/mips/argv.fth
+fload ${BP}/cpu/mips/cobalt/fixexc.fth
+
+: copy-reboot-info ;
+\ fload ${BP}/cpu/mips/bcm12500/reboot.fth
+
+fload ${BP}/ofw/core/startup.fth
+: .fw ." Open Firmware by FirmWorks " .built cr ;
+' .fw to .firmware
+
+fload ${BP}/ofw/core/countdwn.fth \ Auto-boot countdown
+patch 1 6 get-countdown
+
+: linux-setup ( -- )
+ $sr 1 invert and to $sr \ Disable interrupts
+ kseg0 0 sync-cache
+ boot-file boot-device argv,argc to $a0 to $a1
+ null$ " FIRMWARE=OpenFirmware" argv,argc drop to $a2
+ memory-size 1meg * to $a0
+;
+
+: init-program ( -- )
+ \ Turn off interrupts because some of the Linux kernel ELF files
+ \ overwrite the trap vectors.
+ init-program disable-interrupts linux-setup
+
+ \ Kludge alert! Linux expects the PCI Base Address Registers for the
+ \ Ethernet and IDE to be assigned the way the Cobalt firmware does it,
+ \ even though that is inconsistent between the two. So we slam them
+ \ to the expected values before jumping to Linux.
+ h# 280.0045 h# 3804 config-l! \ Ethernet command register
+ h# .4000 h# 380c config-l! \ Ethernet something
+ h# 1010.0000 h# 3810 config-l! \ Ethernet I/O space BAR
+ h# 1200.0000 h# 3814 config-l! \ Ethernet Memory space BAR
+ h# 2814.0104 h# 383c config-l! \ Ethernet someting
+ h# cc00 h# 4920 config-l! \ bmIDE BAR
+;
+
+\ Don't override user-supplied file names
+dev /obp-tftp ' dhcp-modify-file to modify-boot-file dend
+
+patch true diagnostic-mode? diag-type
+patch true diagnostic-mode? diag-cr
+
+install-rom-cold
+.( --- Saving fw.dic ...) " fw.dic" $save-forth cr
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cobalt/mappci.fth
===================================================================
--- cpu/mips/cobalt/mappci.fth (rev 0)
+++ cpu/mips/cobalt/mappci.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,63 @@
+purpose: PCI physical address mapping to root node for BCM1250
+\ See license at end of file
+
+headerless
+
+\ map-pci-phys creates a virtual mapping for the PCI physical address range
+\ "paddr io? size", returning its virtual address "vaddr". It does so by
+\ first translating the PCI physical base address "paddr io?" to the
+\ corresponding physical address in the parent node's address space (which
+\ in this case is the primary system bus address space), and then calling
+\ the parent's "map-in" method.
+
+\ PCI I/O space is mapped to 1000.0000..1200.0000 in the CPU's physical
+\ address space
+\ PCI memory space is mapped 1-1 within the range 1800.0000 - 1c00.0000
+: map-pci-phys ( paddr io? phys.hi size -- vaddr )
+ \ In the next line, we can't use "+" instead of "or" because
+ \ the Cobalt firmware is inconsistent about the way it stores
+ \ assigned I/O space addresses in PCI base address registers.
+ \ Sometimes it leaves off the upper 0x1000.0000 bit, and sometimes
+ \ it doesn't.
+ nip swap if swap h# 1000.0000 or swap then ( paddr' size )
+ " map-in" $call-parent ( mem-vaddr )
+;
+
+\ >pci-devaddr translates the DMA address "parent-devaddr", which is in the
+\ parent node's physical address space, to the corresponding DMA address
+\ "pci-devaddr" in the PCI physical address space (in PCI memory space; DMA
+\ to PCI I/O space is not possible).
+
+: >pci-devaddr ( parent-devaddr -- pci-devaddr ) h# 0 + ;
+
+\ pci-devaddr> translates the DMA address "pci-devaddr", which is in the
+\ PCI physical address space (in PCI memory space; DMA to PCI I/O space is
+\ not possible), to the corresponding DMA address "parent-devaddr" in the
+\ parent node's physical address space.
+
+: pci-devaddr> ( pci-devaddr -- parent-devaddr ) h# 0 - ;
+headers
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cobalt/pciinit.fth
===================================================================
--- cpu/mips/cobalt/pciinit.fth (rev 0)
+++ cpu/mips/cobalt/pciinit.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,69 @@
+purpose: PCI Bus bridge hardware initialization
+\ See license at end of file
+
+also forth definitions
+
+\ This prevents crashes resulting from an attempt to access the
+\ (nonexistent) expansion ROM using ordinary memory access operators.
+\ That doesn't work because we don't properly map PCI devices into
+\ virtual address space. Omitting the find-fcode? function doesn't
+\ hurt us because we have no plugin slots so there's no chance of
+\ probing anything with an expansion ROM.
+patch false find-fcode? populate-device-node
+
+previous definitions
+
+\ Configure the PCI bridge
+: init ( -- )
+;
+
+: pci-probe-list ( -- adr len ) " 7,9" ;
+
+\ AgileTV boards have no plug-in PCI slots
+h# 0000 encode-int " slave-only" property
+h# 0000 encode-int \ Mask of implemented add-in slots
+" slot-names" property
+
+\ XXX this needs work...
+
+\ Determine the parent interrupt information (the "interrupt line" in PCI
+\ parlance) from the child's "interrupt pin" and the child's address,
+\ returning "int-line true" if the child's interrupt line register should
+\ be set or "false" otherwise.
+: assign-int-line ( phys.hi.func INTx -- irq true )
+ 2drop 0 true
+;
+
+\ h# 1200.0000 to first-mem \ This is where Linux starts putting stuff
+\ h# 2000.0000 to mem-space-top
+
+h# 1200.0000 to first-mem
+h# 1400.0000 to mem-space-top
+
+h# 1010.0000 to first-io
+h# 200.0000 to io-space-top
+
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cobalt/probemem.fth
===================================================================
--- cpu/mips/cobalt/probemem.fth (rev 0)
+++ cpu/mips/cobalt/probemem.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,86 @@
+purpose: Memory probing
+\ See license at end of file
+
+\ The memory regions are 0xxx.xxxx, 8xxx.xxxx, 9xxx.xxxx, and cxxx.xxxx
+: (memory?) ( adr -- flag ) d# 28 rshift 0= ;
+' (memory?) to memory?
+
+" /memory" find-device
+
+headerless
+
+h# 0400.0000 constant /ram-bank \ 64 MB banks
+
+h# ffff.ffff value low
+h# 0 value high
+
+: log&release ( adr len -- )
+
+ \ Don't erase the firmware! Reduce the length to avoid it.
+ 2dup over + ( adr len adr adr+len )
+ origin h# 20 - kseg0 - umin over - ( adr len adr len' )
+
+ \ Don't zero the memory
+ 2drop
+
+ over low umin to low ( adr len )
+ 2dup + high umax to high ( adr len )
+ release
+;
+
+: >bank-base ( index -- bank-pa ) d# 26 lshift ;
+: scan-banks ( total-size -- )
+ d# 4 0 do ( size )
+ dup if ( size )
+ i >bank-base ( size bank-adr )
+ over /ram-bank min ( size bank-adr this-size )
+ tuck log&release ( size this-size )
+ - ( size' )
+ then ( size' )
+ loop ( size' )
+ drop
+;
+headers
+: claim ( [ phys ] size align -- kseg0-adr ) claim kseg0 + ;
+: release ( kseg0-adr size -- )
+ over kseg0 u>= if swap kseg0 - swap then release
+;
+
+: probe ( -- )
+ h# 1000.0000
+ ( memsize-loc @ ) scan-banks
+
+ 0 0 encode-bytes ( adr 0 )
+ physavail ['] make-phys-memlist find-node ( adr len prev 0 )
+ 2drop " reg" property
+
+ \ Claim the megabyte used for the trap vectors, Forth, and the section table
+ 0 /resetjmp 0 claim drop
+ high h# 10.0000 - h# 10.0000 0 claim drop
+;
+
+device-end
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cobalt/reboot.fth
===================================================================
--- cpu/mips/cobalt/reboot.fth (rev 0)
+++ cpu/mips/cobalt/reboot.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,53 @@
+purpose: Save reboot info using /reboot-info device
+\ See license at end of file
+
+0 value reboot$
+d# 256 value /reboot$
+
+: copy-reboot-info ( -- )
+ " /reboot-info" open-dev ?dup 0= if exit then >r
+ /reboot$ alloc-mem to reboot$ ( )
+
+ reboot$ 1+ /reboot$ 1- " read" r@ $call-method ( actual )
+ dup 0>= dup to reboot? if ( actual )
+ reboot$ c! ( )
+ else ( -1 )
+ drop reboot$ /reboot$ free-mem ( )
+ then
+ r> close-dev
+;
+
+: (get-reboot-info) ( -- bootcmd$ line# column# ) reboot$ count 0 0 ;
+' (get-reboot-info) to get-reboot-info
+
+: (save-reboot-info) ( bootcmd$ line# column# -- )
+ 2drop
+ " /reboot-info" open-dev ?dup 0= if 2drop exit then >r ( cmd$ r: ih )
+ " write" r@ $call-method drop ( r: ih )
+ r> close-dev
+;
+' (save-reboot-info) to save-reboot-info
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cobalt/regacc.fth
===================================================================
--- cpu/mips/cobalt/regacc.fth (rev 0)
+++ cpu/mips/cobalt/regacc.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,33 @@
+purpose: Register access words for Cobalt
+\ See license at end of file
+
+: kseg1? ( adr -- adr flag ) dup h# f000.0000 and h# b000.0000 = ;
+
+\ ' x@ is rx@ ' x! is rx!
+' l@ is rl@ ' l! is rl!
+' w@ is rw@ ' w! is rw!
+' c@ is rb@ ' c! is rb!
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cobalt/reports.fth
===================================================================
--- cpu/mips/cobalt/reports.fth (rev 0)
+++ cpu/mips/cobalt/reports.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,76 @@
+purpose: Diagnostic display code for early startup
+\ See license at end of file
+
+\ For any Galileo-based MIPS system, e.g. Cobalt Raq2
+h# bc80.0000 constant ns16550-base
+
+label do-report ( t7: char -- )
+ ns16550-base t6 li
+ begin t6 h# 3fd $at lbu $at h# 20 $at andi $at 0 <> until nop
+ t7 t6 h# 3f8 sb
+ begin t6 h# 3fd $at lbu $at h# 20 $at andi $at 0 <> until nop
+
+ ra jr nop
+end-code
+
+\ Kills t6-t7
+: report ( char -- ) " do-report bal $0 swap t7 addiu" evaluate ;
+
+label do-nibble ( t7: digit -- )
+ t7 d# 28 t7 sll t7 d# 28 t7 srl \ Discard high bits
+ t7 h# a negate $at addiu
+ $at 0>= if nop
+ $at ascii A t7 addiu
+ else nop
+ t7 ascii 0 t7 addiu
+ then
+
+ ns16550-base t6 li
+ begin t6 h# 3fd $at lbu $at h# 20 $at andi $at 0 <> until nop
+ t7 t6 h# 3f8 sb
+ begin t6 h# 3fd $at lbu $at h# 20 $at andi $at 0 <> until nop
+
+ ra jr nop
+end-code
+
+label do-dot ( t8: val -- )
+ ra t9 move
+ do-nibble bal t8 d# 28 t7 srl
+ do-nibble bal t8 d# 24 t7 srl
+ do-nibble bal t8 d# 20 t7 srl
+ do-nibble bal t8 d# 16 t7 srl
+ do-nibble bal t8 d# 12 t7 srl
+ do-nibble bal t8 d# 8 t7 srl
+ do-nibble bal t8 d# 4 t7 srl
+ do-nibble bal t8 t7 move
+
+ bl report
+ t9 jr nop
+end-code
+
+\ Kills t6-t9
+: dot ( reg -- ) " do-dot bal t8 move" evaluate ;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/code.fth
===================================================================
--- cpu/mips/code.fth (rev 0)
+++ cpu/mips/code.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,103 @@
+purpose: Assembler macros specific to the virtual machine implementation
+\ See license at end of file
+
+: assembler ( -- ) mips-assembler ;
+
+: asm( also assembler ; immediate
+: )asm previous ; immediate
+
+only forth also assembler also definitions
+
+\ Forth Virtual Machine registers
+
+: np s1 ; : base s2 ; : up s3 ; : tos s4 ; : ip s5 ; : rp s6 ; : sp $sp ;
+
+: w t0 ;
+
+\ Macros:
+
+\ Put a bubble in the pipeline. Used between a load instruction and an
+\ immediately-following instruction that uses the load destination register.
+: bubble ( -- ) nop ;
+
+: get ( ptr dst -- ) 0 swap lw ;
+: put ( src ptr -- ) 0 sw ;
+: move ( src dst -- ) 0 swap addu ;
+: ainc ( ptr -- ) dup 4 swap addiu ;
+: adec ( ptr -- ) dup -4 swap addiu ;
+: push ( src ptr -- ) dup adec put ;
+: pop ( ptr dst -- ) over -rot get ainc ;
+
+: cmp ( src dst -- ) $at subu ;
+: cmpi ( src imm -- ) negate $at addiu ;
+
+: apf ( ptr dst -- ) w 4 ;
+
+\ The next few words are already in the forth vocabulary;
+\ we want them in the assembler vocabulary too
+alias next next
+' previous is do-exitcode
+headers
+alias c; c;
+
+: 'user# \ name ( -- user# )
+ ' ( acf-of-user-variable )
+ >body ( apf-of-user-variable )
+ @ ( user# )
+;
+: 'user \ name ( -- user-addressing-mode )
+ up 'user#
+;
+: 'body \ name ( -- variable-apf-offset )
+ ' ( acf-of-user-variable ) >body origin -
+;
+: 'acf \ name ( -- variable-acf-offset )
+ ' ( acf-of-user-variable ) origin -
+;
+: end-code ( -- )
+ [ forth ]
+ previous
+\ flush-cache \ Make new code available for instruction fetches
+ sp@ csp @ <> if last a@ .id ." : stack depth changed" cr then
+ current token@ context token! \ go back to old context
+;
+
+also forth definitions
+headerless
+: entercode ( -- )
+ also assembler
+ [ also assembler ] here delay-barrier ! [ previous ]
+;
+' entercode is do-entercode
+
+headers
+\ "code" is defined in the kernel
+
+: label \ name ( -- )
+ create !csp entercode
+;
+only forth also definitions
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cpubpsup.fth
===================================================================
--- cpu/mips/cpubpsup.fth (rev 0)
+++ cpu/mips/cpubpsup.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,106 @@
+purpose: Machine-dependent definitions for breakpoints
+\ See license at end of file
+
+h# 0000000d constant breakpoint-opcode
+defer breakpoint-trap?
+' true is breakpoint-trap?
+
+: op@ ( adr -- op ) l@ ;
+: op! ( op adr -- ) instruction! ;
+: bp-address-valid? ( adr -- flag ) 3 and 0= ;
+: at-breakpoint? ( adr -- flag ) op@ breakpoint-opcode = ;
+: put-breakpoint ( adr -- ) breakpoint-opcode swap op! ;
+
+: j? ( adr -- adr flag ) h# 0800.0000 h# fc00.0000 imatch? ;
+: jr? ( adr -- adr flag ) h# 0000.0008 h# fc00.003f imatch? ;
+: branch? ( adr -- flag )
+ h# 1000.0000 h# b000.0000 imatch? >r \ beq(l),bne(l),blez(l),bgtz(l)
+ h# 0400.0000 h# fc1c.0000 imatch? \ bltz,bgez,bltzl,bgezl
+ r> or
+;
+
+: delayed? ( adr -- flag )
+ j? swap jr? swap jal? swap jalr? swap bal? swap branch? swap
+ drop or or or or or
+;
+: .instruction ( -- )
+ $pc
+ [ also disassembler ] pc ! dis1 [ previous ]
+ $pc delayed? if
+ $pc la1+ [ also disassembler ] pc ! dis1 [ previous ]
+ then
+;
+
+\ Find the places to set the next breakpoint for single stepping.
+\ Usually the right place is at nPC . However, for annulled branch
+\ instructions, we have to cope with the possibility that the delay
+\ instruction, which is where nPC points, won't be executed. Annulled
+\ unconditional branches never execute the delay instruction, so we have
+\ to put the breakpoint at the branch target. Annulled conditional
+\ branches will either execute the delay instruction or the one right
+\ after it.
+
+: >after-delay ( adr -- adr' ) 2 la+ ;
+variable step?
+: next-instruction ( stepping? -- next-adr branch-target|0 )
+ step? !
+ $pc
+ j? if >j-target 0 exit then
+ jr? if >jr-target 0 exit then
+ jal? if step? @ if >j-target else >after-delay then 0 exit then
+ jalr? if step? @ if >jr-target else >after-delay then 0 exit then
+ bal? if
+ step? @ if dup >after-delay swap >br-target else >after-delay 0 then
+ exit
+ then
+ branch? if dup >after-delay swap >br-target exit then
+ la1+ 0
+;
+: bumppc ( -- ) $pc la1+ to $pc ;
+alias rpc $pc
+
+code goto ( adr -- )
+ tos t0 move
+ sp tos get
+ t0 jr
+ sp /n sp addiu
+end-code
+
+: return-adr ( -- adr ) $ra ;
+: leaf-return-adr ( -- adr ) $ra ;
+: backward-branch? ( adr -- flag ) \ True if adr points to a backward branch
+ dup branch? ( adr branch? )
+ swap l@ h# 0000.8000 and 0<> ( branch? backward? )
+ and
+;
+: loop-exit-adr ( -- adr )
+ \ Start at PC-4 in case we're sitting on a delay instruction at the loop end
+ $pc 4 - begin dup backward-branch? 0= while 4 + repeat 8 +
+;
+
+headers
+: set-pc ( adr -- ) to $pc ;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/cpustate.fth
===================================================================
--- cpu/mips/cpustate.fth (rev 0)
+++ cpu/mips/cpustate.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,53 @@
+purpose: Buffers for saving program state
+\ See license at end of file
+
+headers
+\ Data structures defining the CPU state saved by a breakpoint trap.
+\ This must be loaded before either catchexc.fth or register.fth,
+\ and is the complete interface between those 2 modules.
+
+headerless
+\ A place to save the CPU registers when we take a trap
+0 value /save-area
+0 value cpu-state
+
+: clear-save-area ( -- ) cpu-state /save-area erase ;
+
+h# 40 constant ua-size
+
+0 value pssave \ A place to save the Forth data stack
+0 value rssave \ A place to save the Forth return stack
+ua-size buffer: uasave \ A place to save part of the Forth user area
+ \ we really want to save saved-rp and saved-sp
+
+headers
+defer .exception \ Display the exception type
+defer handle-breakpoint \ What to do after saving the state
+
+: init ( -- )
+ init /save-area alloc-mem to cpu-state clear-save-area
+;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/ctrace.fth
===================================================================
--- cpu/mips/ctrace.fth (rev 0)
+++ cpu/mips/ctrace.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,128 @@
+purpose: After a crash, displays a backtrace of C stack frames.
+\ See license at end of file
+
+\ This is difficult to do in the MIPS C environment, because the
+\ return address is sometimes in a register and sometimes on the stack.
+
+only forth also hidden also forth definitions
+needs (rstrace rstrace.fth
+needs >saved savedstk.fth
+only forth also hidden also forth definitions
+
+: imatch? ( adr match mask -- adr flag ) 2 pick l@ and = ;
+: jal? ( adr -- adr flag ) h# 0c00.0000 h# fc00.0000 imatch? ;
+: jalr? ( adr -- adr flag ) h# 0000.0009 h# fc00.003f imatch? ;
+: bal? ( adr -- adr flag ) h# 4010.0000 h# fc1c.0000 imatch? ;
+
+: >jr-target ( adr -- target-adr )
+ \ Get the value of the register in the rs field
+ l@ d# 21 >> h# 1f and 2 << >state @
+;
+: >j-target ( adr -- target )
+ dup l@ h# 03ff.ffff and 2 << swap h# f000.0000 and or
+;
+: >br-target ( br-adr -- target )
+ dup l@ d# 16 << d# 14 >>a + la1+
+;
+: 9u.r ( u -- ) push-hex 9 u.r pop-base ;
+
+\ True if adr points to an "addiu sp,sp,-N" instruction
+: stack-push? ( adr -- flag ) l@ h# ffff8000 and h# 27bd8000 = ;
+
+\ Adjust the stack pointer if necessary
+: adjust-sp ( sp pc -- sp' )
+ dup stack-push? if ( sp pc )
+ l@ h# ffff and w->n - ( sp' )
+ else ( sp pc )
+ drop ( sp )
+ then ( sp' )
+;
+
+\ Given the address from which a function was called, display the
+\ name or address of the function and adjust the stack pointer
+\ to the value that it had upon entry to that function.
+: .function ( call-adr -- start-adr )
+ jal? if >j-target dup showaddr exit then
+ jalr? if >jr-target dup showaddr exit then \ leaf context only...
+ bal? if >br-target dup showaddr exit then
+ drop ." ??????" 0
+;
+: .args ( -- ) \ Show C function arguments
+ ." ( " $a0 .x $a1 .x $a2 .x $a3 .x ." ... )"
+;
+
+: .called ( call-adr -- ) ." called from " showaddr cr ;
+
+: .leaf-call ( ra -- start-adr ) dup .function .args swap .called ;
+
+: save-ra? ( adr -- flag ) l@ h# ffff0000 and h# afbf0000 = ;
+
+h# 8000.0000 value mem-base \ Change this to debug userland code
+
+: reasonable-adr? ( n -- flag )
+ dup 3 and if drop false exit then
+ mem-base dup h# 1000.0000 + within
+;
+
+: up1 ( sp ra -- sp' ra' )
+ \ Upon entry, ra is the return address - i.e. an address inside a
+ \ function. We determine the start of that function and display
+ \ its address, then find the new return address and adjust the stack
+ \ pointer. It would be nice to display the arguments too, but that's
+ \ not so easy.
+
+ \ The current version of GCC starts non-leaf functions with
+ \ "addiu sp,sp,-N", so look backward for such an instruction.
+ begin
+ /l -
+ dup reasonable-adr? 0= if drop 0 exit then
+ dup stack-push?
+ until ( sp start-adr )
+
+ dup showaddr ." " ( sp start-adr )
+
+ \ Find the instruction that saves the return address on the stack
+ dup /l -
+ begin la1+ dup save-ra? until ( sp start-adr save-ra-adr )
+
+ \ Find the saved return address
+ l@ h# ffff and w->n ( sp start-adr stack-offset )
+ 2 pick + >saved l@ ( sp start-adr ra )
+
+ >r adjust-sp r> ( sp ra )
+ dup 8 - .called
+;
+
+: ctrace ( -- ) \ C stack backtrace
+ ." Most-recently-called function: " cr
+ $ra 8 - .leaf-call ( sp start-adr )
+
+ $sp swap adjust-sp ( sp' )
+
+ $ra begin dup reasonable-adr? while up1 repeat ( sp' ra' )
+ 2drop
+;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/debugm.fth
===================================================================
--- cpu/mips/debugm.fth (rev 0)
+++ cpu/mips/debugm.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,156 @@
+purpose: CPU-dependent definitions for the source-level debugger
+\ See license at end of file
+
+create no-secondary-cache
+
+true value debug-sync-cache?
+
+: at ( row column -- ) 2drop ;
+: kill-line ( -- ) ;
+
+hex
+
+: low-dictionary-adr ( -- adr ) origin init-user-area + ;
+
+nuser debug-next \ Pointer to "next"
+vocabulary bug bug also definitions
+nuser 'debug \ code field for high level trace
+nuser <ip \ lower limit of ip
+nuser ip> \ upper limit of ip
+nuser cnt \ how many times thru debug next
+
+\ Since we use a shared "next" routine, slow-next and fast-next are no-op's
+alias slow-next 2drop ( high low -- )
+alias fast-next 2drop ( high low -- )
+
+[ifndef] np@
+code np@ ( -- adr ) tos sp push np tos move c;
+[then]
+
+: copy-next ( -- )
+ \ Copy the normal next routine
+ here 8 /n* dup allot ( adr size )
+ np@ -rot cmove
+;
+
+: sync-cache, ( -- )
+ asm(
+\ np 0 5 cache np 4 5 cache
+ " 'user debug-sync-cache?" eval $at lw
+ $at $0 <> if
+ nop
+ np 0 h# 19 cache np 4 h# 19 cache \ WriteBack primary D$
+[ifndef] no-secondary-cache
+ np 0 h# 1b cache np 4 h# 1b cache \ WriteBack secondary D$
+ np 0 h# 12 cache np 4 h# 12 cache \ Invalidate secondary I$
+[then]
+ np 0 h# 10 cache np 4 h# 10 cache \ Invalidate primary I$
+ then
+\ 3 $a2 li h# 40 $a1 li np $a0 move d# 1150 v0 li syscall
+ )asm
+;
+
+label normal-next
+ copy-next
+end-code
+
+label debnext
+ 'user <ip t0 lw
+ bubble
+ ip t0 t1 subu
+ t1 0>= if nop
+ 'user ip> t0 lw
+ bubble
+ ip t0 t1 subu
+ t1 0<= if nop
+ 'user cnt t0 lw
+ 2 t1 li
+ t0 1 t0 addiu
+ t0 'user cnt sw
+ t0 t1 = if nop
+ $0 'user cnt sw
+
+ h# 8ea80000 t0 li \ "ip 0 t0 lw"
+ t0 np 0 sw
+ h# 01124021 t0 li \ "w base w addu"
+ t0 np 4 sw
+\ This is for the old version where the "bubble" macro assembles a nop
+\ $0 np 4 sw \ nop
+
+ sync-cache,
+
+ \ Machine code for 'debug token@ execute
+ 'user 'debug w lw
+ bubble
+ w base w addu
+ w 0 t1 lw
+ bubble
+ t1 base t1 addu
+ t1 jr
+ nop
+ then
+ then
+ then
+ copy-next
+end-code
+
+\ Fix the next routine to use the debug version
+code pnext (s -- )
+ debnext origin - t0 li \ Relative address of debnext
+ t0 base t0 addu \ Absolute address of debnext
+
+
+ t0 4 t0 sll \ Erase top 4 bits
+ t0 6 t0 srl \ Erase bottom 2 bits
+ h# 0800.0000 t1 li \ "j" instruction template
+ t1 t0 t0 addu \ "j debnext"
+ t0 np 0 sw \ Write to first location in "next"
+ $0 np 4 sw \ "nop"
+
+ sync-cache,
+c;
+
+\ Turn off debugging
+code unbug (s -- )
+ h# 8ea80000 t0 li \ "ip 0 t0 lw"
+ t0 np 0 sw
+ h# 01124021 t0 li \ "w base w addu"
+ t0 np 4 sw
+\ This is for the old version where the "bubble" macro assembles a nop
+\ $0 np 4 sw \ "nop"
+
+ sync-cache,
+c;
+
+forth definitions
+
+\ Cannot execute cache instructions under development evironment.
+[ifdef] debug-on-cobalt
+unbug
+[else]
+normal-next debug-next !
+[then]
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/decompm.fth
===================================================================
--- cpu/mips/decompm.fth (rev 0)
+++ cpu/mips/decompm.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,54 @@
+purpose: Machine/implementation-dependent definitions for the decompiler
+\ See license at end of file
+
+decimal
+headerless
+
+only forth also hidden also definitions
+: dictionary-base ( -- adr ) origin ;
+
+: ram/rom-in-dictionary? ( adr -- flag )
+ dup #talign 1- and 0= if
+ dup lo-segment-base lo-segment-limit within
+ swap hi-segment-base hi-segment-limit within or
+ else
+ drop false
+ then
+;
+
+' ram/rom-in-dictionary? is in-dictionary?
+
+\ True if adr is a reasonable value for the interpreter pointer
+: reasonable-ip? ( adr -- flag )
+ dup in-dictionary? if ( ip )
+ #talign 1- and 0= \ must be token-aligned
+ else
+ drop false
+ then
+;
+only forth also definitions
+headers
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/disassem.fth
===================================================================
--- cpu/mips/disassem.fth (rev 0)
+++ cpu/mips/disassem.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,473 @@
+purpose: MIPS disassembler
+\ See license at end of file
+
+vocabulary disassembler
+also disassembler also definitions
+
+headerless
+
+string-array real-regs
+," $0" ," $1" ," v0" ," v1"
+," a0" ," a1" ," a2" ," a3"
+," t0" ," t1" ," t2" ," t3"
+," t4" ," t5" ," t6" ," t7"
+," s0" ," s1" ," s2" ," s3"
+," s4" ," s5" ," s6" ," s7"
+," t8" ," t9" ," k0" ," k1"
+," gp" ," sp" ," s8" ," ra"
+end-string-array
+
+defer regs ' real-regs is regs
+
+string-array normalops
+\ o# 0X
+," " ," " \ special and regimm
+," j" ," jal" \ target
+," beq" ," bne" \ rs,rt,offset
+," blez" ," bgtz" \ rs,offset
+
+\ o# 1X
+," addi" ," addiu" ," slti" ," sltiu" \ rt,rs,immed
+," andi" ," ori" ," xori" ," lui" \ rt,rs,immed
+
+\ o# 2X
+," " ," " ," " ," " \ cop0, cop1, cop2, cop1x
+," " ," " ," " ," " \ beql, bnel, blezl, bgtzl (obsolescent)
+
+\ o# 3X
+," daddi" ," daddiu" \ rt,rs,immed
+," ldl" ," ldr" \ rt,offset(base)
+," " ," jalx" ," " ," " \ special2, jalx, mdmx, reserved
+
+\ o# 4X
+," lb" ," lh" ," lwl" ," lw" \ rt,offset(base)
+," lbu" ," lhu" ," lwr" ," lwu" \ rt,offset(base)
+
+\ o# 5X
+," sb" ," sh" ," swl" ," sw" \ rt,offset(base)
+," sdl" ," sdr" ," swr" \ rt,offset(base)
+," cache" \ code,offset(base)
+
+\ o# 6X
+," ll" ," lwc1" ," lwc2" ," pref" \ rt,offset(base)
+," lld" ," ldc1" ," ldc2" ," ld" \ rt,offset(base)
+
+\ o# 7X
+," sc" ," swc1" ," swc2" ," " \ rt,offset(base)
+," scd" ," sdc1" ," sdc2" ," sd" \ rt,offset(base)
+end-string-array
+
+string-array specialops
+\ o# 0X
+," sll" ," " ," srl" ," sra" \ rd,rt,sa (hole is movci)
+," sllv" ," " ," srlv" ," srav" \ rd,rt,rs
+\ o# 1X
+," jr" \ rs
+," jalr" \ rd,rs
+," movz" ," movn"
+," syscall" ," break" ," " ," sync" \ -
+\ o# 2X
+," mfhi" \ rd
+," mthi" \ rs
+," mflo" \ rd
+," mtlo" \ rs
+," dsllv" ," " ," dsrlv" ," dsrav" \ rd,rt,rs
+\ o# 3X
+," mult" ," multu" ," div" ," divu" \ rs,rt
+," dmult" ," dmultu" ," ddiv" ," ddivu" \ rs,rt
+\ o# 4X
+," add" ," addu" ," sub" ," subu" \ rd,rs,rt
+," and" ," or" ," xor" ," nor" \ rd,rs,rt
+\ o# 5X
+," " ," " ," slt" ," sltu" \ rd,rs,rt
+," dadd" ," daddu" ," dsub" ," dsubu" \ rd,rs,rt
+\ o# 6X
+," tge" ," tgeu" ," tlt" ," tltu" \ rs,rt
+," teq" ," " ," tne" ," " \ rs,rt
+\ o# 7X
+," dsll" ," " ," dsrl" ," dsra" \ rd,rt,sa
+," dsll32" ," " ," dsrl32" ," dsra32" \ rd,rt,sa
+end-string-array
+
+string-array regimmops
+\ o# 0X
+," bltz" ," bgez" ," bltzl" ," bgezl" \ rs,offset
+," " ," " ," " ," "
+\ o# 1X
+," tgei" ," tgeiu" ," tlti" ," tltiu" \ rs,immed
+," teqi" ," " ," tnei" ," " \ rs,immed
+\ o# 2X
+," bltzal" ," bgezal" ," bltzall" ," bgezall" \ rs,offset
+," " ," " ," " ," "
+\ o# 3X
+," " ," " ," " ," "
+," " ," " ," " ," "
+end-string-array
+
+decimal
+\ Generates a mask with #bits set in the low part. 4 >mask yields 0000000f
+lvariable instruction
+variable end-found
+lvariable pc
+lvariable display-offset 0 display-offset l!
+lvariable branch-target \ Help for tracing/single-stepping
+
+' ul. is showaddr
+
+: +offset ( adr -- adr' ) display-offset l@ - ;
+: >mask ( #bits -- mask ) -1 32 rot - >> ;
+: bits ( right-bit #bits -- field )
+ instruction l@ rot >> ( #bits shifted-instruction )
+ swap >mask land ( field )
+;
+: bit? ( bit# -- f ) instruction l@ 1 rot lshift land ;
+
+\ Display formatting
+variable start-column
+: op-col ( -- ) start-column @ d# 8 + to-column ;
+
+: ., ( -- ) ." ," ;
+: 5bits ( pos -- bits ) 5 bits ;
+: rd ( -- n ) 11 5bits ;
+: rt ( -- n ) 16 5bits ;
+: rs ( -- n ) 21 5bits ;
+: sa ( -- n ) 6 5bits ;
+: .freg ( n -- ) dup d# 16 < if ." FGR" else ." FPR" then .d ;
+: .dreg ( n -- ) ." DR" .d ;
+: .reg ( n -- ) regs ". ;
+: .rd ( -- ) rd .reg ;
+: .rs ( -- ) rs .reg ;
+: .rt ( -- ) rt .reg ;
+: 2u.d ( n -- ) base @ >r decimal 0 <# # # #> type r> base ! ;
+: 8u.h ( n -- ) base @ >r hex 0 <# # # # # # # # # #> type r> base ! ;
+: 0s.h ( n -- ) base @ >r hex (.) type r> base ! ;
+: .sa ( n -- ) sa 2u.d ;
+: simmed ( -- n ) 0 16 bits 16 << 16 >>a ;
+: 0immed ( -- u ) 0 16 bits 16 << 16 >> ;
+: .target ( -- )
+ pc @ h# f000.0000 and 0 26 bits 2 << or 8u.h
+;
+: opcode ( -- n ) 26 6 bits ;
+: funct ( -- n ) 0 6 bits ;
+: .broffset ( -- ) pc l@ 4 + simmed 2 << + 8u.h ;
+: .rs,rt,offset ( -- ) .rs ., .rt ., .broffset ;
+: .rs,offset ( -- ) .rs ., .broffset ;
+: .rt,offset(base) ( -- ) .rt ., simmed 0s.h ." (" .rs ." )" ;
+: .rd,rt,sa ( -- ) .rd ., .rt ., .sa ;
+: .rd,rt,rs ( -- ) .rd ., .rt ., .rs ;
+: .rs,rt ( -- ) .rs ., .rt ;
+: .rd,rs ( -- ) .rd ., .rs ;
+: .rd,rs,rt ( -- ) .rd ., .rs ., .rt ;
+: .rs,immed ( -- ) .rs ., simmed 0s.h ;
+: .rt,rs,immed ( n -- ) .rt ., .rs ., 0s.h ;
+: .unimp ( -- ) ." UNIMP" op-col ;
+
+string-array cachesps
+," I" ," D" ," SI" ," SD"
+end-string-array
+string-array cacheops
+," IndexInvalidate" ," IndexWriteBackInvalidate" ," IndexInvalidate" ," IndexWriteBackkInvalidate"
+," IndexLoadTag" ," IndexLoadTag" ," IndexLoadTag" ," IndexLoadTag"
+," IndexStoreTag" ," IndexStoreTag" ," IndexStoreTag" ," IndexStoreTag"
+," " ," CreateDirtyExclusive" ," " ," CreateDirtyExclusive"
+," HitInvalidate" ," HitInvalidate" ," HitInvalidate" ," HitInvalidate"
+," Fill" ," HitWriteBackInvalidate" ," " ," HitWriteBackInvalidate"
+," HitWriteBack" ," HitWriteBack" ," " ," HitWriteBack"
+," " ," " ," HitSetVirtual" ," HitSetVirtual"
+end-string-array
+
+: .cache ( -- )
+ rt cacheops ".
+ ." (" 16 2 bits cachesps ". ." )"
+ ., simmed 0s.h ." (" .rs ." )"
+;
+
+: .op ( pstr -- )
+ dup c@ 0= if drop .unimp else ". op-col then
+;
+: above ( selector limit -- selector testval ) over tuck > if 1- then ;
+: .regimm ( -- )
+ rt dup regimmops .op ( opbits )
+ o# 10 o# 20 within if .rs,immed else .rs,offset then
+;
+: .iw instruction l@ 8u.h ;
+: bits23..21 ( -- n ) d# 21 3 bits ;
+
+string-array bcops
+," f" ," t" ," fl" ," tl"
+end-string-array
+
+: .bad ( -- ) .unimp .iw ;
+: .fop ( pstr -- )
+ ". rs case
+ o# 20 of ." .s" endof
+ o# 21 of ." .d" endof
+ o# 24 of ." .w" endof
+ ( default ) ." .?"
+ endcase
+ op-col
+;
+: .f1r ( -- ) sa .freg ., rd .freg ;
+: .f2r ( -- ) .f1r ., rt .freg ;
+: bits2..0 ( -- n ) 0 3 bits ;
+string-array cvtops
+ ," cvt.s" ," cvt.d" ," " ," " ," cvt.w" ," cvt.l" ," cvt.ps" ," "
+end-string-array
+
+: bits2..0 ( -- n ) 0 3 bits ;
+
+string-array fcalcops
+ ," add" ," sub" ," mul" ," div" ," sqrt" ," abs" ," mov" ," neg"
+
+end-string-array
+
+string-array fc1ops
+ ," round" ," trunc" ," ceil" ," floor"
+end-string-array
+
+string-array fcmpops
+ ," c.f" ," c.un" ," c.eq" ," c.ueq"
+ ," c.olt" ," c.ult" ," c.ole" ," c.ule"
+ ," c.sf" ," c.ngle" ," c.seq" ," c.ngl"
+ ," c.lt" ," c.nge" ," c.le" ," c.ngt"
+end-string-array
+
+: .fcmp ( -- )
+ 0 4 bits fcmpops .fop rd .freg ., rt .freg
+;
+
+[ifdef] notyet
+string-array f2ops
+ ," " ," {movcf}" ," movz" ," movn" ," " ," recip" ," rsqrt" ," "
+end-string-array
+string-array f3ops
+ ," recip2" ," recip1" ," rsqrt1" ," rsqrt2"
+end-string-array
+[then]
+
+: .fcalc ( -- )
+ 3 3 bits case
+ 0 of bits2..0 dup fcalcops .fop 4 < if .f2r else .f1r then endof
+ 1 of bits2..0 4 - dup 0< if drop .bad else fc1ops .fop .f1r then endof
+[ifdef] notyet
+ 2 of bits2..0 f2ops .fop ( .f1r ??) endof
+ 3 of bits2..0 4 - dup 0< if drop .bad else f3ops .fop ( .f1r ??) then endof
+[then]
+ 4 of bits2..0 cvtops .fop .f1r endof
+ 6 of .fcmp endof
+ 7 of .fcmp endof
+ ( default ) .bad
+ endcase
+;
+
+string-array cp0ops
+ ," "
+ ," tlbr"
+ ," tlbwi"
+ ," " ," " ," "
+ ," tlbwr"
+ ," "
+ ," tlbp"
+ ," " ," " ," " ," " ," " ," " ," " \ holes
+ ," " ," " ," " ," " ," " ," " ," " ," " \ holes
+ ," eret" ," " ," " ," " ," " ," " ," " ," deret"
+ ," wait"
+end-string-array
+
+: .cp0 ( -- )
+ pc l@ l@ h# 3f and h# 18 = end-found !
+ 0 6 bits cp0ops .op
+;
+
+string-array mfcops \ rt(16), fs(11=rd)
+," mfc" ," dmfc" ," cfc" ," " ," mtc" ," dmtc" ," ctc" ," "
+," bc" ," bcany2" ," bcany4" ," " ," " ," " ," " ," "
+," s" ," d" ," " ," " ," w" ," l" ," ps" ," "
+end-string-array
+
+: .(cop) ( pstr -- )
+ dup c@ 0= if drop ." UNIMP" else ". d# 26 2 bits ascii 0 + emit then
+;
+
+: .copx ( -- )
+ d# 24 2 bits case
+ 0 of ." Coprocessor instruction " .iw
+ 1 of bits23..21 if
+ .bad
+ else
+ rt 4 > if .bad else rs mfcops .(cop) rt bcops .op .broffset then
+ then
+ endof
+ ( default ) .bad
+ endcase
+;
+
+: .cop0 ( -- )
+ d# 24 2 bits case
+ 0 of rs mfcops .(cop) op-col .rt ., rd 2u.d endof
+ 1 of bits23..21 if
+ .bad
+ else
+ rt 4 > if .bad else rs mfcops .(cop) rt bcops .op .broffset then
+ then
+ endof
+ 2 of .cp0 endof
+ 3 of .bad endof
+ endcase
+;
+
+: .cop1 ( -- )
+ d# 24 2 bits case
+ 0 of rs mfcops .(cop) op-col .rt ., rd .freg endof
+ 1 of bits23..21 if
+ .bad
+ else
+ rt 4 > if .bad else rs mfcops .(cop) rt bcops .op .broffset then
+ then
+ endof
+ 2 of .fcalc endof
+ ( default ) .bad
+ endcase
+;
+
+: .special ( -- )
+ \ Stop when we see jr
+ pc l@ l@ h# fc00.003f and h# 0000.0008 = end-found !
+
+ 0 6 bits dup specialops .op ( opbits )
+ case
+ o# 70 above of .rd,rt,sa endof
+ o# 60 above of .rs,rt endof
+ o# 40 above of .rd,rs,rt endof
+ o# 30 above of .rs,rt endof
+ o# 24 above of .rd,rt,rs endof
+ o# 23 of .rs endof
+ o# 22 of .rd endof
+ o# 21 of .rs endof
+ o# 20 of .rd endof
+ o# 14 above of endof \ no operands
+ o# 11 above of .rd,rs endof
+ o# 10 above of .rs endof
+ o# 04 above of .rd,rt,rs endof
+ ( default ) .rd,rt,sa
+ endcase
+;
+
+\ XXX implement me
+: .mdmx ( -- ) ." MDMX ..." cr ;
+
+: .special2 ( -- )
+ \ Stop when we see jr
+ pc l@ l@ h# 0000.003f and h# 0000.003e = end-found !
+
+ 0 6 bits case
+[ifdef] notyet
+ o# 00 of ." madd" endof
+ o# 01 of ." maddu" endof
+ o# 02 of ." mul" endof
+ o# 04 of ." msub" endof
+ o# 05 of ." msubu" endof
+ o# 40 of ." clz" endof
+ o# 41 of ." clo" endof
+ o# 44 of ." dclz" endof
+ o# 45 of ." dclo" endof
+[then]
+ o# 75 of rs case
+ 0 of ." mfdr" .rt ., rd .dreg endof
+ 4 of ." mtdr" .rt ., rd .dreg endof
+ ( default ) .rd,rt,rs
+ endcase
+ o# 76 of ." dret" endof
+ o# 77 of ." dbreak" endof
+ ( default ) .rd,rt,sa
+ endcase
+;
+
+: .normal ( -- )
+ \ Stop when we see j
+ pc l@ l@ h# fc00.0000 and h# 0800.0000 = end-found !
+ 26 6 bits dup normalops .op ( opbits )
+ case
+ o# 60 above of .rt,offset(base) endof
+ o# 57 of .cache endof
+ o# 32 above of .rt,offset(base) endof
+ o# 30 above of simmed .rt,rs,immed endof
+ o# 26 above of .rs,offset endof
+ o# 24 above of .rs,rt,offset endof
+ o# 17 above of .rt ., 0immed 16 << 8u.h endof
+ o# 14 above of 0immed .rt,rs,immed endof
+ o# 10 above of simmed .rt,rs,immed endof
+ o# 06 above of .rs,offset endof
+ o# 04 above of .rs,rt,offset endof
+ ( default ) .target
+ endcase
+;
+
+: disasm ( 32b -- )
+ instruction l!
+ 26 6 bits case
+ 0 of .special endof
+ 1 of .regimm endof
+ o# 20 of .cop0 endof
+ o# 21 of .cop1 endof
+ o# 22 of .copx endof
+ o# 23 of .copx endof
+ o# 34 of .special2 endof
+ o# 36 of .mdmx endof
+ ( default ) .normal
+ endcase
+ cr
+;
+
+forth definitions
+headers \ ****************
+alias disasm disasm
+\ : .5bits ( n -- n' )
+\ octal
+\ ascii . hold over h# 1f and 0 # # 2drop drop 5 >> 0
+\ ;
+\ : .xop ( -- )
+\ pc l@ l@ 0 <# # # # # .5bits .5bits ascii . hold # # #> type hex
+\ ;
+: .xop ;
+: dis1 ( -- )
+ ??cr
+ pc l@ +offset showaddr 2 spaces .xop
+ 4 spaces #out @ start-column !
+ pc l@ l@ disasm
+ /l pc +!
+;
+: +dis ( -- )
+ base @ >r hex
+ end-found off
+ begin dis1 end-found @ exit? or until
+ dis1 \ Disassemble the delay instruction too
+ r> base !
+;
+: dis ( adr -- ) pc l! +dis ;
+alias (dis dis
+previous previous definitions
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/field.fth
===================================================================
--- cpu/mips/field.fth (rev 0)
+++ cpu/mips/field.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,45 @@
+purpose: Optimized struct and field for MIPS
+\ See license at end of file
+
+\ to the base address of the structure
+
+: struct ( -- 0 ) 0 ;
+
+: field \ name ( offset size -- offset+size )
+ create over , +
+
+ \ The high level equivalent of what the following machine code is:
+ \ does> @ + ;
+ \ We write it in code because the metacompiler facilities for
+ \ resolving DOES> clauses are clumsy
+
+ ;code ( struct-adr -- field-adr )
+ sp t0 pop \ Get the struct address
+ tos 0 tos lw \ Get the structure member offset
+ bubble
+ tos t0 tos addu \ Return the structure member address
+c;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/filecode.fth
===================================================================
--- cpu/mips/filecode.fth (rev 0)
+++ cpu/mips/filecode.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,153 @@
+purpose: Code words to support the file system interface
+\ See license at end of file
+
+code ln+ (s n1 n2 -- n3 ) sp t0 pop tos t0 tos addu c;
+
+\ &ptr is the address of a pointer. fetch the pointed-to
+\ character and post-increment the pointer
+
+code @c@++ ( &ptr -- char )
+ tos t0 get \ Fetch the pointer
+ tos t1 move \ Copy of the address
+ t0 0 tos lbu \ Get the byte
+ t0 1 t0 addiu \ Increment the pointer
+ t0 t1 put \ Replace the pointer
+c;
+
+\ &ptr is the address of a pointer. store the character into
+\ the pointed-to location and post-increment the pointer
+
+code @c!++ ( char &ptr -- )
+ tos t0 get \ Fetch the pointer
+ sp t1 pop \ char in t1
+ t1 t0 0 sb \ Put the byte
+ t0 1 t0 addiu \ Increment the pointer
+ t0 tos put \ Replace the pointer
+ sp tos pop \ Fixup top of stack
+c;
+
+\ "adr1 len2" is the longest initial substring of the string "adr1 len1"
+\ that does not contain the character "char". "adr2 len1-len2" is the
+\ trailing substring of "adr1 len1" that is not included in "adr1 len2".
+\ Accordingly, if there are no occurrences of that character in "adr1 len1",
+\ "len2" equals "len1", so the return values are "adr1 len1 adr1+len1 0"
+
+code split-string ( adr1 len1 char -- adr1 len2 adr1+len2 len1-len2 )
+ \ char in tos
+ sp 0 t1 lw \ len1
+ sp 4 t0 lw \ adr1
+ sp -4 sp addiu \ Make room for extra return value
+
+ t1 $0 <> if \ If string not empty
+ t0 t1 t3 addu \ Delay: Loop limit
+ begin \ t0 points to next character
+ t0 0 t2 lbu \ Get the next character
+ bubble
+ tos t2 = if \ Exit if delimiter found
+ t0 1 t0 addiu \ Delay: Increment address
+
+ t0 -1 t0 addiu \ Cancel last increment
+
+ t3 t1 t1 subu \ Reconstruct adr1
+ t0 t1 t1 subu \ Compute len2
+ t1 sp 4 sw \ .. and store on stack
+
+ t0 sp 0 sw \ store adr1+len2 on stack
+
+ t3 t0 tos sub \ Return len1-len2
+ next
+ then
+ t0 t3 = until
+ nop
+ then
+ \ The test character is not present in the input string
+
+ t3 sp 0 sw \ Store adr1+len2 on stack
+ $0 tos move \ Return rem-len=0
+c;
+
+\ Splits a buffer into two parts around the first line delimiter
+\ sequence. A line delimiter sequence is either CR, LF, CR followed by LF,
+\ or LF followed by CR.
+\ adr1 len2 is the initial substring before, but not including,
+\ the first line delimiter sequence.
+\ adr2 len3 is the trailing substring after, but not including,
+\ the first line delimiter sequence.
+
+code parse-line ( adr1 len1 -- adr1 len2 adr1+len2 len1-len2 )
+ tos t1 move \ len1
+ sp 0 t0 lw \ adr1
+ sp -8 sp addiu \ Make room for extra return values
+
+ $0 h# 0a tos addiu \ Delimiter 1
+ $0 h# 0d t4 addiu \ Delimiter 2
+
+ t1 $0 <> if \ If string not empty
+ t0 t1 t3 addu \ Delay: Loop limit
+ begin \ t0 points to next character
+ t0 0 t2 lbu \ Get the next character
+ bubble
+
+ tos t2 <> if \ Compare to linefeed
+ t0 1 t0 addiu \ Delay: Increment address
+ t4 t2 = if \ Compare to return
+ nop \ Delay
+ but then \ target of linefeed comparison branch
+ \ One of the delimiters matches
+
+ t3 t1 t1 subu \ Reconstruct adr1
+ t0 t1 t1 subu \ Compute len2
+ t1 -1 t1 addiu \ Account for incremented pointer
+ t1 sp 4 sw \ .. and store on stack
+
+ \ Check next character too, unless we're at the
+ \ end of the buffer
+ t0 t3 <> if nop
+ t0 1 t5 lbu \ Get the next character
+ bubble
+ \ Compare next character to other delimiter
+ tos t2 = if nop t4 tos move then \ Other delim in tos
+ tos t5 <> if nop \ If nextchar equals other delim...
+ t0 1 t0 addiu \ ... consume it
+ then
+ then
+ t0 sp 0 sw \ store adr1+len2 on stack
+ t3 t0 tos subu \ Return len1-len2
+ next
+ then
+ t0 t3 = until
+ nop
+ then
+ \ There is no line delimiter in the input string
+
+ t0 sp 0 sw \ Store adr1+len2 on stack
+ $0 tos move \ Return rem-len=0
+c;
+
+headers
+
+nuser delimiter
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/finish.fth
===================================================================
--- cpu/mips/finish.fth (rev 0)
+++ cpu/mips/finish.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,53 @@
+purpose: Final steps of kernel metacompilation for MIPS
+\ See license at end of file
+
+\ ' sys-init-io is init-io
+
+\ hex
+\ " root" $sfind drop resolution@ >user-t link-t@
+\ begin dup u. dup origin-t <> while /link-t - link@-t repeat drop cr
+\ cr
+\ " forth" $sfind drop resolution@ >user-t link-t@
+\ begin dup u. dup origin-t <> while /link-t - link@-t repeat drop cr
+\ cr
+
+
+also assembler
+\ cld 8 + cld branch!
+\ 'body cold-code cld 8 + branch!
+previous
+variable dodoesaddr
+
+' init is do-init
+
+assembler dodoes meta is dodoesaddr
+forth-h
+metaoff
+only forth also meta also definitions
+fix-vocabularies
+only forth also definitions
+' symbols fixall
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/fixvoc.fth
===================================================================
--- cpu/mips/fixvoc.fth (rev 0)
+++ cpu/mips/fixvoc.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,51 @@
+purpose: Post-fixup of metacompiled vocabularies for MIPS
+\ See license at end of file
+
+\ Nasty kludge to resolve the to pointer to the does> clause of vocabulary
+\ within "forth". The problem is that the code field of "forth" contains
+\ a call instruction to the does> clause of vocabulary. This call is a
+\ forward reference which cannot be resolved in the same way as compiled
+\ addresses.
+
+: used-t ( definer-acf child-acf -- )
+ [ also meta ] token!-t [ previous ]
+;
+
+: fix-vocabularies ( -- )
+ [""] <vocabulary> also symbols find previous ( acf true | str false )
+ 0= abort" Can't find <vocabulary> in symbols"
+ dup resolution@ >r ( acf ) ( Return stack: <vocabulary>-adr )
+ dup first-occurrence@ ( acf occurrence )
+ \ Don't let fixall muck with this entry later
+ 0 rot >first-occurrence ! ( occurrence )
+ begin another-occurrence? while ( occurrence )
+ dup [ meta ] token@-t [ forth ] swap ( next-occurrence occurrence )
+ \ Calculate the longword offset to the vocabulary does> clause
+ r@ swap used-t
+ repeat
+ r> drop
+;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/float.fth
===================================================================
--- cpu/mips/float.fth (rev 0)
+++ cpu/mips/float.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,353 @@
+purpose: Forth Floating point package for MIPS
+\ See license at end of file
+
+\ Has a separate floating point stack.
+\ All floating point numbers are IEEE double-precision format.
+
+\ Additional floating point words, including input and output conversion,
+\ are in unix/sparc/floatext.fth
+
+hex
+only forth definitions vocabulary floating
+only forth also hidden also floating also definitions
+
+create float.fth
+
+16 constant f#places
+8 constant /f
+/f constant f#bytes
+
+: align8 ( adr -- adr' ) 7 + -8 and ;
+h# 20 /f * constant /fstack
+
+/fstack /f + buffer: fstack \ Including slack for alignment
+
+/l ualloc user fp0
+
+: fp ( -- n ) [ assembler ] s7 ;
+
+code fp! ( adr -- ) tos fp move sp tos pop c;
+code fp@ ( adr adr ) tos sp push fp tos move c;
+
+: fclear ( -- ) fp0 l@ fp! ;
+: finit ( -- ) fstack align8 /fstack + /f - fp0 l! fclear ;
+
+finit
+: fdepth ( -- n ) fp0 l@ fp@ - /f / ;
+
+code f+ ( f1 f2 -- f3 )
+ fp 0 $f3 lwc1
+ fp 4 $f2 lwc1
+ fp /f fp addiu
+ $f0 $f2 $f0 addf .d
+c;
+code f- ( f1 f2 -- f3 )
+ fp 0 $f3 lwc1
+ fp 4 $f2 lwc1
+ fp /f fp addiu
+ $f2 $f0 $f0 subf .d
+c;
+code f* ( f1 f2 -- f3 )
+ fp 0 $f3 lwc1
+ fp 4 $f2 lwc1
+ fp /f fp addiu
+ $f0 $f2 $f0 mulf .d
+c;
+code f/ ( f1 f2 -- f3 )
+ fp 0 $f3 lwc1
+ fp 4 $f2 lwc1
+ fp /f fp addiu
+ $f2 $f0 $f0 divf .d
+c;
+
+code fsqrt ( f1 -- f2 ) $f0 $f0 sqrt .d c;
+code fnegate ( f1 -- f2 ) $f0 $f0 negf .d c;
+code fabs ( f1 -- f2 ) $f0 $f0 abs .d c;
+
+variable cond
+: leaveflag ( -- )
+ asm(
+ \ CMP.cond.D $f2,$f0
+ cop1 .d $f2 rd $f0 rt h# 30 addbits cond @ h# f land addbits
+
+ tos sp push
+ here h# 0c + cond @ h# 10 land [ also forth ] if [ previous ]
+ bc1f
+ [ also forth ] else [ previous ]
+ bc1t
+ [ also forth ] then [ previous ]
+ $0 -1 tos addiu \ Delay slot, always executed
+ $0 tos move \ Executed only if condition is false
+ ( then )
+ fp /f $f1 lwc1
+ fp /f 4 + $f0 lwc1
+ fp /f fp addiu
+ c;
+ )asm
+;
+: binaryfcmp: ( extension-field -- ) ( Later: f1 f2 -- flag )
+ cond !
+ code
+
+ asm(
+ fp 0 $f3 lwc1
+ fp 4 $f2 lwc1
+ fp /f fp addiu
+ )asm
+
+ leaveflag
+;
+: unaryfcmp: ( extension-field -- ) ( Later: f1 -- flag )
+ cond !
+ code
+ asm(
+ $f2 $0 mtc1 bubble
+ $f2 $f2 cvt.d .w
+ )asm
+ leaveflag
+;
+
+\ The inverse sense of extension-code for the binary comparisons is
+\ because the operands come off the stack in the reverse order
+
+assembler also
+
+ 2 binaryfcmp: f=
+12 binaryfcmp: f<>
+ 4 binaryfcmp: f<
+1f binaryfcmp: f>
+ e binaryfcmp: f<=
+1d binaryfcmp: f>=
+
+ 2 unaryfcmp: f0=
+12 unaryfcmp: f0<>
+1e unaryfcmp: f0<
+ d unaryfcmp: f0>
+1c unaryfcmp: f0<=
+ f unaryfcmp: f0>=
+
+previous floating
+
+/f negate constant -/f
+code fint ( f -- l )
+ $f0 $f0 cvt.w .d
+ tos sp push
+ $f0 tos mfc1
+ fp 0 $f1 lwc1
+ fp 4 $f0 lwc1
+ fp /f fp addiu
+c;
+
+code float ( l -- f )
+ fp -/f fp addiu
+ $f1 fp 0 swc1
+ $f0 fp 4 swc1
+ $f0 tos mtc1
+ sp tos pop
+ $f0 $f0 cvt.d .w
+c;
+code f! ( f adr -- )
+ $f1 tos 0 swc1 \ Don't require doubleword alignment
+ $f0 tos 4 swc1
+ sp tos pop
+ fp 0 $f1 lwc1
+ fp 4 $f0 lwc1
+ fp /f fp addiu
+c;
+code f@ ( adr -- f )
+ fp -/f fp addiu
+ $f1 fp 0 swc1
+ $f0 fp 4 swc1
+ tos 0 $f1 lwc1 \ Don't require doubleword alignment
+ tos 4 $f0 lwc1
+ sp tos pop
+c;
+code fdrop ( f -- )
+ fp 0 $f1 lwc1
+ fp 4 $f0 lwc1
+ fp /f fp addiu
+c;
+code fswap ( f1 f2 -- f2 f1 )
+ fp 0 $f3 lwc1
+ fp 4 $f2 lwc1
+ bubble
+ $f1 fp 0 swc1
+ $f0 fp 4 swc1
+ $f2 $f0 movf .d
+c;
+code fover ( f1 f2 -- f1 f2 f1 )
+ fp -/f fp addiu
+ $f1 fp 0 swc1
+ $f0 fp 4 swc1
+ fp /f $f1 lwc1
+ fp /f 4 + $f0 lwc1
+c;
+code fdup ( f -- f f )
+ fp -/f fp addiu
+ $f1 fp 0 swc1
+ $f0 fp 4 swc1
+c;
+code frot ( f1 f2 f3 -- f2 f3 f1 )
+ fp 0 $f3 lwc1
+ fp 4 $f2 lwc1
+ $f1 fp 0 swc1
+ $f0 fp 4 swc1
+ fp /f $f1 lwc1
+ fp /f 4 + $f0 lwc1
+ $f3 fp /f swc1
+ $f2 fp /f 4 + swc1
+c;
+code fpick ( n -- ; F: fn ... f0 -- fn ... f0 fn )
+ fp -/f fp addiu \ Make space on stack
+ $f1 fp 0 swc1
+ tos $0 <> if
+ $f0 fp 4 swc1 \ Delay slot; push top of stack to memory
+ tos 3 tos sll \ Index into floating point stack
+ fp tos tos addu
+ tos 0 $f1 lwc1 \ Get n'th item from floating point stack
+ tos 4 $f0 lwc1
+ then
+ sp tos pop
+c;
+
+code fpop ( f -- l l )
+ tos sp push
+ sp -4 sp addiu
+ $f0 sp 0 swc1
+ $f1 tos mfc1
+ fp 0 $f1 lwc1
+ fp 4 $f0 lwc1
+ fp /f fp addiu
+c;
+code fpush ( l l -- f )
+ fp -/f fp addiu
+ $f1 fp 0 swc1
+ $f0 fp 4 swc1
+ $f1 tos mtc1
+ sp 0 $f0 lwc1
+ sp 4 tos lw
+ sp 8 sp addiu
+c;
+
+: fvariable ( -- ) create /f allot ;
+: fconstant ( fp -- )
+ create here /f allot f!
+ does> f@
+;
+: ifconstant ( fp-on-p-stack -- )
+ create here /f allot dup >r l! r> /l + l!
+ does> f@
+;
+00000000 3ff00000 ifconstant 1E0
+00000000 3fe00000 ifconstant .5E0
+
+\ XXX We really should round to nearest or even.
+: fix ( -- ) .5E0 f+ fint ;
+
+code (flit) ( -- fp )
+ fp -/f fp addiu
+ $f1 fp 0 swc1
+ $f0 fp 4 swc1
+ ip 0 $f1 lwc1
+ ip 4 $f0 lwc1
+ ip /f ip addiu
+c;
+
+
+: fliteral ( fp -- ) compile (flit) here /f allot f! ; immediate
+
+code 10**i ( i -- fp ) \ Raise 10 to the i'th power
+
+ \ if i < 0, we compute 10**|i|, then take the reciprocal
+
+ fp -/f fp addiu \ Prepare to push the floating number
+ $f1 fp 0 swc1
+ $f0 fp 4 swc1
+
+ 1 t0 li
+ $f0 t0 mtc1
+ d# 10 t0 li \ (Load delay)
+ $f0 $f0 cvt.d .w \ 1E0 in $f0
+
+ $f2 t0 mtc1
+ bubble
+ $f2 $f2 cvt.d .w \ 10E0 in $f2
+
+ \ Set scr to the absolute value of i
+
+ tos 0< if
+ tos t0 move \ t0 = i
+ $0 tos t0 subu \ t0 = -i
+ then
+
+ tos $0 <> if \ Leave answer at 1 if i=0
+ nop
+ begin
+ $f0 $f2 $f0 mulf .d \ Multiply current result by 10
+ t0 -1 t0 addiu
+ t0 $0 = until
+ nop
+ then
+
+ \ If the exponent is negative, compute the reciprocal
+ tos 0< if \ Save i for its sign
+ 1 t0 li
+ $f2 t0 mtc1
+ $f2 $f2 cvt.d .w \ 1E0 in $f2
+ $f2 $f0 $f0 divf .d \ Take the reciprocal
+ then
+
+ sp tos pop \ Fix data stack
+c;
+
+: >f ( l -- fscaled )
+ float dpl @ 0> if dpl @ 10**i f/ then
+;
+
+\ Kludge, kludge
+\ Example: 1.3 E 4 puts the floating point number 13000 on the float stack
+\ Works inside of colon definitions too.
+: E \ exponent ( l -- fscaled )
+ state @
+ if \ If we're compiling, we have to grab the number from the code stream
+ here /l - /token - token@
+ ['] (llit) =
+ if here /l - l@ /l /token + negate allot
+ else ." E must be preceded by a number containing a decimal point"
+ cr abort
+ then
+ then
+ >f bl word number 10**i f*
+ state @ if [compile] fliteral then
+; immediate
+
+forth definitions
+: (cold-hook ( -- ) (cold-hook finit ;
+' (cold-hook is cold-hook
+only forth floating also forth also definitions
+
+decimal
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/forthint.fth
===================================================================
--- cpu/mips/forthint.fth (rev 0)
+++ cpu/mips/forthint.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,338 @@
+purpose: Low-level handler for alarm interrupt
+\ See license at end of file
+
+headerless
+
+\ Interfaces to system-dependent routines
+defer set-tick-limit ( #msecs -- ) \ Setup tick interrupt source
+defer init-dispatcher ( -- )
+defer dispatch-interrupt ' noop to dispatch-interrupt
+defer dispatch-exceptions ( exception# -- ) ' drop to dispatch-exceptions
+
+0 value intsave
+h# 1300 d# 34 /x* + constant /intstack
+
+\ The interrupt save/stack area is laid out as follows:
+\ 0000 - register save area (size d# 34 /x*)
+\ 0110 - data stack area (size h#1100)
+\ 1210 - return stack area (size h#200)
+\ 1410 - <end>
+\
+\ The register save area, which is exported to the client program via the
+\ "tick" callback, contains the following registers, all from the interrupted
+\ context:
+\ 00 - $1
+\ ...
+\ 60 - $25
+\ 64 - $28
+\ ...
+\ 70 - $at
+\
+\ When the interrupt handler returns, the complete context is restored from
+\ the save area. The client program can cause a context switch by modifying
+\ these saved valued.
+
+hex
+
+: ?call-os ( -- ) intsave " tick" ($callback1) ;
+
+0 value ge-return-loc
+code ge-return ( -- )
+
+ \ At the first indication of a keyboard abort, we branch to the
+ \ Forth entry trap handler. We do the actual branch after we have
+ \ restored all the state, so it appears as if Forth were entered
+ \ directly from the program that was running, rather than through
+ \ the exception handler.
+
+ 0 k0 set \ Clear derived abort flag
+ 'user aborted? s0 lw \ Get abort flag
+ 1 s1 set
+ s0 s1 = if
+ nop \ delay slot
+ \ Don't abort in the middle of the terminal emulator, because
+ \ it's not reentrant.
+ 'user terminal-locked? s1 lw
+ s1 0 = if
+ nop \ delay slot
+ s0 1 s0 addi
+ s0 'user aborted? sw
+ 1 k0 set \ Set derived abort flag
+ then
+ then
+
+ \ Restore registers
+ 'user intsave k1 lw \ Address of interrupt save area
+ k1 d# 32 /x* t0 ld
+ k1 d# 33 /x* t1 ld
+ t0 mtlo t1 mthi
+
+ d# 12 t2 mfc0 \ Get status register
+ t2 d# 28 t2 srl \ Shift coprocessor status bits down
+ t2 h# 02 t2 andi \ Mask bit 1 (coprocessor 1 - Floating point)
+ t2 $0 <> if \ Skip if coprocessor disabled
+ nop \ Delay
+ k1 d# 34 /x* t2 ld
+ d# 31 t2 ctc1
+ then
+
+ d# 25 0 do
+ k1 i /x* ( offset ) $0 1+ i + ( reg# ) ld
+ loop
+ 4 0 do
+ k1 i d# 25 + /x* ( offset ) $0 d# 28 + i + ( reg# ) ld
+ loop
+
+ \ Now the registers are back to the state that existed upon entry to
+ \ the exception handler. We can use only k0 and k1 in the following code.
+
+ k0 0 = if
+ nop \ delay slot
+ eret \ Return to interrupted code
+ nop
+ then
+
+ here origin- to ge-return-loc
+ 1.0001 k1 set \ will be save-state address (force 2 instructions)
+ -1 k0 set
+ k1 jr \ Jump to save-state
+ nop
+
+end-code
+
+\ We implement this in the following way, instead of just having
+\ a value named getmsecs, so that other tasks can use get-msecs
+\ This way is faster too, since the "+!" in the interrupt handler
+\ routine is faster than "to".
+variable msec-counter
+[ifdef] local
+: getmsecs ( -- n ) main-task msec-counter local @ ;
+[else]
+: getmsecs ( -- n ) msec-counter @ ;
+[then]
+
+0 value tick-increment
+
+: intr-timer ( -- )
+ ms/tick msec-counter +!
+ check-alarm
+ count@ tick-increment + compare!
+;
+
+string-array exception-code
+," Interrupt"
+," TLB modified exception"
+," TLB exception (load or instruction fetch)"
+," TLB exception (store)"
+," Address error exception (load or instruction fetch)"
+," Address error exception (store)"
+," Bus error exception (instuction fetch)"
+," Bus error exception (data reference: load or store)"
+," system call exception"
+," Breakpoint exception"
+," Reserved instruction exception"
+," Coprocessor unusable exception"
+," Arithmetic overflow exception"
+," Trap exception"
+," Undefined exception"
+," Floating point exception"
+," " ," " ," " ," " ," " ," " ," "
+," Reference to WatchHi/WatchLo address"
+," " ," " ," " ," " ," " ," " ," " ," "
+end-string-array
+
+: (.exception) ( exception-code -- )
+ dup exception-code
+ dup c@ if nip ". else drop ." Unknown exception " .x then
+ cr
+;
+' (.exception) to dispatch-exceptions
+
+defer intr-sw0 ' noop to intr-sw0
+defer intr-sw1 ' noop to intr-sw1
+defer intr-hw0 ' noop to intr-hw0
+defer intr-hw1 ' noop to intr-hw1
+defer intr-hw2 ' noop to intr-hw2
+defer intr-hw3 ' noop to intr-hw3
+defer intr-hw4 ' noop to intr-hw4
+
+: dispatch-interrupts ( -- )
+ cause@ 8 >> h# ff and
+ dup h# 1 and if intr-sw0 cause@ h# ffff.feff and cause! then
+ dup h# 2 and if intr-sw1 cause@ h# ffff.fdff and cause! then
+ dup h# 4 and if intr-hw0 then
+ dup h# 8 and if intr-hw1 then
+ dup h# 10 and if intr-hw2 then
+ dup h# 20 and if intr-hw3 then
+ dup h# 40 and if intr-hw4 then
+ h# 80 and if intr-timer then
+;
+
+defer ge-handler-hook ' noop to ge-handler-hook
+: ge-handler ( -- )
+ ge-handler-hook
+ cause@ 2 >> h# 1f and ?dup if
+ dispatch-exceptions
+ else
+ dispatch-interrupts
+ then
+ ge-return
+;
+
+0 value ge-preamble-loc
+label ge-preamble ( -- )
+
+ \ If breakpoint exception, transfer control to save-state immediately.
+ d# 13 k1 mfc0 \ Get CAUSE
+ k1 h# 7c k1 andi \ Get exception code
+ 9 2 << k0 set \ Breakpoint exception
+ k0 k1 = if
+ nop
+ here origin- to ge-preamble-loc
+ 1.0001 k1 set \ will be save-state address (force 2 instructions)
+ 3 k0 set
+ k1 jr \ Jump to save-state
+ nop
+ then
+
+ \ Find address of interrupt save area
+ ra k0 move \ Save ra
+ here 8 + bal \ ra = Absolute address of next instruction
+ here origin - 4 + k1 set \ k1 = relative address of this instruction
+ ra k1 k1 subu \ k1 address of Forth kernel
+ k0 ra move \ Restore ra
+
+ 'body main-task k0 set \ User pointer address: main-task
+ k1 k0 k0 addu
+ k0 0 k0 lw
+ k0 'user# intsave k0 addiu \ User pointer
+ k0 0 k0 lw \ Address of interrupt save area
+
+ \ Save registers
+ d# 25 0 do
+ $0 1+ i + ( reg# ) k0 i /x* ( offset ) sd
+ loop
+ 4 0 do
+ $0 d# 28 + i + ( reg#) k0 i d# 25 + /x* ( offset ) sd
+ loop
+ t0 mflo t1 mfhi
+
+ d# 12 t2 mfc0 \ Get status register
+ t2 d# 28 t2 srl \ Shift coprocessor status bits down
+ t2 h# 02 t2 andi \ Mask bit 1 (coprocessor 1 - Floating point)
+ t2 $0 <> if \ Skip if coprocessor disabled
+ nop \ Delay
+ d# 31 t2 cfc1
+ then
+
+ t0 k0 d# 32 /x* sd
+ t1 k0 d# 33 /x* sd
+ t2 k0 d# 34 /x* sd
+
+ \ Set up Forth stacks
+ k0 /intstack rp addiu \ Return stack pointer
+ rp h# -204 sp addi \ Data stack pointer
+
+ k1 base move
+ 'body main-task up set
+ base up up addu
+ up 0 up lw
+
+ np@ origin- np set
+ np base np addu
+
+ 'body ge-handler ip set
+ ip base ip addu
+c;
+
+: set-tick-limit ( #msecs -- )
+ dup to ms/tick
+ ms-factor * dup to tick-increment
+ count@ + compare!
+ sr@ h# 8000 or sr!
+;
+
+: (Disable-interrupts) ( -- ) sr@ h# ffff.fffe and sr! ;
+' (disable-interrupts) to disable-interrupts
+: (enable-interrupts) ( -- ) sr@ 1 or sr! ;
+' (enable-interrupts) to enable-interrupts
+
+label default-handler
+ begin again nop
+end-code
+
+code clear-floating-point ( -- )
+ d# 12 t0 mfc0 \ Get status register
+ t0 d# 28 t0 srl \ Shift coprocessor status bits down
+ t0 h# 02 t0 andi \ Mask bit 1 (coprocessor 1 - Floating point)
+ t0 $0 <> if \ Skip if coprocessor disabled
+ nop \ Delay
+ d# 31 $0 ctc1 \ Clear floating point if it's enabled
+ then
+c;
+
+defer tlb-handler ' default-handler to tlb-handler
+defer xtlb-handler ' default-handler to xtlb-handler
+defer cache-handler ' default-handler to cache-handler
+" Implement TLB and cache error handlers" ?reminder
+: catch-exceptions ( -- )
+ [ also hidden ]
+ tlb-handler 0 install-handler
+ xtlb-handler 1 install-handler
+ cache-handler 2 install-handler
+ ge-preamble 3 install-handler \ General exception
+
+ \ Interrupts can come in on either vector 3 (offset h#180) or vector 4
+ \ (offset h#200), depending on the setting of the IV bit (bit 23) in the
+ \ CP0 Cause register. If that bit is clear, interrupts share vector 3
+ \ with exceptions. If that bit is set, exceptions use vector 3 and
+ \ interrupts use vector 4. We wish to operate correctly with either
+ \ setting, so we install the same handler at both locations.
+ ge-preamble 4 install-handler \ Interrupt
+
+ sr@ h# 40.0000 invert and sr! \ BEV = normal
+ [ previous ]
+;
+: install-alarm ( -- )
+ ['] getmsecs to get-msecs
+ /intstack alloc-mem to intsave
+ intsave /intstack erase \ Paranoia
+ disable-interrupts
+ init-dispatcher
+ clear-floating-point
+ catch-exceptions
+ d# 1 set-tick-limit
+ enable-interrupts \ Turn interrupts on
+;
+
+stand-init: Fixup ge-preamble and ge-return
+ \ Fix up save-state in interrupt-return
+ save-state ge-return-loc origin+ fix-set32
+ save-state ge-preamble-loc origin+ fix-set32
+;
+
+headers
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/ftrace.fth
===================================================================
--- cpu/mips/ftrace.fth (rev 0)
+++ cpu/mips/ftrace.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,41 @@
+purpose: Display a Forth stack backtrace for MIPS
+\ See license at end of file
+
+: .stack ( -- ) \ Forth data stack
+ ." Data stack: "
+ $sp sp0 @ dup ps-size - swap /n - within if
+ $sp sp0 @ /n - do i >saved @ .x /n negate +loop
+ then
+ cr
+;
+only forth also hidden also forth definitions
+: ftrace ( -- ) \ Forth return stack
+ $ip >saved .traceline
+ $rp >saved rssave-end swap (rstrace
+ cr .stack
+;
+only forth also definitions
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/getms.fth
===================================================================
--- cpu/mips/getms.fth (rev 0)
+++ cpu/mips/getms.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,104 @@
+purpose: Interval timing functions
+\ See license at end of file
+
+headerless
+
+: ticks-enabled? ( -- flag ) sr@ h# 8001 tuck and = ;
+
+0 value tick-msecs
+: (get-msecs) ( -- n ) tick-msecs ;
+' (get-msecs) to get-msecs
+
+d# 10 value ms/tick
+d# 50,000 constant ms-factor
+d# 50 value us-factor
+
+: ticks ( #ticks -- )
+ count@ + ( target )
+
+ \ We use "- 0<" instead of "<" so that the right thing will happen
+ \ when the tick count wraps around.
+ \ We use "0<" instead of "0<=" so that we are sure to wait at least
+ \ the requested time; otherwise we might not wait long enough if the
+ \ first call to get-msecs were to occur just before the timer ticked.
+ begin dup count@ - 0<= until \ Loop until target time reached
+ drop ( )
+;
+: us ( #microseconds -- ) us-factor * ticks ;
+
+: (ms) ( #ms -- )
+ dup ms/tick 3 * u> ticks-enabled? and if ( #ms )
+ \ For relatively long durations, we use the ticker because it is
+ \ presumed to be reasonably accurate over the long run. However,
+ \ if interrupts are not enabled, we can't use the ticker because
+ \ it won't be ticking.
+
+ get-msecs + ( target )
+
+ \ We use "- 0<" instead of "<" so that the right thing will happen
+ \ when the tick count wraps around.
+ \ We use "0<" instead of "0<=" so that we are sure to wait at least
+ \ the requested time; otherwise we might not wait long enough if the
+ \ first call to get-msecs were to occur just before the timer ticked.
+ begin dup get-msecs - 0<= until \ Loop until target time reached
+
+ drop ( )
+ else ( #ms )
+ \ For relatively short durations, we use a timing loop because
+ \ the ticker probably has rather coarse granularity.
+
+ ms-factor * ticks
+ then
+;
+' (ms) to ms
+
+" calibrate ticker in cpu/mips/getms.fth" ?reminder
+
+d# 33,333,333 constant cpu-clock-speed
+
+\ The way to do this is to determine the internal clock frequency
+\ by multiplying 33.3 MHz by the multiplier value derived from the
+\ CP0 config register, then dividing by two to get the number of ticks
+\ per second, from which us-factor and ms-factor can be derived.
+: calibrate-ticker ( -- )
+ cpu-clock-speed ( bus-clock-Hz )
+ config@ d# 28 rshift 7 and case
+ 0 of 2 * endof \ 2:1
+ 1 of 3 * endof \ 3:1
+ 2 of 4 * endof \ 4:1
+ 6 of endof \ 1:1
+ 7 of 3 * 2 / endof \ 3:2
+ endcase ( processor-clock-Hz )
+ 1+ 2/ ( count-Hz )
+ d# 1000 / dup to ms-factor ( ms-counts )
+ d# 1000 / to us-factor
+;
+
+headers
+stand-init: Calibrate
+ calibrate-ticker
+;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/initpgm.fth
===================================================================
--- cpu/mips/initpgm.fth (rev 0)
+++ cpu/mips/initpgm.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,43 @@
+purpose: Generic tools for load image handlers
+\ See license at end of file
+
+: (init-program) ( pc sp -- )
+ clear-save-area state-valid on
+ sr@ to $sr
+
+ \ PowerPC calling conventions store the link register at SP+8,
+ \ so we start with r1 a little below the top of the allocated region
+ to $sp to $pc
+ cif-handler to $a3
+
+ restartable? on
+ true to already-go?
+;
+
+: +base ( n -- adr ) load-base + ;
+
+headers
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/installation.html
===================================================================
--- cpu/mips/installation.html (rev 0)
+++ cpu/mips/installation.html 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,117 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+ <title>MIPS Getting Started</title>
+ <meta http-equiv="content-type"
+ content="text/html; charset=ISO-8859-1">
+ <meta name="author" content="Mitch Bradley">
+</head>
+<body>
+<h2 align="center">MIPS Open Firmware</h2>
+<h2 align="center">Getting Started</h2>
+<h3>Unpacking the Files</h3>
+<ul>
+ <li>Login to the Linux MIPS machine that you will use for your Open Firmware
+compilations.<br>
+ </li>
+ <li>Create a directory on that machine for the Open Firmware build tree.
+ It can be on either a local disk or a mounted network filesystem. A
+mounted filesystem may be better in the long run if you expect to use the
+same tree for other processor architectures later. Example: <b>mkdir
+/home/wmb/ofw</b></li>
+ <li>Set the BP environment variable to that directory. Example: <b>export
+BP=/home/wmb/ofw</b></li>
+ <li>Enter that directory:<b> cd $BP</b></li>
+ <li>Extract the files: <b>tar xf mips-ofw.tar.gz</b></li>
+ <li>If you use CVS or a similar version control system, checkin the
+tree.</li>
+</ul>
+<h3>Creating platform directories</h3>
+Builds are done in a directory named $BP/cpu/mips/<i><b>chipset/platform</b></i>/build/
+.<br>
+<br>
+<i><b>chipset </b></i>is a name that identifies the core logic chipset for
+your system. Source files in that directory contain code that is common
+to all systems built with that chipset. In some cases, the source distribution
+will already include a suitable <i>chipset </i>directory for your chipset,
+e.g. $BP/cpu/mips/emma2/.<br>
+<ul>
+ <li>If a suitable chipset directory does not exist, create one. Example:
+ <b>mkdir $BP/arch/mips/mychip</b></li>
+</ul>
+<i><b>platform</b></i> is a name that you choose to identify your system.
+You need a separate <i>platform</i> directory for each distinct Open Firmware
+binary image. Typically you would have a different platform directory for
+each of your different boards. Source files in that directory contain code
+that is board-specific. For example, different boards often have different
+external I/O devices, so the builder script files in the various <i>platform</i>
+directories would load different I/O drivers. It is possible to support
+several boards from a single Open Firmware binary image if the board differences
+can be detected at run time. There is a tradeoff between the difficulty of
+maintaining several different images versus the trouble of testing new combined
+images on all platforms.
+<ul>
+ <li>Create one or more platform directories. Example: <b>mkdir $BP/cpu/mips/mychip/myboard</b>
+ </li>
+</ul>
+The builder puts object files in a "build" subdirectory beneath the <i>platform</i>
+directory. Typically the build directory contains no source files.<br>
+<ul>
+ <li>Create a build directory below each platform directory. Example: <b>mkdir
+$BP/cpu/mips/mychip/myboard/build</b></li>
+</ul>
+<h3>Compilation tools</h3>
+The Open Firmware compilation process uses the following tools:
+<dl>
+ <dd><b>build</b> is the main command for Open Firmware compilation. It
+is a simple shell script that you install (per the above) in a directory
+on your search path. The script's purpose is to set some environment variable
+and then to locate and execute the appropriate executable files for the particular
+host system.</dd>
+ <dd><b>forth</b> is the executable program that <b>build </b>invokes. It
+resides in $BP/bin/<i>cpu</i>/<i>os</i>/forth, where <i>cpu </i>and <i>os</i>
+are the host instruction set (e.g. mips) and operating system (e.g. linux)
+on which it executes.</dd>
+ <dd><b>native.dic</b> is the Open Firmware compiler. It resides in $BP/bin/<i>cpu</i>/native.dic
+. native.dic is a Forth dictionary file that includes all the tools necessary
+for the compilation process, including a Forth metacompiler, a Forth incremental
+compiler, an assembler, an FCode tokenizer, an FCode detokenizer, a dependency
+manager (the "builder"), and a dropin manager (tools for creating sequences
+of dropin modules to form a ROM image file). It can also be extended
+with tools to create specific download file formats.</dd>
+</dl>
+<h3>Compiling "forth" the first time</h3>
+The <b>forth </b>executable is actually just a collection of I/O interface
+procedures that provide the "glue" to let native.dic work on a particular
+operating system. The forth executable is the only part of the system that
+must be compiled with external tools. It is written in C, and may be compiled
+by various C compilers; typically gcc on a Unix system (but it doesn't use
+any GCC-specific extensions). After it has been compiled once, it does not
+need to be compiled again unless you change the host operating system in a
+way that breaks older binaries or shared libraries.<br>
+<br>
+To find out if you need to recompile the "forth" executable for your system,
+do this (on the MIPS Linux development system):<br>
+<blockquote>
+ <pre>cd $BP/bin/mips/linux<br>./forth ../native.dic</pre>
+</blockquote>
+You should see a banner like this:<br>
+<blockquote>
+ <pre>Forthmacs version 4.0<br>Copyright (c) 1994 FirmWorks All Rights Reserved<br>ok <br></pre>
+</blockquote>
+To exit, type <b>bye</b> .<br>
+<br>
+If the above doesn't work, type:<br>
+<blockquote>
+ <pre>make forth</pre>
+</blockquote>
+and try again.
+<h3>Porting to your platform</h3>
+<br>
+<br>
+<br>
+<br>
+<br>
+<br>
+</body>
+</html>
Added: cpu/mips/intctl.fth
===================================================================
--- cpu/mips/intctl.fth (rev 0)
+++ cpu/mips/intctl.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,56 @@
+purpose: Device node for MIPS R4000 internal interrupt controller
+\ See license at end of file
+
+" interrupt-controller" device-name
+my-address my-space h# 20 reg
+
+0 value pic-base
+
+: >mask ( bit# -- mask ) 1 swap lshift ;
+: this-interrupt ( -- irq# )
+ cause@ 8 rshift h# ff and ( mask )
+ 8 0 do dup i >mask and if drop i true unloop exit then loop ( mask )
+ drop false
+;
+: interrupt-mask@ ( -- mask ) sr@ 8 rshift h# ff and ;
+: interrupt-mask! ( mask -- ) 8 lshift sr@ h# ff00 invert and or sr! ;
+: enable-irq ( irq# -- )
+ >mask interrupt-mask@ or interrupt-mask!
+;
+: disable-irq ( irq# -- )
+ >mask interrupt-mask@ swap invert and interrupt-mask!
+;
+: clear-interrupt ( irq# -- ) 1 swap lshift 1 pic-base >offset rb! ;
+: open ( -- flag )
+ pic-base 0= if
+ my-address my-space h# 38 " map-in" $call-parent to pic-base
+ \ 0 interrupt-mask!
+ then
+ pic-base 0<>
+;
+: slot-vector@ ( slot# -- vector ) pic-base >offset rb@ ;
+: close ( -- ) ;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/irq.fth
===================================================================
--- cpu/mips/irq.fth (rev 0)
+++ cpu/mips/irq.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,56 @@
+purpose: Interrupt dispatcher using MIPS R4000 internal interrupt controller
+\ See license at end of file
+
+8 constant #irqs
+
+0 value pic-node
+: enable-interrupt ( level -- ) " enable-irq" pic-node $call-method ;
+: disable-interrupt ( level -- ) " disable-irq" pic-node $call-method ;
+
+: stray-interrupt ( level -- )
+ ." Unexpected interrupt on IRQ" dup .d cr
+ disable-interrupt \ To prevent recurrence
+;
+
+#irqs /n* buffer: interrupt-handlers
+: interrupt-handler! ( xt int-level -- ) interrupt-handlers swap na+ ! ;
+: interrupt-handler@ ( int-level -- xt ) interrupt-handlers swap na+ @ ;
+
+: (dispatch-interrupt) ( -- )
+ " this-interrupt" pic-node $call-method if ( level )
+ dup interrupt-handlers over na+ @ execute ( level )
+ " clear-interrupt" pic-node $call-method ( )
+ then ( )
+;
+: (init-dispatcher) ( -- )
+ pic-node 0= if
+ " /interrupt-controller" open-dev to pic-node
+ #irqs 0 do ['] stray-interrupt i interrupt-handler! loop
+ ['] (dispatch-interrupt) to dispatch-interrupt
+ then
+;
+' (init-dispatcher) to init-dispatcher
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/kernboot.fth
===================================================================
--- cpu/mips/kernboot.fth (rev 0)
+++ cpu/mips/kernboot.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,203 @@
+purpose: Startup code for running under the C wrapper
+\ See license at end of file
+
+\ Version for running Forth as a Unix user process
+
+\ Boot code (cold start). The cold start code is executed
+\ when Forth is initially started. Its job is to initialize the Forth
+\ virtual machine registers.
+
+hex
+
+only forth also labels also meta also definitions
+
+0 constant main-task
+: init-user (s -- ) ;
+
+headerless
+
+\ Stuff initialized at cold start time
+
+nuser memtop \ The top of the memory used by Forth
+0 value #args \ The process's argument count
+0 value args \ The process's argument list
+
+: process-command-line ( -- ) ;
+
+\ This code gets control shortly after Forth is first called from the
+\ C wrapper program (the executable file "forth"). At the beginning
+\ of the Forth dictionary, there is a branch instruction that branches
+\ to the following code.
+
+label cold-code ( -- )
+here-t cld 8 + branch!
+\ called with forth_startup(header-adr, functions, mem_end, &gargc, &gargv)
+\ a0 a1 a2 a3 a4
+
+ sp 10 t8 lw \ &gargv
+
+\ Get a fresh set of local registers.
+ sp 8 /n* negate sp addiu \ Make room on stack
+ s0 sp 0 sw \ Save registers
+ s1 sp 4 sw
+ s2 sp 8 sw
+ s3 sp c sw
+ s4 sp 10 sw
+ s5 sp 14 sw
+ s6 sp 18 sw
+ s7 sp 1c sw
+
+\ Allocate high memory for the stacks and stuff, starting at memtop and
+\ allocating downwards. a2 contains the "mem_end" argument passed in
+\ from C; we use it as an the allocation pointer.
+
+ $a2 t6 move \ We'll need this value later for memtop
+
+\ Find the user area size from the header. a0 contains the "header-adr"
+\ argument passed in from C.
+
+ $a0 8 t4 lw \ Data size = user area size in t4
+ bubble
+
+\ Allocate the RAM copy of the User Area
+
+ $a2 t4 $a2 subu \ Allocate the bytes
+ $a2 up move \ Set user pointer
+
+ $a0 20 base addiu \ Base address of image
+
+ 'body main-task t5 li \ Allow the exception handler to find the
+ t5 base t5 addu \ user area by storing the address of the
+ up t5 0 sw \ main user area in the "constant" main-task
+
+\ Copy the initial User Area image to the RAM copy
+ $a0 4 t3 lw \ Text size = offset to start of data
+ up t7 move \ Destination pointer (load delay)
+ t3 base t3 addu \ Relocate Init-up pointer in t3
+ t3 t4 t4 addu \ t4 = source limit
+
+ begin
+ t3 0 t5 lw \ Read a longword
+ t3 4 t3 addiu \ (load delay) Increment src
+ t5 t7 0 sw \ Write a longword
+ t3 t4 = until \ Loop until limit is reached
+ t7 4 t7 addiu \ Increment destination (delay slot)
+
+\ Now the user area has been copied to the proper place, so we can set
+\ some important user variables whose inital values are determined at
+\ run time.
+
+\ Little-endian flag
+ $a0 0 t0 lb \ Get first byte of header
+ h# 10 t1 li \ Most significant byte of "branch" instruction
+ t0 t1 <> if
+ $0 t0 move \ Delay - set flag to 0 (big-endian)
+ $0 -1 t0 addiu \ Set flag to -1 (little-endian)
+ then
+ t0 'user in-little-endian? sw
+
+\ Top of memory and dictionary limit
+ t6 'user memtop sw \ t6 contains the mem_end value saved above
+
+\ Set the up0 user variable
+ up 'user up0 sw
+
+\ Establish the return stack and set the rp0 user variable
+ $a2 rp move \ Set rp register
+ rp 'user rp0 sw \ Save in rp0 user variable
+ $a2 rs-size-t negate $a2 addiu \ allocate space for the return stack
+
+\ Establish the Parameter Stack
+ $a2 20 negate $a2 addiu \ Guard band between Parameter Stack and TIB
+ $a2 'user sp0 sw \ Store initial stack pointer in sp0 user var.
+ $a2 /n sp addi \ /n accounts for the top of stack register
+
+ $a2 ps-size-t negate $a2 addiu \ Allocate space for the stack
+
+ t6 $a2 $at sltu
+ $at $0 <> if nop
+ t6 $a2 move
+ then
+ $a2 'user limit sw \ Set the dictionary limit value
+
+
+\ Save the address of the system call table in the user variable syscall-vec
+\ $a1 constains the value of the "functions" argument passed in from C.
+ $a1 up syscall-user# sw
+
+\ Set the dictionary pointer; $a0 is the header address
+ $a0 4 t0 lw \ Text size field from header
+ bubble
+ t0 base t0 add \ Base + text_size = text_end_adr
+
+\ $a0 8 t1 lw \ Data size field from header
+\ t0 t1 t0 add \ preserve ua init area so restart is faster
+
+ t0 'user dp sw \ Set dp
+
+ $a3 'user #args sw \ Set argc and argv
+ t8 'user args sw
+
+ (next) np li
+ np base np addu \ Set NEXT pointer
+
+\ Enter Forth
+ 'body cold ip li \ Relative address of "cold" Forth word
+ ip base ip addu \ Relocate it to an absolute address
+
+c; \ c; automatically assembles "next"
+ \ so this enters Forth executing "cold"
+
+0 [if]
+: warm ( -- ) ." Warm start" cr quit ;
+
+label warm-code ( -- )
+
+ here-t 8 + $0 bgezal
+ nop
+ here-t base li \ Offset to here
+ ra base base subu \ base: Absolute address of origin
+
+ 'body main-task up li \ Find the user area
+ up base up add
+ up 0 up lw
+
+ 'user rp0 rp lw \ Set the return stack pointer
+ 'user sp0 sp lw \ Set the data stack pointer
+ sp /n sp addi \ /n accounts for the top of stack register
+
+ (next) np li
+ np base np addu \ Set NEXT pointer
+
+\ Enter Forth
+ 'body warm ip li \ Relative address of "cold" Forth word
+ ip base ip addu \ Relocate it to an absolute address
+
+c; \ c; automatically assembles "next"
+ \ so this enters Forth executing "warm"
+[then]
+headers
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/kerncode.fth
===================================================================
--- cpu/mips/kerncode.fth (rev 0)
+++ cpu/mips/kerncode.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,1539 @@
+purpose: MIPS kernel code words
+\ See license at end of file
+
+\ TODO - put I in a register
+
+meta
+hex
+
+\ Allocate and clear the initial user area image
+\ mlabel init-user-area
+
+setup-user-area
+
+only forth also labels also meta assembler also definitions
+
+\ Forth Virtual Machine registers
+
+\ Global Registers
+
+\ Note that the Forth Stack Pointer (r1) is NOT the same register that
+\ C uses for the stack pointer (r14). The hardware does all sorts of
+\ funny things with the C stack pointer when you do save and restore
+\ instructions, and when the register windows overflow.
+
+: np s1 ; : base s2 ; : up s3 ; : tos s4 ; : ip s5 ; : rp s6 ; : sp $sp ;
+
+: w t0 ;
+
+\ Macros:
+
+\ Parameter Field Address
+: apf ( -- ) w 4 ;
+
+: bubble ( -- ) nop ;
+: bubble ;
+
+: get ( ptr dst -- ) 0 swap lw ;
+: put ( src ptr -- ) 0 sw ;
+: move ( src dst -- ) 0 swap addu ;
+: ainc ( ptr -- ) dup 4 swap addiu ;
+: adec ( ptr -- ) dup -4 swap addiu ;
+: push ( src ptr -- ) dup adec put ;
+: pop ( ptr dst -- ) over -rot get ainc ;
+
+: cmp ( src dst -- ) $at subu ;
+: cmpi ( src imm -- ) negate $at addiu ;
+\ NOTE brif ( target-adr condition -- ) $at make-branch ;
+
+\ Take a high-level branch
+: take-branch (s -- )
+ ip 0 t0 lw
+ bubble
+ ip t0 ip addu
+;
+: skip-branch ( -- )
+ ip /branch ip addiu
+;
+
+only forth also labels also meta also assembler definitions
+
+:-h /n* /n * ;-h
+
+\ We create the shared code for the "next" routine so that:
+\ a) It will be in RAM for speed (ROM is often slow)
+\ b) We can use the user pointer as its base address, for quick jumping
+
+[ifdef] put-next-in-user-area
+also forth
+compilation-base here-t \ Save meta dictionary pointer
+0 dp-t ! userarea-t is compilation-base \ Point it to user area
+previous
+[then]
+
+mlabel (next) \ Shared code for next; will be copied into user area
+ ip 0 w lw \ Read the token at the ip location
+ bubble
+ w base w addu \ Relocate
+ w 0 t1 lw \ Read the contents of the code field
+ bubble
+ t1 base t1 addu \ Relocate
+ t1 jr \ Jump to the code
+ ip /token-t ip addiu \ Advance ip to point to the next token
+end-code
+
+[ifdef] put-next-in-user-area
+also forth
+dp-t ! is compilation-base previous \ Restore meta dict. pointer
+
+d# 32 equ #user-init \ Leaves space for the shared "next"
+[else]
+0 equ #user-init
+[then]
+
+
+hex meta assembler definitions
+\ assembler macro to assemble next
+:-h next
+ [ assembler ]-h
+ \ If it is inappropriate to move the last instruction into the
+ \ delay slot of next's "jr" instruction, insert a nop to be
+ \ moved instead.
+
+ here delay-barrier @ [ meta ]-h = if [ assembler ]-h
+ nop
+ [ meta ]-h then [ assembler ]-h
+
+ \ Move the last instruction into the delay slot of the "jr up"
+ here -1 la+ asm@ ( last-instruction ) \ Save instruction
+ /l negate asm-allot ( last-instruction ) \ Erase it
+[ifdef] put-next-in-user-area
+ up jr ( last-instruction ) \ Replace with "jr"
+[else]
+ np jr
+\ (next) h# 20 + j
+[then]
+ here /l asm-allot asm! ( ) \ Put instruction after jr
+;-h
+
+:-h c; next end-code ;-h
+
+code-field: docolon assembler
+ ip rp push \ Push the ip register on the return stack
+ apf ip addiu \ Set ip to apf of the colon definition
+c;
+
+code-field: dovariable
+ tos sp push \ Save the top-of-stack register on memory stack
+ apf tos addiu \ Put pfa in top-of-stack register
+c;
+
+code-field: dolabel
+ tos sp push \ Save the top-of-stack register on memory stack
+ apf tos addiu \ Put pfa in top-of-stack register
+c;
+
+code-field: douser
+ tos sp push \ Save the top-of-stack register on memory stack
+ apf t0 lw \ Get the user number
+ bubble
+ t0 up tos addu \ Add the base address of the user area into tos
+c;
+
+code-field: dovalue
+ tos sp push \ Save the top-of-stack register on memory stack
+ apf t0 lw \ Get the user area offset from the parameter field
+ bubble
+ up t0 t0 addu
+ t0 0 tos lw \ Get the contents of the user area location into tos
+c;
+
+code-field: dodefer
+ apf t1 lw \ Get the user area offset from the parameter field
+ bubble
+ up t1 t1 addu
+ t1 0 w lw \ Get the acf stored in that user location
+ bubble
+ w base w addu \ Relocate
+ w 0 t1 lw \ Get the contents of the code field
+ bubble
+ t1 base t1 addu \ Relocate
+ t1 jr \ Execute that word
+ nop
+end-code
+
+code-field: doconstant
+ tos sp push \ Save the top-of-stack register on memory stack
+ apf tos lw \ Get the constant's value into tos register
+c;
+
+code-field: do2constant
+ sp -8 sp addiu \ Make room on the stack
+ tos sp 4 sw \ Save the old tos on the memory stack
+ apf t1 lw \ Get the bottom constant's value
+ apf 4 + tos lw \ Get the top constant's value
+ t1 sp put \ Put bottom constant on the memory stack
+c;
+
+code-field: dodoes
+ \ The child word's code field contains a pointer to the doesclause
+ \ The doesclause's code field contains dodoes jal sp adec
+
+ tos sp push \ Prepare to push the pfa
+ apf 4 + tos addiu \ push the pfa (delay slot)
+
+ apf w lw \ Set w to acf of the definition
+
+ w base w addu \ Relocate
+ w 0 t1 lw \ Read the code field contents
+ bubble
+ t1 base t1 addu \ Relocate
+ t1 jr \ Jump to that location
+ nop
+end-code
+
+:-h code-cf ( -- ) here /token + aligned token,-t align-t ;-h
+:-h label-cf ( -- ) dolabel token,-t align-t ;-h
+:-h colon-cf ( -- ) docolon token,-t ;-h
+:-h constant-cf ( -- ) doconstant token,-t ;-h
+:-h variable-cf ( -- ) dovariable token,-t ;-h
+:-h user-cf ( -- ) douser token,-t ;-h
+:-h value-cf ( -- ) dovalue token,-t ;-h
+:-h defer-cf ( -- ) dodefer token,-t ;-h
+:-h startdoes ( -- ) colon-cf ;-h
+:-h start;code ( -- ) code-cf ;-h
+:-h create-cf ( -- ) dodoes token,-t compile-t noop ;-h
+:-h vocabulary-cf ( -- ) dodoes token,-t compile-t <vocabulary> ;-h
+
+meta definitions
+
+\ dovariable constant dovariable
+\ dodoes constant dodoes
+
+code (lit) (s -- n )
+ tos sp push
+ ip tos get
+ ip ainc
+c;
+
+\ Execute a Forth word given a code field address
+code execute (s acf -- )
+ tos w move \ Pop stack into t1
+ sp tos get \ "
+ w 0 t1 lw \ Read the contents of the code field
+ bubble
+ t1 base t1 addu \ Relocate
+ t1 jr \ Jump to the code
+ sp ainc \ Finish popping stack in delay slot
+end-code
+
+\ High level branch. The branch offset is compiled in-line.
+code branch (s -- )
+mlabel bran1
+ take-branch
+c;
+
+\ High level conditional branch.
+code ?branch (s f -- ) \ Takes the branch if the flag is false
+ tos t0 move
+ sp tos get
+ bran1 t0 $0 beq
+ sp ainc \ Delay slot
+ skip-branch
+c;
+
+\ Run time word for loop
+code (loop) (s -- )
+ rp t0 get
+ bubble
+ t0 1 t1 addiu \ Increment index
+ bran1 t1 bgez \ Result still positive; continue looping
+ t1 rp put \ Write back the loop index in the delay slot
+
+ bran1 t0 bltz \ Result negative, so check operand
+ nop \ If operand is negative too, continue looping
+
+ \ The internal "i" value went from positive to negative, so the loop ends
+ rp 3 /n* rp addiu \ remove loop params from stack
+ skip-branch
+c;
+
+\ Run time word for +loop
+code (+loop) (s increment -- )
+ rp t0 get
+ bubble
+ t0 tos t1 addu \ increment loop index
+ t1 rp put \ Write back the loop index
+ t0 tos t3 xor \ Compare operand signs
+ sp tos get \ Pop stack
+ bran1 t3 bltz \ Operand signs different
+ sp ainc \ Delay slot
+
+ t1 t0 t2 xor \ Compare result with an operand
+ bran1 t2 bgez \ Result has same sign as operand; continue looping
+ nop
+
+ \ The result sign differs from the operand signs; so the loop ends
+ rp 3 /n* rp addiu \ remove loop params from stack
+ skip-branch
+c;
+
+\ Run time word for do
+code (do) (s l i -- )
+ tos t1 move \ i in t1
+ sp t0 get \ l in t0
+ sp /n tos lw
+ sp 2 /n* sp addiu
+mlabel pd0 ( -- r: loop-end-offset l+0x8000 i-l-0x8000 )
+ ip rp push \ remember the do offset address
+ skip-branch \ Skip the do offset
+ h# 8000.0000 t2 sethi
+ t0 t2 t0 addu
+ t0 rp push
+ t1 t0 t1 subu
+ t1 rp push
+c;
+meta
+
+\ Run time word for ?do
+code (?do) (s l i -- )
+ sp t0 get \ l in t0
+ tos t1 move \ i in t1
+ sp /n tos lw
+ pd0 t1 t0 bne
+ sp 2 /n* sp addiu \ Delay slot
+ take-branch
+c;
+
+\ Loop index for current do loop
+code i (s -- n )
+ tos sp push
+ rp tos get
+ rp /n t0 lw
+ bubble
+ tos t0 tos addu
+c;
+
+\ Limit value for the enclosing do loop
+code ilimit ( -- n )
+ tos sp push
+ rp /n tos lw
+ bubble
+ h# 8000.0000 t0 sethi
+ tos t0 tos subu
+c;
+
+\ Loop index for next enclosing do loop
+code j (s -- n )
+ tos sp push
+ rp 3 /n* tos lw
+ rp 4 /n* t0 lw
+ bubble
+ tos t0 tos addu
+c;
+\ Limit value for the next enclosing do loop
+code jlimit ( -- n )
+ tos sp push
+ rp 4 /n* tos lw
+ bubble
+ h# 8000.0000 t0 sethi
+ tos t0 tos subu
+c;
+
+code (leave) (s -- )
+mlabel pleave
+ rp 2 /n* ip lw \ Get the address of the ending offset
+ rp 3 /n* rp addiu \ get rid of the loop indices
+ take-branch
+c;
+
+code (?leave) (s f -- )
+ tos t0 move
+ sp tos get
+ pleave t0 $0 bne
+ sp ainc \ Delay slot
+c;
+
+code unloop ( -- ) rp 3 /n* rp addiu c; \ Discard the loop indices
+
+code (of) ( selector test -- [ selector ] )
+ sp t0 pop \ Test in tos, Selector in t0
+ t0 tos = if
+ t0 tos move \ Delay slot - Copy selector to tos
+ sp tos pop \ Overwrite tos if selector matches
+ skip-branch
+ next
+ then
+ take-branch
+c;
+
+\ (endof) is the same as branch, and (endcase) is the same as drop,
+\ but redefining them this way makes the decompiler much easier.
+code (endof) (s -- ) take-branch c;
+code (endcase) (s n -- ) sp tos pop c;
+
+meta-base
+assembler
+mlabel dofalse
+ $0 tos move
+ next
+meta
+
+hex
+\ Convert a character to a digit according to the current base
+code digit (s char base -- digit true | char false )
+ tos t0 move \ base in t0
+ sp tos get \ char in tos
+ bubble
+ tos -30 tos addiu \ convert to number \ 30 is ascii 0
+ dofalse tos bltz \ Anything less than ascii 0 isn't a digit
+ tos a cmpi \ Delay slot - test for >= 10
+ $at 0>= if \ Try for a letter representing a digit
+ tos ascii A ascii 0 - cmpi
+ dofalse $at 0< brif \ bad if > '9' and < 'A'
+ tos ascii a ascii 0 - cmpi \ >= 'a' (delay slot)
+ $at 0>= if
+ tos ascii A ascii 0 - d# 10 - negate tos addiu \ (delay slot)
+ tos ascii a ascii A - negate tos addiu
+ then
+ then
+ tos t0 cmp \ Compare digit to base
+ dofalse $at 0>= brif \ Error if digit is bigger than base
+ nop
+ tos sp put \ Replace the char on the stack with the digit
+ $0 -1 tos addiu \ True to indicate success
+c;
+
+\ Copy cnt characters starting at from-addr to to-addr. Copying is done
+\ strictly from low to high addresses, so be careful of overlap between the
+\ two buffers.
+
+code cmove ( src dst cnt -- ) \ Copy from bottom to top
+ sp 4 t0 lw \ Src into t0
+ sp 0 t1 lw \ Dst into t1
+
+ t0 tos t2 addu \ t2 = src limit
+
+ t0 t2 <> if
+ nop
+
+ begin
+ t0 0 t3 lbu \ Load byte
+ t0 1 t0 addiu \ (load delay) Increment src
+ t3 t1 0 sb \ Store byte
+ t0 t2 = until
+ t1 1 t1 addiu \ (delay) Increment dst
+
+ then
+
+ sp 8 tos lw \ Delay slot - Reload tos
+ sp 3 /n* sp addiu \ "
+c;
+
+code cmove> ( src dst cnt -- ) \ Copy from top to bottom
+ sp 4 t0 lw \ Src into t0
+ sp 0 t1 lw \ Dst into t1
+
+ t0 tos t2 addu \ Top of src area
+ t1 tos t1 addu \ Top of dst area
+
+ t0 t2 <> if \ Don't do anything if the count is 0.
+ nop
+
+ begin
+ t2 -1 t3 lbu \ Load byte
+ t2 -1 t2 addiu \ (load delay) Decrement src
+ t3 t1 -1 sb \ Store byte
+ t0 t2 = until
+ t1 -1 t1 addiu \ (delay) Decrement dst
+
+ then
+
+ sp 8 tos lw \ Delete 3 stack items
+ sp 3 /n* sp addiu \ "
+c;
+
+code and (s n1 n2 -- n3 ) sp t0 pop tos t0 tos and c;
+code or (s n1 n2 -- n3 ) sp t0 pop tos t0 tos or c;
+code xor (s n1 n2 -- n3 ) sp t0 pop tos t0 tos xor c;
+code invert (s n1 -- n2 ) $0 tos tos subu tos -1 tos addiu c;
+
+code lshift (s n1 cnt -- n2 ) sp t0 pop t0 tos tos sllv c;
+code rshift (s n1 cnt -- n2 ) sp t0 pop t0 tos tos srlv c;
+code << (s n1 cnt -- n2 ) sp t0 pop t0 tos tos sllv c;
+code >> (s n1 cnt -- n2 ) sp t0 pop t0 tos tos srlv c;
+code >>a (s n1 cnt -- n2 ) sp t0 pop t0 tos tos srav c;
+
+code + (s n1 n2 -- n3 ) sp t0 pop tos t0 tos addu c;
+code - (s n1 n2 -- n3 ) sp t0 pop t0 tos tos subu c;
+code negate (s n1 -- n2 ) $0 tos tos subu c;
+
+: abs (s n1 -- n2 ) dup 0< if negate then ;
+
+: min (s n1 n2 -- n3 ) 2dup > if swap then drop ;
+: max (s n1 n2 -- n3 ) 2dup < if swap then drop ;
+: umin (s u1 u2 -- u3 ) 2dup u> if swap then drop ;
+: umax (s u1 u2 -- u3 ) 2dup u< if swap then drop ;
+
+code up@ (s -- addr ) tos sp push up tos move c;
+code sp@ (s -- addr ) tos sp push sp tos move c;
+code rp@ (s -- addr ) tos sp push rp tos move c;
+code up! (s addr -- ) tos up move sp tos pop c;
+code sp! (s addr -- ) tos sp move sp tos pop c;
+code rp! (s addr -- ) tos rp move sp tos pop c;
+code >r (s n -- ) tos rp push sp tos pop c;
+code r> (s -- n ) tos sp push rp tos pop c;
+code r@ (s -- n ) tos sp push rp tos get c;
+code 2>r (s n1 n2 -- )
+ rp -8 rp addiu
+ sp 0 t0 lw
+ bubble
+ t0 rp 4 sw
+ tos rp 0 sw
+ sp 4 tos lw
+ sp 8 sp addiu
+c;
+code 2r> (s -- n1 n2 )
+ sp -8 sp addiu
+ tos sp 4 sw
+ rp 4 tos lw
+ bubble
+ tos sp 0 sw
+ rp 0 tos lw
+ rp 8 rp addiu
+c;
+code 2r@ (s -- n1 n2 )
+ sp -8 sp addiu
+ tos sp 4 sw
+ rp 4 tos lw
+ bubble
+ tos sp 0 sw
+ rp 0 tos lw
+c;
+
+code >ip (s n -- ) tos rp push sp tos pop c;
+code ip> (s -- n ) tos sp push rp tos pop c;
+code ip@ (s -- n ) tos sp push rp tos get c;
+: ip>token ( ip -- token-adr ) /token - ;
+
+code exit (s -- ) rp ip pop c;
+code unnest (s -- ) rp ip pop c;
+
+code tuck (s n1 n2 -- n2 n1 n2 )
+ sp t0 get
+ bubble
+ t0 sp push
+ tos sp 4 sw
+c;
+code nip (s n1 n2 -- n2 )
+ sp ainc
+c;
+code flip (s w1 -- w2 ) \ byte swap
+ tos 18 t0 sll
+ t0 10 t0 srl
+ tos 8 tos srl
+ tos t0 tos or
+c;
+
+assembler definitions
+:-h leaveflag (s condition -- )
+\ macro to assemble code to leave a flag on the stack
+ if
+ $0 tos move \ Delay slot
+ $0 -1 tos addiu
+ then
+;-h
+
+meta definitions
+code 0< (s n -- f ) tos $0 tos slt $0 tos tos subu c;
+code 0> (s n -- f ) $0 tos tos slt $0 tos tos subu c;
+code 0<= (s n -- f ) $0 tos tos slt tos -1 tos addiu c;
+code 0>= (s n -- f ) tos $0 tos slt tos -1 tos addiu c;
+
+code 0= (s n -- f ) tos $0 = leaveflag c;
+code 0<> (s n -- f ) tos $0 <> leaveflag c;
+
+assembler definitions
+:-h compare
+ sp t0 pop
+ t0 tos cmp
+;-h
+meta definitions
+
+code = (s n1 n2 -- f ) sp t0 pop tos t0 = leaveflag c;
+code <> (s n1 n2 -- f ) sp t0 pop tos t0 <> leaveflag c;
+
+code < (s n1 n2 -- f ) sp t0 pop t0 tos tos slt $0 tos tos subu c;
+code >= (s n1 n2 -- f ) sp t0 pop t0 tos tos slt tos -1 tos addiu c;
+code > (s n1 n2 -- f ) sp t0 pop tos t0 tos slt $0 tos tos subu c;
+code <= (s n1 n2 -- f ) sp t0 pop tos t0 tos slt tos -1 tos addiu c;
+code u< (s n1 n2 -- f ) sp t0 pop t0 tos tos sltu $0 tos tos subu c;
+code u>= (s n1 n2 -- f ) sp t0 pop t0 tos tos sltu tos -1 tos addiu c;
+code u> (s n1 n2 -- f ) sp t0 pop tos t0 tos sltu $0 tos tos subu c;
+code u<= (s n1 n2 -- f ) sp t0 pop tos t0 tos sltu tos -1 tos addiu c;
+
+code drop (s n -- ) sp tos pop c;
+code dup (s n -- n n ) tos sp push c;
+code over (s n1 n2 -- n1 n2 n1 ) tos sp push sp 4 tos lw c;
+code swap (s n1 n2 -- n2 n1 )
+ sp t0 get
+ tos sp put
+ t0 tos move
+c;
+code rot (s n1 n2 n3 -- n2 n3 n1 )
+ sp t0 get
+ sp 4 t1 lw
+ t0 sp 4 sw
+ tos sp put
+ t1 tos move
+c;
+code -rot (s n1 n2 n3 -- n3 n1 n2 )
+ sp t0 get
+ sp 4 t1 lw
+ tos sp 4 sw
+ t1 sp put
+ t0 tos move
+c;
+code 2drop (s d -- ) sp ainc sp tos pop c;
+code 2dup (s d -- d d )
+ sp t0 get
+ sp -8 sp addiu
+ tos sp 4 sw
+ t0 sp 0 sw
+c;
+code 2over (s d1 d2 -- d1 d2 d1 )
+ sp -8 sp addiu
+ tos sp 4 sw
+ sp 10 tos lw
+ bubble
+ tos sp 0 sw
+ sp 0c tos lw
+c;
+code 2swap (s d1 d2 -- d2 d1 )
+ sp 8 t2 lw
+ sp 4 t1 lw
+ sp 0 t0 lw
+ bubble
+ t0 sp 8 sw
+ tos sp 4 sw
+ t2 sp 0 sw
+ t1 tos move
+c;
+code 3drop (s n1 n2 n3 -- )
+ sp 8 tos lw
+ sp c sp addiu
+c;
+code 3dup (s n1 n2 n3 -- n1 n2 n3 n1 n2 n3 )
+ sp 4 t1 lw
+ sp 0 t0 lw
+ sp -c sp addiu
+ tos sp 8 sw
+ t1 sp 4 sw
+ t0 sp 0 sw
+c;
+code 4drop (s n1 n2 n3 n4 -- )
+ sp 0c tos lw
+ sp 10 sp addiu
+c;
+code 5drop (s n1 n2 n3 n4 n5 -- )
+ sp 10 tos lw
+ sp 14 sp addiu
+c;
+
+code pick (s nm ... n1 n0 k -- nm ... n2 n0 nk )
+ tos 2 tos sll \ Multiply by /n
+ sp tos tos addu
+ tos 0 tos lw \ Index into stack
+c;
+
+code 1+ (s n1 -- n2 ) tos 1 tos addiu c;
+code 2+ (s n1 -- n2 ) tos 2 tos addiu c;
+code 1- (s n1 -- n2 ) tos -1 tos addiu c;
+code 2- (s n1 -- n2 ) tos -2 tos addiu c;
+
+code 2/ (s n1 -- n2 ) tos 1 tos sra c;
+code u2/ (s n1 -- n2 ) tos 1 tos srl c;
+code 2* (s n1 -- n2 ) tos 1 tos sll c;
+code 4* (s n1 -- n2 ) tos 2 tos sll c;
+code 8* (s n1 -- n2 ) tos 3 tos sll c;
+
+code on (s addr -- )
+ $0 -1 t0 addiu
+ t0 tos put
+ sp tos pop
+c;
+code off (s addr -- )
+ $0 tos put
+ sp tos pop
+c;
+
+code +! (s n addr -- )
+ sp t0 get
+ tos t1 get
+ bubble
+ t1 t0 t1 addu
+ t1 tos put
+ sp 4 tos lw
+ sp 8 sp addiu
+c;
+
+code @ (s adr -- n ) tos 0 tos lw c; \ longword aligned
+code l@ (s adr -- l ) tos 0 tos lw c; \ longword aligned
+code w@ (s adr -- w ) tos 0 tos lhu c; \ 16-bit word aligned
+code <w@ (s adr -- w ) tos 0 tos lh c; \ with sign extension
+code c@ (s adr -- c ) tos 0 tos lbu c;
+
+code ! (s n adr -- )
+ sp 0 t0 lw
+ bubble
+ t0 tos 0 sw
+ sp 4 tos lw
+ sp 8 sp addiu
+c;
+code l! (s n adr -- )
+ sp 0 t0 lw
+ bubble
+ t0 tos 0 sw
+ sp 4 tos lw
+ sp 8 sp addiu
+c;
+code w! (s w adr -- )
+ sp 0 t0 lw
+ bubble
+ t0 tos 0 sh
+ sp 4 tos lw
+ sp 8 sp addiu
+c;
+code c! (s c adr -- )
+ sp 0 t0 lw
+ bubble
+ t0 tos 0 sb
+ sp 4 tos lw
+ sp 8 sp addiu
+c;
+
+code x@ (s adr -- x ) \ doubleword aligned
+ tos 0 t0 ld
+ sp -4 sp addiu
+ t0 sp 0 sw
+ t0 0 tos dsra32
+c;
+code x! (s x adr -- )
+ sp 0 t0 lw
+ bubble
+ t0 0 t0 dsll32
+ sp 4 t1 lw
+ t1 0 t1 dsll32
+ t1 0 t1 dsrl32
+ t0 t1 t0 or
+
+ t0 tos 0 sd
+ sp 8 tos lw
+ sp c sp addiu
+c;
+
+: instruction! (s n adr -- ) tuck ! /l sync-cache ;
+
+: instruction, (s opcode -- ) here /l allot instruction! ;
+
+code 2@ (s adr -- d )
+ tos $at move
+ $at 4 t0 lw
+ t0 sp push
+ $at 0 tos lw
+c;
+code 2! (s d adr -- )
+ sp 0 t0 lw
+ bubble
+ t0 tos 0 sw
+ sp 4 t0 lw
+ bubble
+ t0 tos 4 sw
+ sp 8 tos lw
+ sp 0c sp addiu
+c;
+
+code fill (s start-adr count char -- )
+ \ char in tos
+ sp 0 t0 lw \ count in t0
+ sp 4 t1 lw \ dst in t1
+ bubble
+
+ t0 t1 t0 addu \ limit in t0
+ t0 t1 <> if
+ t1 1 t1 addiu \ (delay) increment dst
+
+ begin
+ tos t1 -1 sb
+ t0 t1 = until
+ t1 1 t1 addiu \ (delay) increment dst
+ then
+
+ sp 8 tos lw
+ sp 0c sp addiu
+c;
+
+code lfill (s start-adr count long -- )
+ \ long in tos
+ sp 0 t0 lw \ count in t0
+ sp 4 t1 lw \ dst in t1
+ bubble
+
+ t0 3 t0 addi \ round up
+ t0 2 t0 srl
+ t0 2 t0 sll \ Clear low bits
+
+ t0 t1 t0 addu \ limit in t0
+ t0 t1 <> if
+ t1 4 t1 addiu \ (delay) increment dst
+
+ begin
+ tos t1 -4 sw
+ t0 t1 = until
+ t1 4 t1 addiu \ (delay) increment dst
+ then
+
+ sp 8 tos lw
+ sp 0c sp addiu
+c;
+
+code noop (s -- ) c;
+
+code n->l (s n.unsigned -- l ) c;
+
+code lwsplit (s l -- w.low w.high ) \ split a long into two words
+ tos t0 move
+ t0 10 t0 sll
+ t0 10 t0 srl
+ t0 sp push
+ tos 10 tos srl
+c;
+code wljoin (s w.low w.high -- l )
+ sp t0 pop
+ t0 10 t0 sll \ Throw away any high order bits in w.low
+ t0 10 t0 srl
+ tos 10 tos sll
+ tos t0 tos or
+c;
+
+1 constant /c
+2 constant /w
+4 constant /l
+/l constant /n
+
+code ca+ (s addr index -- addr+index*/c )
+ sp t0 pop
+ tos t0 tos addu
+c;
+code wa+ (s addr index -- addr+index*/w )
+ sp t0 pop
+ tos 1 tos sll
+ tos t0 tos addu
+c;
+code la+ (s addr index -- addr+index*/l )
+ sp t0 pop
+ tos 2 tos sll
+ tos t0 tos addu
+c;
+code na+ (s addr index -- addr+index*/n )
+ sp t0 pop
+ tos 2 tos sll
+ tos t0 tos addu
+c;
+code ta+ (s addr index -- addr+index*/t )
+ sp t0 pop
+ tos 2 tos sll
+ tos t0 tos addu
+c;
+
+code ca1+ (s addr -- addr+/w ) tos 1 tos addiu c;
+code char+ (s addr -- addr+/w ) tos 1 tos addiu c;
+code wa1+ (s addr -- addr+/w ) tos 2 tos addiu c;
+code la1+ (s addr -- addr+/l ) tos 4 tos addiu c;
+code na1+ (s addr -- addr+/n ) tos 4 tos addiu c;
+code cell+ (s addr -- addr+/n ) tos 4 tos addiu c;
+code ta1+ (s addr -- addr+/token ) tos /token tos addiu c;
+
+code /c* (s n -- n*/c ) c;
+code chars (s n -- n*/c ) c;
+code /w* (s n -- n*/w ) tos 1 tos sll c;
+code /l* (s n -- n*/l ) tos 2 tos sll c;
+code /n* (s n -- n*/n ) tos 2 tos sll c;
+code cells (s n -- n*/n ) tos 2 tos sll c;
+
+: upc (s char -- upper-case-char )
+ dup ascii a ascii z between if ( hex ) 20 - then
+;
+: lcc (s char -- upper-case-char )
+ dup ascii A ascii Z between if ( hex ) 20 + then
+;
+
+code c@+ (s adr -- adr' char )
+ tos 1 t0 addiu
+ t0 sp push
+ tos 0 tos lbu
+c;
+
+: comp (s addr1 addr2 len -- -1 | 0 | 1 )
+ rot 0 swap 2swap ( 0 addr1 addr2 len )
+ bounds ?do ( 0 addr1' )
+ c@+ i c@ <> if ( 0 addr1' )
+ nip dup 1- c@ i c@ < if -1 else 1 then ( addr1' flag )
+ swap leave ( flag addr1' )
+ then ( 0 addr1' )
+ loop
+ drop
+;
+
+: caps-comp (s addr1 addr2 len -- -1 | 0 | 1 )
+ rot 0 swap 2swap ( 0 addr1 addr2 len )
+ bounds ?do ( 0 addr1' )
+ c@+ lcc i c@ lcc <> if ( 0 addr1' )
+ nip dup 1- c@ lcc i c@ lcc <
+ if -1 else 1 then ( addr1' flag )
+ swap leave ( flag addr1' )
+ then ( 0 addr1' )
+ loop
+ drop
+;
+
+: pack (s str-adr len to -- to )
+ dup >r
+ 2dup c! ( str-adr len to )
+ 1+ 2dup + 0 swap c! ( str-adr len to+1 )
+ swap cmove
+ r>
+;
+
+\ code pack (s str-adr len to -- to )
+\ sp t0 pop \ t0 is len
+\ sp t1 pop \ t1 is "from"; tos is "to"
+\
+\ t0 ff t0 andi \ Never store more than 257 bytes
+\
+\ t0 tos 0 stb \ Place length byte
+\
+\ tos 1 tos addiu \ Offset "to" by 1 to skip past the length byte
+\
+\ tos t0 $at addu
+\ $0 $at stb \ Put a null byte at the end
+\
+\ 0 F: bra \ jump to the until branch
+\ t0 1 t0 subcc \ Delay slot
+\
+\ begin
+\ t2 tos t0 stb
+\ t0 1 t0 subcc
+\ 0 L:
+\ 0< until annul
+\ t1 t0 t2 ldub \ Delay slot
+\
+\ tos -1 tos addiu \ Fix "to" to point to the length byte
+\ c;
+
+code (') (s -- acf )
+ tos sp push
+ ip 0 tos lw
+ ip /token ip addiu
+ tos base tos addu
+c;
+
+\ Modifies caller's ip to skip over an in-line string
+code skipstr (s -- adr len)
+ sp -8 sp addiu
+ tos sp 4 sw
+ rp 0 t0 lw \ Get string address in t0
+ bubble
+ t0 0 tos lbu \ Get length byte in tos
+ t0 1 t0 addiu \ Address of data bytes
+ t0 sp 0 sw \ Put adr on stack
+
+ \ Now we have to skip the string
+ t0 tos t0 addu \ Scr now points past the last data byte
+ t0 #talign t0 addiu \ Round up to token boundary + null byte
+ $0 #talign negate $at addiu
+ t0 $at t0 and
+ t0 rp 0 sw \ Put the modified ip back
+c;
+
+code (") (s -- adr len)
+ sp -8 sp addiu
+ tos sp 4 sw
+ ip 0 tos lbu \ Get length byte in tos
+ ip 1 ip addiu \ Address of data bytes
+ ip sp 0 sw \ Put adr on stack
+
+ \ Now we have to skip the string
+ ip tos ip addu \ ip now points past the last data byte
+ ip #talign ip addiu \ Round up to a token boundary, plus null byte
+ $0 #talign negate $at addiu
+ ip $at ip and
+c;
+
+code count (s adr -- adr+1 len )
+ tos 1 tos addiu
+ tos -1 t0 lbu
+ tos sp push
+ t0 tos move
+c;
+
+\ 0 constant origin
+\ here-t 4 - set-relocation-bit-t drop
+code origin (s -- addr )
+ tos sp push
+ base tos move
+c;
+
+: origin+ (s n -- adr ) origin + ;
+: origin- (s n -- adr ) origin - ;
+
+headers
+
+\ Put a branch instruction to target-adr at where
+: put-branch ( target-adr where -- )
+ tuck 4 - - ( where byte-offset )
+ 2/ 2/ ffff and ( where longword-offset )
+ 1000.0000 or ( where "$0 $0 beq" )
+ swap !
+;
+: acf-align (s -- )
+ begin here #acf-align 1- and while 0 c, repeat
+ here 'lastacf token!
+;
+
+headerless
+
+\ Place the "standard" code field
+
+: set-cf (s action-adr -- )
+ acf-align origin+ token,
+;
+
+headers
+: place-cf (s action-adr -- )
+ acf-align token,
+;
+: code-cf (s -- ) acf-align here ta1+ aligned token, align ;
+
+: >code ( acf-of-code-word -- address-of-start-of-machine-code ) token@ ;
+: code? ( acf -- f ) \ True if the acf is for a code word
+ dup token@ swap >body =
+;
+
+\ Assemble "next" routine at the end of a code definition.
+\ This is not needed for the kernel to run; it is used later
+\ after the resident assembler has been loaded
+
+: next (s --- )
+ \ (next) j nop
+\ 0800.0000 [ (next) ] literal h# 20 + 2 >> or , 0000.0000 ,
+ \ np jr nop
+ h# 0220.0008 instruction, 0000.0000 instruction,
+;
+
+: create-cf (s -- ) [ dodoes ] literal set-cf ['] noop token, ;
+: variable-cf (s -- ) [ dovariable ] literal set-cf ;
+
+: place-;code (s -- ) code-cf ;
+: place-does (s -- ) [ docolon ] literal set-cf ;
+
+\ Ip is assumed to point to (;code . flag is true if
+\ the code at ip is a does> clause as opposed to a ;code clause.
+: does-ip? ( ip -- ip' flag )
+ dup token@ ['] (does>) = ( ip flag ) swap ta1+ ta1+ swap
+;
+
+: put-cf (s action-clause-adr where -- ) token! ;
+
+\ uses sets the code field of the indicated word so that
+\ it will execute the code at action-clause-adr
+: uses (s action-clause-adr xt -- )
+ tuck /token + put-cf
+ [ dodoes ] literal origin+ swap put-cf
+;
+
+\ used sets the code field of the most-recently-defined word so that
+\ it executes the word at action-clause-adr
+: used (s action-clause-adr -- ) lastacf uses ;
+
+: colon-cf? ( possible-acf -- flag )
+ dup token@ [ docolon ] literal origin+ = if
+ /token - token@
+ dup ['] branch <>
+ over ['] ?branch <> and
+ over ['] (of) <> and
+ over ['] (leave) <> and
+ over ['] (?leave) <> and
+ over ['] (do) <> and
+ over ['] (?do) <> and
+ swap ['] (lit) <> and
+ else
+ drop false
+ then
+;
+: colon-cf (s -- ) [ docolon ] literal set-cf ;
+: user-cf (s -- ) [ douser ] literal set-cf ;
+: value-cf (s -- ) [ dovalue ] literal set-cf ;
+: constant-cf (s -- ) [ doconstant ] literal set-cf ;
+: defer-cf (s -- ) [ dodefer ] literal set-cf ;
+: 2constant-cf (s -- ) [ do2constant ] literal set-cf ;
+
+4 constant /branch
+: branch, ( offset -- ) , ;
+: branch! ( offset where -- ) ! ;
+
+headerless
+: branch@ ( where -- offset ) @ ;
+\ >target depends on the way that branches are compiled
+: >target ( ip-of-branch-instruction -- target ) ta1+ dup branch@ + ;
+headerless
+
+/a constant /a
+
+headers
+
+code a@ ( adr -- adr' )
+ tos tos get
+ bubble
+ tos base tos addu
+c;
+
+\ R : a! ( adr1 adr2 -- ) set-relocation-bit l! ;
+code a! ( adr1 adr2 -- )
+ sp t0 pop
+ t0 base t0 subu
+ t0 tos put
+ sp tos pop
+c;
+: a, ( adr -- ) here /a allot a! ;
+
+/token constant /token
+code token@ (s adr -- cfa )
+ tos 0 tos lw
+ bubble
+ tos base tos addu
+c;
+\ R : token! (s cfa adr -- ) set-relocation-bit l! ;
+code token! (s cfa addr -- )
+ sp t0 get
+ bubble
+ t0 base t0 subu
+ t0 tos put
+ sp 4 tos lw
+ sp 8 sp addiu
+c;
+
+
+: token, (s cfa -- ) here /token allot token! ;
+
+: null ( -- token ) origin ;
+: !null-link ( adr -- ) null swap link! ;
+: !null-token ( adr -- ) null swap token! ;
+: non-null? ( link -- false | link true )
+ dup origin = if drop false else true then
+;
+\ code non-null? ( link -- false | link true )
+\ tos base cmp
+\ <> if
+\ false t0 move \ Delay slot
+\
+\ tos sp push
+\ true t0 move
+\ then
+\ t0 tos move
+\ c;
+: get-token? ( adr -- false | acf true ) token@ non-null? ;
+: another-link? ( adr -- false | link true ) link@ non-null? ;
+
+\ The "word type" is a number which distinguishes one type of word
+\ from another. This is highly implementation-dependent.
+
+\ For the MIPS implementation, the magic number returned by word-type
+\ is the absolute address of the action code.
+
+: long-cf? (s acf -- flag ) token@ origin- [ dodoes ] literal = ;
+
+: word-type (s acf -- word-type ) dup long-cf? if ta1+ then token@ ;
+
+: body> (s apfa -- acf )
+ /token - dup /token - long-cf? if /token - then
+;
+: >body (s acf -- apf ) dup long-cf? if ta1+ then ta1+ ;
+
+4 constant /user#
+
+\ Move to a machine alignment boundary.
+
+: aligned (s adr -- adr' ) /n round-up ;
+
+code acf-aligned (s adr -- adr' )
+ tos 3 tos addiu
+ $0 -4 $at addiu
+ tos $at tos and
+c;
+
+\ Floored division is prescribed by the Forth 83 standard.
+\ The quotient is rounded toward negative infinity, and the
+\ remainder has the same sign as the divisor.
+
+: /mod (s dividend divisor -- remainder quotient )
+ \ Check if either factor is negative
+ 2dup ( n1 n2 n1 n2)
+ or 0< if ( n1 n2)
+
+ \ Both factors not non-negative; do division by:
+ \ Take absolute value and do unsigned division
+ \ Convert to truncated signed divide by:
+ \ if dividend is negative then negate the remainder
+ \ if dividend and divisor have opposite signs then negate the quotient
+ \ Then convert to floored signed divide by:
+ \ if quotient is negative and remainder is non-zero
+ \ add divisor to remainder and decrement quotient
+
+ 2dup swap abs swap abs ( n1 n2 u1 u2) \ Absolute values
+
+ u/mod ( n1 n2 urem uqout) \ Unsigned divide
+ >r >r ( n1 n2) ( uquot urem)
+
+ over 0< if ( n1 n2) ( uquot urem)
+ r> negate >r \ Negative dividend; negate remainder
+ then ( n1 n2) ( uquot trem)
+
+ swap over ( n2 n1 n2) ( uquot trem)
+ xor 0< if ( n2) ( uquot trem)
+ r> r>
+ negate ( n2 trem tquot) \ Opposite signs; negate quotient
+ -rot ( tquot n2 trem)
+ dup 0<> if
+ + ( tquot rem) \ Negative quotient & non-zero remainder
+ swap 1- ( rem quot) \ add divisor to rem. & decrement quot.
+ else
+ nip swap ( rem quot)
+ then
+ else
+ drop r> r> ( rem quot)
+ then
+
+ else \ Both factors non-negative
+
+ u/mod ( rem quot)
+ then
+;
+
+code u/mod (s u.dividend u.divisor -- u.remainder u.quotient )
+ sp t0 get \ dividend
+ bubble
+ t0 tos divu \ Calculate result
+ t0 mfhi \ Get remainder
+ t0 sp put
+ tos mflo \ Get quotient
+c;
+
+: / (s n1 n2 -- quot ) /mod nip ;
+
+: mod (s n1 n2 -- rem ) /mod drop ;
+
+: um/mod (s ul.dividend un.divisor -- un.remainder un.quotient ) u/mod ;
+
+: m/mod (s l.dividend n.divisor -- n.remainder n.quotient ) /mod ;
+
+\ 32*32->64 bit unsigned multiply
+\ y rs2 y rd
+
+code um* ( u1 u2 -- ud[lo hi] )
+ sp t0 get
+ bubble
+ t0 tos multu
+ t0 mflo
+ t0 sp put
+ tos mfhi
+c;
+
+code m* ( n1 n2 -- low high )
+ sp t0 get
+ bubble
+ t0 tos mult
+ t0 mflo
+ t0 sp put
+ tos mfhi
+c;
+
+code * ( n1 n2 -- n3 )
+ sp t0 pop
+ t0 tos mult
+ tos mflo
+c;
+
+: ul* (s un1 un2 -- lproduct ) * ;
+: u* (s un1 un2 -- uproduct ) * ;
+
+: d+ ( d.a d.b -- d.c )
+ >r rot tuck + ( a.hi a.lo c.lo r: b.hi )
+ tuck u> negate ( a.hi c.lo carry r: b.hi )
+ rot + r> + ( d.c )
+;
+: d- ( d.a d.b -- d.c )
+ >r swap >r ( a.lo b.lo r: b.hi a.hi )
+ 2dup u< >r ( a.lo b.lo r: b.hi a.hi borrow )
+ - ( c.lo r: b.hi a.hi borrow )
+ r> r> + r> - ( d.c )
+;
+: d@ ( adr -- low high ) dup 4 + @ swap @ ;
+
+\ MIPS version is dynamically relocated, so we don't need a bitmap
+: clear-relocation-bits ( adr len -- ) 2drop ;
+
+only forth also labels also meta also assembler definitions
+
+:-h 'user# \ name ( -- user# )
+ [ meta ]-h ' ( acf-of-user-variable ) >body-t
+ @-t
+;-h
+:-h 'user \ name ( -- user-addressing-mode )
+ [ assembler ]-h up 'user#
+;-h
+:-h 'body \ name ( -- variable-apf )
+ [ meta ]-h ' ( acf-of-user-variable ) >body-t
+;-h
+:-h 'acf \ name ( -- variable-apf )
+ [ meta ]-h ' ( acf-of-user-variable ) >body-t
+;-h
+
+only forth also labels also meta also definitions
+
+: move ( src dst cnt -- )
+ >r 2dup u< if r> cmove> else r> cmove then
+;
+
+init-user-area constant init-user-area
+
+code (llit) (s -- l )
+ tos sp push ip tos get ip ainc
+c;
+
+code (dlit) (s -- d )
+ sp -8 sp addiu
+ tos sp 4 sw
+ ip 4 t0 lw
+ ip tos get
+ t0 sp 0 sw
+ ip 8 ip addiu
+c;
+
+\ Select a vocabulary thread by hashing the lookup name.
+\ Hashing function: Use the lower bits of the first character in the
+\ name to select one of #threads threads in the array pointed-to by
+\ the user number in the parameter field of voc-acf.
+code hash (s str-addr voc-acf -- thread )
+ \ The next 2 lines are equivalent to ">threads", which in this
+ \ implementation happens to be the same as ">body >user"
+ tos 8 tos lw \ Get the user number
+ bubble
+ up tos tos addu \ Find the address of the threads
+
+ sp t0 pop
+ t0 1 t0 lbu
+ bubble
+ t0 #threads-t 1- t0 andi
+ t0 2 t0 sll \ Convert index to longword offset
+ tos t0 tos addu
+c;
+
+\ Search a vocabulary thread (link) for a name matching string.
+\ If found, return its code field address and -1 if immediate, 1 if not
+\ immediate. If not found, return the string and 0.
+
+\ Name field:
+\ name: forth-style packed string, no tag bits
+\ flag: 40 bit is immediate bit
+\ Padding is optionally inserted between the name and the flags
+\ so that the byte after the flag byte is on an even boundary.
+
+[ifdef] notdef
+code (find) (s string link origin -- acf -1 | acf 1 | string 0 )
+ tos t5 move \ Origin in t5
+ sp tos pop \ link in tos
+\ Registers:
+\ tos alf of word being tested
+\ t0 string
+\ t1 name being tested
+\ t2 # of characters left to test
+\ string is kept on the top of the external stack
+
+ begin tos t5 <> while \ Test for end of list
+ tos /token t1 addiu \ Get name address of word to test
+ sp t0 get \ Get string address
+ bubble
+ t0 0 t2 lbu \ get the name field length
+ begin
+ t0 0 t3 lbu \ Compare 2 characters
+ t1 0 t4 lbu
+ bubble
+ t3 t4 = while \ Keep looking as long as characters match
+ t0 1 t0 addiu \ Increment byte pointers
+ t2 -1 t2 addiu \ Decrement byte counter
+ t2 0< if \ If we've tested all chars, the names match.
+ t1 1 t1 addiu \ Delay slot
+ t1 0 tos lbu \ Get flags byte into tos register
+
+ t1 4 t1 addiu \ Now find the code field by
+ $0 -4 $at addiu
+ t1 $at t1 and \ aligning to the next 4 byte boundary
+
+ tos 20 $at andi \ Test the alias flag
+ $at $0 <> if
+ nop
+ t1 0 t1 lw \ Get acf
+ bubble
+ t1 base t1 addu \ Relocate
+ then
+
+ t1 sp put \ Replace string on stack with acf
+ tos 40 $at andi \ Test the immediate flag
+ $at $0 <> if
+ $0 -1 tos addiu \ Not immediate \ Delay slot
+ ( else )
+ $0 1 tos addiu \ Immediate
+ then
+ next
+ then
+ repeat
+ nop
+
+ \ The names did not match, so check the next name in the list
+ tos 0 tos lw \ Fetch next link
+ bubble
+ tos base tos addu \ Relocate
+ repeat
+ nop \ Delay slot
+
+ \ If we get here, we've checked all the names with no luck
+ $0 tos move
+c;
+[then]
+
+code ($find-next) (s adr len link -- adr len alf true | adr len false )
+\ Registers:
+\ tos alf of word being tested
+\ t0 string
+\ t1 anf of word being tested
+\ t2 saves ctr register value
+\ t3 character from string
+\ t4 character from name
+\ t5 string length
+\ string is kept on the top of the external stack
+
+ sp 4 t0 lw \ Get string address
+ sp 0 t5 lw \ get the name field length
+ \ link in tos
+
+ ahead nop \ Branch to end of loop the first time
+\ tos 0 tos lw \ Fetch next link ( next acf )
+\ bubble
+
+\ tos $0 <> if \ Until end of linked list
+\ tos base tos addu \ Relocate (delay slot)
+
+ begin
+ tos -4 tos addiu \ >link
+ tos -1 t1 addiu \ t1 points before count byte at string *end*
+ t1 t5 t1 subu \ t1 points to beginning of string
+ t0 t6 move
+
+ t5 $at move \ Set starting loop index
+ begin
+ t1 0 t4 lbu \ Get character from name field
+ t1 1 t1 addiu
+ t6 0 t3 lbu \ Get character from search string
+ t6 1 t6 addiu
+ t3 t4 = while \ Compare 2 characters
+ $at -1 $at addiu \ Decrement character count (delay slot)
+ $at $0 = if
+ nop \ If we've tested all name chars, we
+ t1 0 t4 lbu \ may have a match; check the count byte
+ bubble
+ t4 h# 1f t4 andi \ Remove tag bits
+ t4 t5 = if \ Compare count bytes
+ nop
+ tos sp push \ Push alf above pstr
+ $0 -1 tos addiu \ True on top of stack means "found"
+ next
+ then
+ then
+ repeat
+ nop
+
+ but then \ Target of "ahead" branch
+
+ \ The names did not match, so check the next name in the list
+ tos 0 tos lw \ Fetch next link ( next acf )
+ bubble
+
+ tos $0 = until \ Until end of linked list
+ tos base tos addu \ Relocate (delay slot)
+\ then
+
+ \ If we get here, we've checked all the names with no luck
+ $0 tos move \ Return false
+c;
+
+: ?negate (s n1 n2 -- n3 ) if negate then ;
+
+code wflip (s l1 -- l2 ) \ word swap
+ tos t0 move
+ tos 10 tos srl
+ t0 10 t0 sll
+ tos t0 tos or
+c;
+
+: cset (s byte-mask adr -- ) tuck c@ or swap c! ;
+: creset (s byte-mask adr -- ) swap invert over c@ and swap c! ;
+: ctoggle (s byte-mask adr -- ) tuck c@ xor swap c! ;
+: toggle (s adr byte-mask -- ) swap ctoggle ;
+
+code s->l (s n.signed -- l ) c;
+code l->n (s l -- n ) c;
+code n->a (s n -- a ) c;
+code l->w (s l -- w ) tos 10 tos sll tos 10 tos srl c;
+code n->w (s n -- w ) tos 10 tos sll tos 10 tos srl c;
+code w->n (s w -- n ) tos 10 tos sll tos 10 tos sra c;
+
+code l>r (s l -- ) tos rp push sp tos pop c;
+code lr> (s -- l ) tos sp push rp tos pop c;
+code lr@ (s -- l ) tos sp push rp tos get c;
+
+code /t* (s n -- n*/t ) tos 2 tos sll c;
+
+#align-t constant #align
+#acf-align-t constant #acf-align
+#talign-t constant #talign
+
+: align (s -- ) #align (align) ;
+: taligned (s adr -- adr' ) #talign round-up ;
+: talign (s -- ) #talign (align) ;
+
+code np@ ( -- adr ) tos sp push np tos move c;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/kernel.bth
===================================================================
--- cpu/mips/kernel.bth (rev 0)
+++ cpu/mips/kernel.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,127 @@
+purpose: Load file for MIPS Forth kernel
+\ See license at end of file
+
+command: &builder &this
+build-now
+
+create little-endian-t
+
+ ' $report-name is include-hook
+\ ' noop is include-hook
+\ ' noop is include-exit-hook
+
+\ Don't accept ',' as numeric punctuation because doing so makes
+\ the forward referencing mechanism think that "c," is a number!
+ascii . ascii , npatch numdelim?
+
+warning off \ Turn OFF the warning messages
+
+[ifdef] maketags
+fload ${BP}/forth/lib/tags.fth
+' ("header) is "header
+defer "header-t-hook ' (tags-header) is "header-t-hook
+"" loadkern.fth last-filename "copy
+[then]
+
+alias constant-h constant
+
+fload ${BP}/forth/kernel/conft32.fth
+fload ${BP}/forth/kernel/meta1.fth
+
+only forth also meta also definitions
+\needs mips-assembler fload ${BP}/cpu/mips/assem.fth
+
+only forth also meta definitions
+: assembler ( -- ) mips-assembler ;
+
+only forth also meta also assembler definitions
+\needs L: fload ${BP}/forth/lib/loclabel.fth
+init-labels
+
+only forth also definitions
+\needs bitset fload ${BP}/forth/lib/bitops.fth
+
+fload ${BP}/forth/kernel/swapmap.fth
+\ : : : lastacf .name cr ;
+fload ${BP}/cpu/mips/target.fth
+fload ${BP}/forth/kernel/forward.fth
+fload ${BP}/cpu/mips/fixvoc.fth
+fload ${BP}/forth/kernel/metacompile.fth
+
+warning on
+fload ${BP}/cpu/mips/metainit.fth
+
+\ fload ${BP}/cpu/mips/metarel.fth
+
+" kernel.tag" r/w create-file drop meta-tag-file !
+
+always-headers
+
+\ Comment out the following line(s) when debugging
+-1 threshold ! \ Turn OFF ALL debugging messages
+warning-t off \ Turn OFF target warning messages
+
+\ Uncomment the following line(s) for more debug output
+\ show? on 1 granularity ! 1 threshold !
+\ warning-t on
+
+fload ${BP}/cpu/mips/kerncode.fth
+
+fload ${BP}/forth/kernel/uservars.fth
+fload ${BP}/forth/kernel/double.fth
+fload ${BP}/forth/kernel/scan.fth
+
+fload ${BP}/forth/lib/bitops.fth
+fload ${BP}/cpu/ppc/kernrel.fth
+\ fload ${BP}/forth/kernel/swapmap.fth
+
+fload ${BP}/forth/lib/struct.fth
+
+fload ${BP}/cpu/mips/unalign.fth
+
+fload ${BP}/forth/kernel/kernel.fth
+
+fload ${BP}/forth/kernel/sysio.fth
+fload ${BP}/forth/lib/dumballo.fth
+
+fload ${BP}/cpu/mips/filecode.fth
+
+fload ${BP}/cpu/mips/sys.fth
+
+fload ${BP}/cpu/mips/kernboot.fth
+
+\ fload ${BP}/cpu/mips/boot.fth
+fload ${BP}/forth/kernel/init.fth
+fload ${BP}/cpu/mips/finish.fth
+
+meta-tag-file @ fclose meta-tag-file off
+
+fload ${BP}/cpu/mips/savemeta.fth
+
+.( Saving as kernel.dic ...) " kernel.dic" $save-meta
+cr
+
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/ksegaddr.fth
===================================================================
--- cpu/mips/ksegaddr.fth (rev 0)
+++ cpu/mips/ksegaddr.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,35 @@
+purpose: KSEG addresses for MIPS
+\ See license at end of file
+
+headerless
+
+h# 0000.0000 constant kuseg \ 2GB user space
+h# 8000.0000 constant kseg0 \ "unmapped" cached
+h# a000.0000 constant kseg1 \ "unmapped" uncached
+h# c000.0000 constant kseg2 \ mapped space
+
+headers
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/lmove.fth
===================================================================
--- cpu/mips/lmove.fth (rev 0)
+++ cpu/mips/lmove.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,69 @@
+purpose: Longword memory copy
+\ See license at end of file
+
+code lmove ( from-addr to-addr cnt -- )
+ sp 4 t0 lw \ Src into t0
+ sp 0 t1 lw \ Dst into t1
+
+ t0 tos t2 addu \ t2 = src limit
+
+ t0 t2 <> if
+ nop
+
+ begin
+ t0 0 t3 lw \ Load word
+ t0 4 t0 addiu \ (load delay) Increment src
+ t3 t1 0 sw \ Store word
+ t0 t2 = until
+ t1 4 t1 addiu \ (delay) Increment dst
+
+ then
+
+ sp 8 tos lw \ Delay slot - Reload tos
+ sp 3 /n* sp addiu \ "
+c;
+code wmove ( from-adr to-adr #bytes -- )
+ sp 4 t0 lw \ Src into t0
+ sp 0 t1 lw \ Dst into t1
+
+ t0 tos t2 addu \ t2 = src limit
+
+ t0 t2 <> if
+ nop
+
+ begin
+ t0 0 t3 lhu \ Load halfword
+ t0 2 t0 addiu \ (load delay) Increment src
+ t3 t1 0 sh \ Store halfword
+ t0 t2 = until
+ t1 2 t1 addiu \ (delay) Increment dst
+
+ then
+
+ sp 8 tos lw \ Delay slot - Reload tos
+ sp 3 /n* sp addiu \ "
+c;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/loadmach.fth
===================================================================
--- cpu/mips/loadmach.fth (rev 0)
+++ cpu/mips/loadmach.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,93 @@
+purpose: Load file for MIPS machine-specific words
+\ See license at end of file
+
+start-module
+assembler? [if]
+fload ${BP}/cpu/mips/assem.fth
+fload ${BP}/cpu/mips/code.fth
+fload ${BP}/forth/lib/loclabel.fth
+[else]
+transient fload ${BP}/cpu/mips/assem.fth resident
+fload ${BP}/cpu/mips/code.fth
+transient fload ${BP}/forth/lib/loclabel.fth resident
+[then]
+
+fload ${BP}/cpu/mips/disassem.fth \ Exports (dis , pc , dis1 , +dis
+
+fload ${BP}/forth/lib/instdis.fth
+
+fload ${BP}/cpu/mips/decompm.fth
+
+: be-l! ( l adr -- ) >r lbsplit r@ c! r@ 1+ c! r@ 2+ c! r> 3 + c! ;
+: be-l, ( l -- ) here set-swap-bit here 4 allot be-l! ;
+: be-l@ ( adr -- n ) >r r@ 3 + c@ r@ 2+ c@ r@ 1+ c@ r> c@ bljoin ;
+: be-w@ ( adr -- w ) dup 1+ c@ swap c@ bwjoin ;
+
+fload ${BP}/cpu/mips/objsup.fth
+fload ${BP}/forth/lib/objects.fth
+also hidden
+alias reasonable-ip? reasonable-ip?
+previous
+end-module
+
+fload ${BP}/cpu/mips/cpustate.fth
+fload ${BP}/cpu/mips/register.fth
+
+fload ${BP}/forth/lib/savedstk.fth
+fload ${BP}/forth/lib/rstrace.fth
+fload ${BP}/cpu/mips/ftrace.fth
+fload ${BP}/cpu/mips/ctrace.fth
+
+fload ${BP}/cpu/mips/debugm.fth \ Forth debugger support
+fload ${BP}/forth/lib/debug.fth \ Forth debugger
+
+[ifdef] notyet
+also bug
+alias set-package set-package
+alias unset-package unset-package
+previous
+[then]
+
+fload ${BP}/cpu/mips/cpubpsup.fth \ Breakpoint support
+fload ${BP}/forth/lib/breakpt.fth
+
+[ifdef] notyet
+fload ${BP}/cpu/mips/dfill.fth \ Memory fill words
+fload ${BP}/cpu/mips/memtest.fth
+[then]
+
+\ fload ${BP}/cpu/mips/fentry.fth \ I don't think we need this...
+fload ${BP}/cpu/mips/call.fth
+
+transient fload ${BP}/forth/lib/binhdr.fth resident
+transient fload ${BP}/cpu/mips/savefort.fth resident
+
+alias $save-forth $save-forth
+
+fload ${BP}/cpu/mips/lmove.fth
+
+fload ${BP}/cpu/mips/r4000cp0.fth
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/machdep.fth
===================================================================
--- cpu/mips/machdep.fth (rev 0)
+++ cpu/mips/machdep.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,102 @@
+purpose: Breakpoint support words for MIPS
+\ See license at end of file
+
+: op@ ( adr -- op ) >vmem l@ ;
+: op! ( op adr -- ) >vmem instruction! ;
+: at-breakpoint? ( adr -- flag ) op@ breakpoint-opcode = ;
+: put-breakpoint ( adr -- ) breakpoint-opcode swap op! ;
+
+: j? ( adr -- adr flag ) h# 0800.0000 h# fc00.0000 imatch? ;
+: jr? ( adr -- adr flag ) h# 0000.0008 h# fc00.003f imatch? ;
+: branch? ( adr -- flag )
+ h# 1000.0000 h# b000.0000 imatch? >r \ beq(l),bne(l),blez(l),bgtz(l)
+ h# 0400.0000 h# fc1c.0000 imatch? \ bltz,bgez,bltzl,bgezl
+ r> or
+;
+
+: delayed? ( adr -- flag )
+ j? swap jr? swap jal? swap jalr? swap bal? swap branch? swap
+ drop or or or or or
+;
+: .instruction ( -- )
+ $pc
+ [ also disassembler ] pc ! dis1 [ previous ]
+ $pc delayed? if
+ $pc la1+ [ also disassembler ] pc ! dis1 [ previous ]
+ then
+;
+
+\ Find the places to set the next breakpoint for single stepping.
+\ Usually the right place is at nPC . However, for annulled branch
+\ instructions, we have to cope with the possibility that the delay
+\ instruction, which is where nPC points, won't be executed. Annulled
+\ unconditional branches never execute the delay instruction, so we have
+\ to put the breakpoint at the branch target. Annulled conditional
+\ branches will either execute the delay instruction or the one right
+\ after it.
+
+: >after-delay ( adr -- adr' ) 2 la+ ;
+variable step?
+: next-instruction ( stepping? -- next-adr branch-target|0 )
+ step? !
+ $pc
+ j? if >j-target 0 exit then
+ jr? if >jr-target 0 exit then
+ jal? if step? @ if >j-target else >after-delay then 0 exit then
+ jalr? if step? @ if >jr-target else >after-delay then 0 exit then
+ bal? if
+ step? @ if dup >after-delay swap >br-target else >after-delay 0 then
+ exit
+ then
+ branch? if dup >after-delay swap >br-target exit then
+ la1+ 0
+;
+: bumppc ( -- ) $pc la1+ to $pc ;
+alias rpc $pc
+
+code goto ( adr -- )
+ tos t0 move
+ sp tos get
+ t0 jr
+ sp /n sp add
+end-code
+
+: return-adr ( -- adr ) $ra ;
+: leaf-return-adr ( -- adr ) $ra ;
+: backward-branch? ( adr -- flag ) \ True if adr points to a backward branch
+ l@ ( instruction )
+ dup branch? ( instruction branch? )
+ swap h# 0000.8000 and 0<> ( branch? backward? )
+ and
+;
+: loop-exit-adr ( -- adr )
+ \ Start at PC-4 in case we're sitting on a delay instruction at the loop end
+ $pc 4 - begin dup backward-branch? 0= while 4 + repeat 8 +
+;
+
+headers
+: set-pc ( adr -- ) to $pc ;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/makeinflater.notes
===================================================================
--- cpu/mips/makeinflater.notes (rev 0)
+++ cpu/mips/makeinflater.notes 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,14 @@
+The inflater is made with a GCC cross compiler.
+
+To build inflate.img, the following worked at one point (the GCC options might have changed since then):
+
+cd ${BP}/cpu/mips/Linux
+mipsel-gcc -ffreestanding -nostdlib -mips=rm52xx -mips1 -mno-abicalls -membedded-data -g0 -EL -mno-long-calls -c ${BP}/tools/inflate.c
+mipsel-ld -oformat elf32-littlemips -EL -G0 -N -Ttext=80100000 inflate.o -o inflate.elf
+mipsel-objcopy -O binary inflate.elf inflate.img
+
+The above lines make an image which should be loaded at absolute address 8010.0000.
+Should that be different, the change would have to be reflected in:
+
+ ${BP}/cpu/mips/basefw.bth
+ ${BP}/cpu/mips/bonito/reset.bth (and any other reset.bth that loads the inflater)
Added: cpu/mips/metainit.fth
===================================================================
--- cpu/mips/metainit.fth (rev 0)
+++ cpu/mips/metainit.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,78 @@
+purpose: Initialize the metacompiler for MIPS
+\ See license at end of file
+
+\ Metacompiler initialization
+
+\ Debugging aids
+
+0 #words ! d# 1000 threshold ! 10 granularity !
+
+warning off
+forth definitions
+: unixname bl word
+ drop
+\ ". cr
+;
+
+metaon
+meta definitions
+\ show? on
+
+\ We want the kernel to be romable, so we put variables in the user area
+:-h variable ( -- ) nuser ;-h
+alias \m \
+
+initmeta
+
+th 11000 alloc-mem target-image \ Allocate space for the target image
+
+\ org sets the lowest address that is used by Forth kernel.
+hex
+
+0.0000 org 0.0000
+ voc-link-t token-t!
+
+200 equ ps-size
+
+assembler
+
+\ This is at the first location in the Forth image.
+
+\ init-forth is the initialization entry point. It should be called
+\ exactly once, with arguments (dictionary_start, dictionary_size).
+\ init-forth sets up some global variables which allow Forth to locate
+\ its RAM areas, including the data stack, return stack, user area,
+\ cpu-state save area, and dictionary.
+
+hex
+mlabel cld
+ 9000 bra \ The address will be fixed later.
+ nop \ Delay slot
+ nop
+ nop
+
+meta
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/metarel.fth
===================================================================
--- cpu/mips/metarel.fth (rev 0)
+++ cpu/mips/metarel.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,51 @@
+purpose: Maintain a byte swap table for metacompiling for MIPS
+\ See license at end of file
+
+
+only forth also meta also definitions
+
+hex debug $really-header-t
+h# 10000 constant max-kernel-t
+
+\ The swap map has one bit for every 32-bit word, since we assume
+\ that relocated longwords must start on a 32-bit boundary
+d# 32 constant bits/swapbit-t
+
+\ Number of bytes in bitmap
+: >swap-map-size-t ( end-adr -- )
+ origin-t - bits/swapbit-t /mod swap if 1+ then
+;
+
+max-kernel-t >swap-map-size-t constant /swap-map-t \ Number of bytes in bitmap
+/swap-map-t buffer: swap-map-t
+
+: set-swap-bit-t ( addr -- ) origin-t - 2 >> swap-map-t bitset ;
+: note-string-t ( adr len -- adr len )
+ 2dup bounds ?do i set-swap-bit-t /n +loop
+;
+
+: init-swap-t ( -- ) swap-map-t /swap-map-t erase ;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/objsup.fth
===================================================================
--- cpu/mips/objsup.fth (rev 0)
+++ cpu/mips/objsup.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,147 @@
+purpose: MIPS support routines for the objects package.
+\ See license at end of file
+
+\ implementation.
+
+\ Assembles the common code executed by actions. That code
+\ extracts the next token (which is the acf of the object) from the
+\ code stream, and leaves the corresponding apf in scr
+
+headerless
+
+: start-code ( -- ) code-cf !csp ;
+
+\ Assembles the code which begins a ;code clause
+\ For MIPS, the acf of the child word is left in w
+: start-;code ( -- ) start-code ;
+
+\ Code for executing an object action. Extracts the next token
+\ (which is the apf of the object) from the code stream and pushes
+\ it on the stack. Then performs the action of "docolon".
+
+\ The Forth token stream contains a pointer to the code:
+\ doaction call sp adec
+: doaction ( -- ) acf-align colon-cf ;
+
+\ Returns the address of the code executed by the word whose code field
+\ address is acf
+: >code-adr ( acf -- code-adr ) token@ ;
+
+code >action-adr ( object-acf action# -- )
+ ( ... -- object-acf action# #actions true | object-apf action-adr false )
+ \ action# in tos
+ sp t0 get \ object-acf in scr
+ bubble
+ \ Make sure it's a does> word
+ t0 0 t1 lw \ code-field token
+ t1 ' forth @ cmpi
+ $at $0 <> if nop
+ sp -4 sp addiu \ Make room on stack
+ sp -4 sp addiu \ The error case needs more room on the stack
+ tos sp 4 sw \ Place action# on stack
+ $0 sp 0 sw \ Place #actions on stack
+ next
+ then
+
+ t0 4 t1 lw \ code offset in t1
+ bubble
+ t1 base t1 addu \ code address in t1
+ t1 -4 t2 lw \ #actions in t2
+ bubble
+ t2 tos cmp \ Test action
+ $at 0<= if \ "true" branch is error
+ sp -4 sp addiu \ Make room on stack (delay slot)
+ sp -4 sp addiu \ The error case needs more room on the stack
+ tos sp 4 sw \ Place action# on stack
+ t2 sp 0 sw \ Place #actions on stack
+ else
+ true tos move \ Return true for error (delay)
+
+ t0 /token 2* t0 addiu \ Compute action-apf from action-acf
+ t0 sp 4 sw \ Put action-apf on stack
+
+ tos 2 tos sll \ Convert #actions to token offset
+ t1 tos t1 subu \ Skip back several tokens
+ t1 -4 t1 lw \ Get action-adr token, -4 skips action# field
+ t1 base t1 addu \ Relocate
+ t1 sp 0 sw \ Put action-adr on stack
+ false tos move \ Return false for no error
+ then
+c;
+
+headers
+: action-name \ name ( action# -- )
+ create \ Store action number in data field
+ l,
+ ;code ( -- object-pfa )
+ tos 0 t0 lw \ Action# in t0
+
+
+ ip 0 t1 lw \ Object acf in t1
+ ip /token ip addiu \ Advance to next token
+ t1 base t1 addu \ Relocate object acf
+
+ t1 /token 2* tos addiu \ Compute and push object-apf
+
+ t1 /token t1 lw \ relative version of ..
+ t1 base t1 addu \ default action code address
+
+ t0 2 t0 sll \ Convert action# to token offset
+ t1 t0 t1 subu \ Skip back action# tokens
+ t1 -1 /n* w lw \ Get action-adr token
+
+ w base w addu \ Tail of "next"
+ w 0 t1 lw
+ bubble
+ t1 base t1 addu
+ t1 jr
+ nop
+end-code
+
+: >action# ( apf -- action# ) l@ ;
+
+\ Some examples of object actions defined in code.
+\ 3 actions
+\ action-code
+\ apf w lw bubble w base w addu
+\ w 0 t1 lw bubble t1 base t1 addu
+\ t1 jr nop
+\ end-code
+\ action: token! ; \ is
+\ action: ; \ addr
+\ : defer \ name ( -- )
+\ create ['] crash token,
+\ use-actions
+\ ;
+\ 3 actions
+\ action-code tos sp push apf tos lw c; \ Default; fetch
+\ action-code tos apf sw sp tos pop c; \ to
+\ action-code tos sp push apf tos addiu c; \ addr
+\ : value \ name ( initial-value -- )
+\ create ,
+\ use-actions
+\ ;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/pause.fth
===================================================================
--- cpu/mips/pause.fth (rev 0)
+++ cpu/mips/pause.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,58 @@
+purpose: MIPS code words for multitasking
+\ See license at end of file
+
+ tos sp push
+ ip 'user saved-ip sw
+ rp 'user saved-rp sw
+ sp 'user saved-sp sw
+
+ 'user link up lw \ get up for new task
+ bubble
+ 'user entry t0 lw \ get pc for new task
+ bubble
+ t0 jr
+ nop
+end-code
+
+label to-next-task (s -- address-of-"next-task"-code )
+ 'user link up lw \ get up for new task
+ bubble
+ 'user entry t0 lw \ get pc for new task
+ bubble
+ t0 jr
+ nop
+end-code
+
+\ Called with up set to the user area address of the task to run
+label task-resume (s -- ) \ start a task
+ tos sp push
+ 'user saved-ip ip lw
+ 'user saved-rp rp lw
+ 'user saved-sp sp lw
+ bubble
+ sp tos pop
+c;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/physaddr.fth
===================================================================
--- cpu/mips/physaddr.fth (rev 0)
+++ cpu/mips/physaddr.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,34 @@
+purpose: Physical addresses for generic MIPS system
+\ See license at end of file
+
+headerless
+
+h# 0000.0000 constant ram-pa
+h# 1fc0.0000 constant rom-pa
+
+h# 400 constant /resetjmp
+headers
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/probemem.fth
===================================================================
--- cpu/mips/probemem.fth (rev 0)
+++ cpu/mips/probemem.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,73 @@
+purpose: Memory probing
+\ See license at end of file
+
+: (memory?) ( adr -- flag ) /ram-bank u< ;
+' (memory?) to memory?
+
+" /memory" find-device
+
+headerless
+
+h# ffff.ffff value low
+h# 0 value high
+
+: log&release ( adr len -- )
+ over low umin to low ( adr len )
+ 2dup + high umax to high ( adr len )
+ release
+;
+
+: scan-banks ( base mask -- )
+ d# 32 0 do ( base mask )
+ dup 1 and if ( base mask )
+ over /ram-bank log&release ( base mask )
+ then ( base mask )
+ swap /ram-bank + swap 1 rshift ( base' mask' )
+ loop ( base mask )
+ 2drop
+;
+0 value membanks
+headers
+: claim ( [ phys ] size align -- kseg0-adr ) claim kseg0 + ;
+
+: probe ( -- )
+ ram-pa bank-mask @ scan-banks
+
+ 0 0 encode-bytes ( adr 0 )
+ physavail ['] make-phys-memlist find-node ( adr len prev 0 )
+ 2drop " reg" property
+
+ \ Claim the megabyte used for the trap vectors, Forth, and the section table
+[ifdef] ram-image
+ 0 rom-base /rom + 0 claim drop
+[else]
+ 0 /resetjmp 0 claim drop
+[then]
+ high h# 10.0000 - h# 10.0000 0 claim drop
+;
+
+device-end
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/r4000cp0.fth
===================================================================
--- cpu/mips/r4000cp0.fth (rev 0)
+++ cpu/mips/r4000cp0.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,73 @@
+purpose: Coprocessor 0 registers for MIPS R4000 series
+\ See license at end of file
+
+code index! ( #ticks -- ) 0 tos mtc0 sp tos pop c;
+code index@ ( -- #ticks ) tos sp push 0 tos mfc0 c;
+code random@ ( -- #ticks ) tos sp push 1 tos mfc0 c;
+code entrylo0! ( #ticks -- ) 2 tos mtc0 sp tos pop c;
+code entrylo0@ ( -- #ticks ) tos sp push 2 tos mfc0 c;
+code entrylo1! ( #ticks -- ) 3 tos mtc0 sp tos pop c;
+code entrylo1@ ( -- #ticks ) tos sp push 3 tos mfc0 c;
+code context! ( #ticks -- ) 4 tos mtc0 sp tos pop c;
+code context@ ( -- #ticks ) tos sp push 4 tos mfc0 c;
+code pagemask! ( #ticks -- ) 5 tos mtc0 sp tos pop c;
+code pagemask@ ( -- #ticks ) tos sp push 5 tos mfc0 c;
+code wired! ( #ticks -- ) 6 tos mtc0 sp tos pop c;
+code wired@ ( -- #ticks ) tos sp push 6 tos mfc0 c;
+code badvaddr@ ( -- #ticks ) tos sp push 8 tos mfc0 c;
+code count! ( #ticks -- ) 9 tos mtc0 sp tos pop c;
+code count@ ( -- #ticks ) tos sp push 9 tos mfc0 c;
+code entryhi! ( n -- ) d# 10 tos mtc0 sp tos pop c;
+code entryhi@ ( -- n ) tos sp push d# 10 tos mfc0 c;
+code compare! ( n -- ) d# 11 tos mtc0 sp tos pop c;
+code compare@ ( -- n ) tos sp push d# 11 tos mfc0 c;
+code sr! ( n -- ) d# 12 tos mtc0 sp tos pop c;
+code sr@ ( -- n ) tos sp push d# 12 tos mfc0 c;
+code cause! ( n -- ) d# 13 tos mtc0 sp tos pop c;
+code cause@ ( -- n ) tos sp push d# 13 tos mfc0 c;
+code epc! ( n -- ) d# 14 tos mtc0 sp tos pop c;
+code epc@ ( -- n ) tos sp push d# 14 tos mfc0 c;
+code prid@ ( -- n ) tos sp push d# 15 tos mfc0 c;
+code config! ( n -- ) d# 16 tos mtc0 sp tos pop c;
+code config@ ( -- n ) tos sp push d# 16 tos mfc0 c;
+code lladdr! ( n -- ) d# 17 tos mtc0 sp tos pop c;
+code lladdr@ ( -- n ) tos sp push d# 17 tos mfc0 c;
+code watchlo! ( n -- ) d# 18 tos mtc0 sp tos pop c;
+code watchlo@ ( -- n ) tos sp push d# 18 tos mfc0 c;
+code watchhi! ( n -- ) d# 19 tos mtc0 sp tos pop c;
+code watchhi@ ( -- n ) tos sp push d# 19 tos mfc0 c;
+code xcontext! ( n -- ) d# 20 tos mtc0 sp tos pop c;
+code xcontext@ ( -- n ) tos sp push d# 20 tos mfc0 c;
+code perr! ( n -- ) d# 26 tos mtc0 sp tos pop c;
+code perr@ ( -- n ) tos sp push d# 26 tos mfc0 c;
+code cacherr@ ( -- n ) tos sp push d# 27 tos mfc0 c;
+code taglo! ( n -- ) d# 28 tos mtc0 sp tos pop c;
+code taglo@ ( -- n ) tos sp push d# 28 tos mfc0 c;
+code taghi! ( n -- ) d# 29 tos mtc0 sp tos pop c;
+code taghi@ ( -- n ) tos sp push d# 29 tos mfc0 c;
+code errorepc! ( n -- ) d# 30 tos mtc0 sp tos pop c;
+code errorepc@ ( -- n ) tos sp push d# 30 tos mfc0 c;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/regacc.fth
===================================================================
--- cpu/mips/regacc.fth (rev 0)
+++ cpu/mips/regacc.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,37 @@
+purpose: Register access words
+\ See license at end of file
+
+\ We assume that all devices of interest are mapped suitably for I/O
+
+defer rx@ ' x@ is rx@ ( addr -- d )
+defer rx! ' x! is rx! ( d addr -- )
+defer rl@ ' l@ is rl@ ( addr -- l )
+defer rl! ' l! is rl! ( l addr -- )
+defer rw@ ' w@ is rw@ ( addr -- w )
+defer rw! ' w! is rw! ( w addr -- )
+defer rb@ ' c@ is rb@ ( addr -- b )
+defer rb! ' c! is rb! ( b addr -- )
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/register.fth
===================================================================
--- cpu/mips/register.fth (rev 0)
+++ cpu/mips/register.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,167 @@
+purpose: Buffers for saving program state
+\ See license at end of file
+
+\ Display and modify the saved state of the CPU.
+\
+\ This code is highly machine-dependent.
+\
+\ Requires:
+\
+\ >state ( offset -- addr )
+\ Returns an address within the processor state array given the
+\ offset into that array
+\
+\ Defines:
+\
+\ %g0 .. %g7 %o0 .. %o7 %l0 .. %l7 %i0 .. %i7
+\ %pc %hi %lo
+\ .registers .locals
+
+needs action: objects.fth
+
+also hidden
+alias reasonable-ip? reasonable-ip?
+previous
+
+decimal
+
+only forth hidden also forth also definitions
+
+: /x* ( n1 -- n2 ) 3 lshift ;
+
+: >state ( offset -- adr ) /x* cpu-state + ;
+
+false value x-registers?
+
+3 actions
+action: @ >state x@ x-registers? 0= if drop then ;
+action: @ >state x-registers? 0= if swap s>d rot then x! ; ( is )
+action: @ >state ; ( addr )
+: reg \ name ( offset -- )
+ create ,
+ use-actions
+;
+: regs \ name name ... ( high low -- )
+ bounds ?do i reg loop
+;
+
+\ This mimics the layout of the sigcontext structure
+
+ 0 3 regs $regmask $sigmask $pc
+
+\ 3 16 regs $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $10 $11 $12 $13 $14 $15
+ 3 16 regs $0 $at $v0 $v1 $a0 $a1 $a2 $a3 $t0 $t1 $t2 $t3 $t4 $t5 $t6 $t7
+
+\ 19 16 regs $16 $17 $18 $19 $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $30 $31
+19 16 regs $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $t8 $t9 $k0 $k1 $gp $sp $s8 $ra
+22 4 regs $up $tos $ip $rp
+
+35 reg $fpowned
+36 8 regs $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7
+44 8 regs $f8 $f9 $f10 $f11 $f12 $f13 $f14 $f15
+52 8 regs $f16 $f17 $f18 $f19 $f20 $f21 $f22 $f23
+60 8 regs $f24 $f25 $f26 $f27 $f28 $f29 $f30 $f31
+
+68 2 regs $fcsr $feir
+70 2 regs $hi $lo
+
+72 6 regs $cause $badvaddr $badpaddr $sigset $triggersave $ssflags
+
+78 2 regs exception# $sigcode
+80 3 regs %saved-my-self %state-valid %restartable?
+83 1 regs $sr
+
+d# 84 /x* to /save-area
+
+\ These could be defined as e.g. "addr %restartable?", but that
+\ causes problems when compiling with SPIM, which can't execute
+\ code words that were recently incrementally compiled.
+: saved-my-self ( -- addr ) d# 80 >state ;
+: state-valid ( -- addr ) d# 81 >state ;
+: restartable? ( -- addr ) d# 82 >state ;
+: ?saved-state ( -- )
+ state-valid @ 0= abort" No program state has been saved in this session."
+;
+
+: .lx ( l -- ) push-hex 9 u.r pop-base ;
+: .xx ( d -- ) push-hex d# 17 ud.r pop-base ;
+
+: .registers ( -- )
+ ?saved-state
+ ??cr
+." $pc $hi $lo $sr" cr
+ $pc .lx $hi .lx $lo .lx $sr .lx
+cr cr
+." $0 $at $v0 $v1 $a0 $a1 $a2 $a3" cr
+ $0 .lx $at .lx $v0 .lx $v1 .lx $a0 .lx $a1 .lx $a2 .lx $a3 .lx
+cr cr
+." $t0 $t1 $t2 $t3 $t4 $t5 $t6 $t7" cr
+ $t0 .lx $t1 .lx $t2 .lx $t3 .lx $t4 .lx $t5 .lx $t6 .lx $t7 .lx
+cr cr
+." $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7" cr
+ $s0 .lx $s1 .lx $s2 .lx $s3 .lx $s4 .lx $s5 .lx $s6 .lx $s7 .lx
+cr cr
+." $t8 $t9 $k0 $k1 $gp $sp $s8 $ra" cr
+ $t8 .lx $t9 .lx $k0 .lx $k1 .lx $gp .lx $sp .lx $s8 .lx $ra .lx
+cr cr
+;
+
+: .xregisters ( -- )
+ ?saved-state
+ x-registers? >r true to x-registers?
+ ??cr
+." $pc $hi $lo $sr" cr
+ $pc .xx $hi .xx $lo .xx $sr .xx
+cr cr
+." $0 $at $v0 $v1" cr
+ $0 .xx $at .xx $v0 .xx $v1 .xx
+cr cr
+." $a0 $a1 $a2 $a3" cr
+ $a0 .xx $a1 .xx $a2 .xx $a3 .xx
+cr cr
+." $t0 $t1 $t2 $t3" cr
+ $t0 .xx $t1 .xx $t2 .xx $t3 .xx
+cr cr
+." $t4 $t5 $t6 $t7" cr
+ $t4 .xx $t5 .xx $t6 .xx $t7 .xx
+cr cr
+." $s0 $s1 $s2 $s3" cr
+ $s0 .xx $s1 .xx $s2 .xx $s3 .xx
+cr cr
+." $s4 $s5 $s6 $s7" cr
+ $s4 .xx $s5 .xx $s6 .xx $s7 .xx
+cr cr
+." $t8 $t9 $k0 $k1" cr
+ $t8 .xx $t9 .xx $k0 .xx $k1 .xx
+cr cr
+." $gp $sp $s8 $ra" cr
+ $gp .xx $sp .xx $s8 .xx $ra .xx
+cr cr
+ r> to x-registers?
+;
+
+only forth also definitions
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/resetjmp.bth
===================================================================
--- cpu/mips/resetjmp.bth (rev 0)
+++ cpu/mips/resetjmp.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,106 @@
+purpose: Reset vector handler
+\ See license at end of file
+
+command: &native &this
+build-now
+
+\needs start-assembling fload ${BP}/cpu/mips/asmtools.fth
+
+\ The size of this module affects the constant /resetjmp in
+\ physaddr.fth.
+
+start-assembling
+
+hex
+
+label resetvec
+ \ **** This is the initial entry point (reset vector) for the ROM.
+ \ It just branches past the following copyright string and past the
+ \ dropin module header for the "resetvec" dropin module, landing at
+ \ the entry point for that module. The "resetvec" dropin module
+ \ must appear in the ROM image right after the image that this file
+ \ creates.
+ here h# 420 + $0 $0 beq
+ nop
+
+end-code
+
+ \ This copyright string will appear in the ROM right after the branch
+ \ instruction.
+ " Copyright 2001 FirmWorks All Rights Reserved" c$,
+
+ \ Locations 56-5b are reserved for a MAC address, for systems
+ \ that wish to store the MAC address in the boot ROM instead of
+ \ in a UID EEPROM.
+ h# 56 pad-to
+ h# ff c, h# ff c, h# ff c, h# ff c, h# ff c, h# ff c,
+
+ \ We reserve ROM locations 5c-5f for the PROMICE AI port and place
+ \ a distinct signature there. If the AI port is present and enabled
+ \ at those locations, it will overlay the ROM contents, thus allowing
+ \ the software to determine whether or not the AI port is present.
+
+ \ The signature should be tested at offset 5c+3 (5f), which is the
+ \ AI port status register. The value d4 is present at both 5c+0
+ \ and 5c+3, in case we ever have to handle big-endian systems that
+ \ byte-swap the ROM in some modes.
+
+ h# 5c pad-to \ Pad to the location reserved for the AI port
+ h# d4 c, h# 5a c, h# 5b c, h# d4 c, \ Signature distinct from AI port
+
+ h# 200 pad-to
+label tlbrefill
+ here h# 220 + $0 $0 beq
+ nop
+end-code
+
+ h# 280 pad-to
+label xtlbrefill
+ here h# 1a0 + $0 $0 beq
+ nop
+end-code
+
+ h# 300 pad-to
+label cacheerr
+ here h# 120 + $0 $0 beq
+ nop
+end-code
+
+ h# 380 pad-to
+label generalexc
+ here h# a0 + $0 $0 beq
+ nop
+end-code
+
+ h# 400 pad-to
+ \ This module must have a fixed size of /resetjmp
+
+end-assembling
+
+writing resetjmp.img
+asm-base here over - ofd @ fputs
+ofd @ fclose
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/rootnode.fth
===================================================================
--- cpu/mips/rootnode.fth (rev 0)
+++ cpu/mips/rootnode.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,191 @@
+purpose: Methods for the root node using MIPS Kseg address translation
+\ See license at end of file
+
+: root-map-in ( phys len -- virt )
+ " /" " map-in" execute-device-method drop
+;
+: root-map-out ( virt len -- )
+ " /" " map-out" execute-device-method drop
+;
+
+dev /
+extend-package
+
+[ifdef] 2-cell-rootnode 2 [else] 1 [then]
+encode-int " #address-cells" property
+
+0 0 encode-bytes
+ h# 8000.0000 encode-int encode+ \ Base address
+[ifdef] 2-cell-rootnode
+ 0 encode-int encode+
+[then]
+ h# 0200.0000 encode-int encode+ \ Size
+" dma-ranges" property
+
+hex
+headers
+
+\ Static methods
+: decode-unit ( adr len -- phys )
+ push-hex
+[ifdef] 2-cell-rootnode
+ $dnumber? case
+ 0 of 0. endof
+ 1 of 0 endof
+ 2 of endof
+ endcase
+[else]
+ $number if 0 then
+[then]
+ pop-base
+;
+: encode-unit ( phys -- adr len )
+ push-hex
+[ifdef] 2-cell-rootnode
+ <# #s #>
+[else]
+ (u.)
+[then]
+ pop-base
+;
+
+\ Not-necessarily-static methods
+: open ( -- true ) true ;
+: close ( -- ) ;
+
+: map-in ( phys size -- virt )
+ drop ( phys.low phys.high )
+[ifdef] 2-cell-rootnode
+ 0= over h# 2000.0000 u>= or
+[else]
+ dup h# 2000.0000 u>=
+[then]
+ abort" Can't map addresses > (hex) 2000.0000"
+ kseg1 or
+;
+: map-out ( virtual size -- ) 2drop ;
+
+headerless
+list: dmalist
+listnode
+ /n field >dma-ua \ address obtained from alloc-mem, unaligned
+ /n field >dma-aa \ address passed on to caller, cache-line aligned
+ /n field >dma-len \ original length used to alloc-mem
+nodetype: dmanode
+
+0 dmalist !
+0 dmanode !
+0 value dma-aa
+
+: dma-aa=? ( node -- aa=? )
+ >dma-aa @ dma-aa =
+;
+: find-dmanode? ( -- prev-node this-node|0 )
+ dmalist ['] dma-aa=? find-node
+;
+: alloc-dmanode ( -- node )
+ dmanode allocate-node dup dmalist last-node insert-after
+;
+: free-dmanode ( prev -- )
+ delete-after dmanode free-node
+;
+
+headers
+
+[ifndef] prepare-dma-range
+\ This is the default version, appropriate for systems without hardware
+\ cache coherency between the CPU and DMA
+: prepare-dma-range ( size ua aa -- size ua dma-aa )
+ over 3 pick flush-d$-range ( size ua aa ) \ Remove from cache
+ kseg1 or
+;
+[then]
+
+\ Many MIPS systems require, or at least prefer, that DMA memory is
+\ aligned on cache line boundaries.
+: dma-alloc ( size -- virt )
+ /cache-line + /cache-line round-up dup ( size' size' )
+ alloc-mem ( size ua )
+ dup /cache-line round-up ( size ua aa )
+ prepare-dma-range ( size ua dma-aa )
+ dup >r ( size ua aa ) ( R: aa )
+ alloc-dmanode ( size ua aa node ) ( R: aa )
+ tuck >dma-aa ! ( size ua node ) ( R: aa )
+ tuck >dma-ua ! ( size node ) ( R: aa )
+ >dma-len ! ( ) ( R: aa )
+ r>
+;
+: dma-free ( virt size -- )
+ over to dma-aa find-dmanode? dup if
+ dup >dma-ua @ swap >dma-len @ free-mem
+ free-dmanode 2drop
+ else
+ 2drop free-mem
+ then
+;
+: dma-map-in ( virt size cacheable -- devaddr )
+ drop 2dup pcicache-wbinv
+ drop h# 1fff.ffff and
+ [ifdef] 2-cell-rootnode 0 [then]
+;
+: dma-map-out ( virt devaddr size -- ) pcicache-wbinv drop ;
+: dma-sync ( virt devaddr size -- ) pcicache-wbinv drop ;
+: dma-push ( virt devaddr size -- ) pcicache-inv drop ;
+: dma-pull ( virt devaddr size -- ) pcicache-wbinv drop ;
+
+finish-device
+
+device-end
+
+headerless
+\ Call this after the system-mac-address is determined, which is typically
+\ done near the end of the probing process.
+: set-system-id ( -- )
+ system-mac-address dup if ( adr 6 )
+ " /" find-device ( adr 6 )
+
+ \ Convert the six bytes of the MAC address into a string of the
+ \ form 0NNNNNNNNNN, where N is an uppercase hex digit.
+ push-hex ( adr 6 )
+
+ <# bounds swap 1- ?do ( )
+ i c@ u# u# drop ( )
+ -1 +loop ( )
+ 0 u# u#> ( adr len )
+
+ 2dup upper ( adr len ) \ Force upper case
+
+ pop-base ( adr len )
+
+ encode-string " system-id" property ( )
+
+ device-end
+ else
+ 2drop
+ then
+;
+headers
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/savefort.fth
===================================================================
--- cpu/mips/savefort.fth (rev 0)
+++ cpu/mips/savefort.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,112 @@
+purpose: Save dictionary to a file for MIPS
+\ See license at end of file
+
+\ save-forth ( filename -- )
+\ Saves the Forth dictionary to a file so it may be later used under Unix
+\
+\ save-image ( header-adr header-len init-routine-name filename -- )
+\ Primitive save routine. Saves the dictionary image to a file.
+\ The header is placed at the start of the file. The latest definition
+\ whose name is the same as the "init-routine-name" argument is
+\ installed as the init-io routine.
+
+only forth also hidden also forth definitions
+
+headerless
+: swap-size ( -- n ) here >swap-map-size ;
+
+\needs lbflip : lbflip ( l1 -- l2 ) lbsplit swap 2swap swap bljoin ;
+variable swap-temp
+: swap-lput ( adr -- )
+ l@ lbflip swap-temp l!
+ swap-temp 4 ofd @ fputs
+;
+: swap-fputs ( adr len -- ) bounds ?do i swap-lput 4 +loop ;
+: ?swap-fputs ( adr len -- )
+ 3 + 2 >> 0 ?do ( adr )
+ dup i la+ ( adr adr' )
+ i swap-map bittest if ( adr adr' )
+ 4 ofd @ fputs ( adr )
+ else ( adr adr' )
+ swap-lput ( adr )
+ then ( adr )
+ loop ( adr )
+ drop
+;
+
+false value swapped-save?
+: save-image ( header header-len init-routine-name filename -- )
+ $new-file
+
+ ( header header-len init-routine-name )
+
+ init-save
+
+ swapped-save? if
+ ( header header-len ) swap-fputs \ Write header
+ origin text-size ?swap-fputs \ Write dictionary
+ up@ user-size swap-fputs \ Write user area
+ else
+ ( header header-len ) ofd @ fputs \ Write header
+ origin text-size ofd @ fputs \ Write dictionary
+ up@ user-size ofd @ fputs \ Write user area
+ then
+ swap-map swap-size ofd @ fputs \ Write swap map
+ ofd @ fclose
+;
+headers
+
+0 value growth-size
+
+: make-bin-header ( -- )
+ 10000007 h_magic l! \ This is a ba,a .+0x20 instruction
+ text-size h_tlen l! \ Set the text size in program header
+ user-size h_dlen l! \ Set the data size in program header
+ growth-size h_blen l! \ Set the bss size in program header
+ 0 h_slen l! \ Set the symbol size in program header
+ origin h_entry l! \ Set the current starting address
+ swap-size h_trlen l! \ Set the relocation size
+;
+
+\ Save an image of the target system in a file.
+: $save-forth ( str -- )
+ 8 (align) \ Make sure image is 8 byte aligned
+
+ 2>r
+
+ make-bin-header
+
+ bin-header /bin-header " sys-init" 2r> save-image
+;
+: $save-forth-swapped ( str -- )
+ true to swapped-save?
+ $save-forth
+ false to swapped-save?
+;
+: save-forth ( str -- ) count $save-forth ;
+
+only forth also definitions
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/savemeta.fth
===================================================================
--- cpu/mips/savemeta.fth (rev 0)
+++ cpu/mips/savemeta.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,115 @@
+purpose: Save metacompiled MIPS kernel to a file
+\ See license at end of file
+
+hex
+only forth labels also forth also definitions
+
+\ Program header
+create header forth
+th 10000007 l, \ Magic number (bra .+32)
+ 0 l, \ Text size, actual value will be set later
+ 0 l, \ Data size, actual value will be set later
+ 0 l, \ Bss size
+ 0 l, \ Symbol Table size
+ 0 l, \ Entry
+ 0 l, \ Text Relocation Size
+ 0 l, \ Data Relocation Size
+\ End of header.
+here header - constant /header
+
+only forth also meta also forth-h also definitions
+
+\ Save an image of the target system in the file whose name
+\ is the argument on the stack.
+
+: doubleword-align ( n -- n' ) 7 + 7 invert and ;
+: text-base ( -- adr ) origin-t >hostaddr ;
+: text-size ( -- n ) here-t origin-t - doubleword-align ;
+: swap-size ( -- n ) here-t >swap-map-size-t ;
+: user-base ( -- adr ) userarea-t ;
+: user-size ( -- n ) user-size-t doubleword-align ;
+
+\needs lbflip : lbflip ( l1 -- l2 ) lbsplit swap 2swap swap bljoin ;
+variable swap-temp
+: swap-lput ( adr -- )
+ l@ lbflip swap-temp l!
+ swap-temp 4 ofd @ fputs
+;
+: swap-fputs ( adr len -- ) bounds ?do i swap-lput 4 +loop ;
+: ?swap-fputs ( adr len -- )
+ 3 + 2 >> 0 ?do ( adr )
+ dup i la+ ( adr adr' )
+ i swap-map-t bittest if ( adr adr' )
+ 4 ofd @ fputs ( adr )
+ else ( adr adr' )
+ swap-lput ( adr )
+ then ( adr )
+ loop ( adr )
+ drop
+;
+
+: $start-save ( filename$ -- )
+ \ Doubleword alignment is not absolutely required, but may turn out to
+ \ be useful if we ever do a 64-bit implementation.
+ begin here-t 7 and while 0 c,-t repeat
+
+ $new-file
+
+ \ Set the text and data sizes in the program header
+ h# 1000.0007 header h# 0 + l-t! \ Magic number
+ text-size header h# 4 + l-t! \ Text size
+ user-size header h# 8 + l-t! \ Data size
+ 0 header h# 10 + l-t! \ Symbol table size
+
+ 0 header h# 14 + l-t! \ Entry point
+ swap-size header h# 18 + l-t! \ Swap map size
+
+;
+: $save-meta ( filename$ -- )
+ $start-save
+
+ header /header ofd @ fputs
+ text-base text-size ofd @ fputs
+ user-base user-size ofd @ fputs
+
+ swap-map-t swap-size ofd @ fputs \ Swap map
+
+ ofd @ fclose
+;
+: $save-meta-swapped ( filename$ -- )
+ $start-save
+
+ header /header swap-fputs
+ text-base text-size ?swap-fputs
+ user-base user-size swap-fputs
+
+ swap-map-t swap-size ofd @ fputs \ Swap map
+
+ ofd @ fclose
+;
+
+only forth also meta also definitions
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/startup.html
===================================================================
--- cpu/mips/startup.html (rev 0)
+++ cpu/mips/startup.html 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,490 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html>
+<head>
+ <title>Open Firmware Startup on MIPS Processors</title>
+</head>
+ <body>
+
+<h1>Open Firmware Startup on MIPS Processors</h1>
+ This document describes the startup process for Open Firmware on MIPS processors.
+ It summarizes the requirements for MIPS startup and tells how Open Firmware
+code modules can be structured to accomplish the system initialization necessary
+for running the main Open Firmware Forth code.
+<h2>Overview of Open Firmware Structure</h2>
+ The sizes listed below are for the code when it is resident in RAM. When
+in ROM, the code is typically compressed (as with gzip) to about one half
+its uncompressed size.
+<p> The Open Firmware ROM image consists of a sequence of modules in "dropin
+format". Each "dropin module" consists of a 32-byte header and some code
+or data of varying length. The details of dropin module format are described
+in a later section. The various dropin modules are concatenated to form
+the overall ROM image. </p>
+<p> The critical dropin modules are: </p>
+<ul>
+ <li>resetjmp - about 1K </li>
+ <li>reset - about 3K </li>
+ <li>start - variable; perhaps 3K to 25K </li>
+ <li>firmware - about 400K </li>
+</ul>
+
+<h3>The "resetjmp" code</h3>
+ On MIPS processors, the first instruction that is executed after the CPU
+comes out of reset is at the beginning of the ROM, so the first thing in
+the ROM cannot be a dropin module with a proper dropin header. The first
+true dropin module (with a header) is after the code that occupies the exception
+vectors defined by the MIPS hardware specification. The code at the reset
+vector jumps directly to the beginning of first true dropin module, named
+"reset".<br>
+<br>
+The source file that defines this code is "arch/mips/<i>platform</i>/resetjmp.bth".
+ It may also contain entry code for the other ROM exception vectors.
+
+<h3>The "reset" module</h3>
+ The "reset" module is a relatively small (typically about 3K) amount of
+machine code that sequences the execution of other dropin modules to accomplish
+the early startup process. In principle, the "reset" module ought to be
+generic so that the same code could run on any MIPS system, but in practice
+it is somewhat platform specific for two reasons:
+<ol>
+ <li>The reset code must flush the cache, and cache-flushing code varies
+somewhat across different MIPS processors </li>
+ <li>It's useful to include in the reset code some rudimentary debug facilities
+like LED blinking or serial line output; such code is inherently platform-specific.
+ </li>
+</ol>
+Possibly after initializing a diagnostic output device, the reset module
+locates the start module (by searching through the ROM to find a dropin module
+with the named "start" in its header) and calls it (at its beginning address)
+as a subroutine.<br>
+<br>
+The source file that defines this module is "arch/mips/<i>platform</i>/reset.bth".<br>
+
+<h3>The "start" module</h3>
+ The purpose of the start module is to initialize the core logic, memory
+system, and just enough of the I/O system to get a diagnostic serial port
+working. The start module is entirely dependent on the design of the core
+logic hardware, so it must be rewritten for each chip family. Writing and
+debugging the start module is the crucial step in bringing up Open Firmware
+on a new MIPS chipset. A later section of of this document tells how to create
+a start module for a new chipset. In preparation for initializing the memory
+and a serial port, the start module often has to initialize other parts of
+the core logic such as caches, first-level host bridges, etc. In general,
+however, the "start" module initializes just enough to get a memory and serial
+port working. Initialization of secondary devices like interrupt and DMA
+controllers, timers, and most I/O devices is usually left to later code in
+the "firmware" module.<br>
+<br>
+The source file that defines this module is "arch/mips/<i>platform</i>/start.bth".
+If the process of initializing the memory system is relatively simple, the
+entire "start" code might be in that one file. Otherwise, "start.bth" might
+sequence the compilation process of several other files that together implement
+the core logic and memory system startup sequence.<br>
+
+<h3>Loading the "firmware" module</h3>
+ The start modules returns (as from a normal subroutine) to the reset module
+that called it. Subsequent code can then use the RAM memory that the start
+module initialized. The reset module's final task is to locate the "firmware"
+module (by searching ROM for a dropin module named "firmware"), move it into
+RAM, and jump to it. However, there are some complications:
+<ul>
+ <li>The "firmware" module is usually stored in ROM in compressed (gzip) form.
+ If that is the case, the "reset" module must unzip the "firmware" module
+into RAM instead of simply copying it. To do so, the "reset" module locates
+the "inflate" module, copies it into RAM (for faster execution), and calls
+it with the ROM address of the compressed "firmware" module and the RAM address
+where the uncompressed version should be placed. </li>
+ <li>After the "firmware" module has been copied or uncompressed into RAM,
+it is usually necessary to flush the data cache and invalidate the instruction
+cache so the CPU can execute the firmware code. </li>
+</ul>
+ Even if the system has enough ROM to store the "firmware" module in ROM
+uncompressed, there is an advantage to compressing it. The compressed image
+contains a CRC and a redundant length; taken together they constitute a quick
+and effective test of the integrity of ROM and RAM. ROM problems corrupt
+the compressed code stream, which makes the inflater get "out of sync" and
+misread the final length field. RAM problems show up as a CRC mismatch when
+the inflater computes the CRC of the RAM image after uncompressing it.
+<p> It's possible to do more extensive memory tests at this point, but it's
+better to defer them until later, when the full Open Firmware I/O system
+can be used to report the results. </p>
+<h3>The "firmware" module</h3>
+ The firmware module contains the vast majority of the functionality of Open
+Firmware. It is mostly written in Forth, on top of a relatively small assembly
+language kernel that implements the Forth virtual machine. Its basic internal
+structure is that of a Forth "dictionary", which is a set of linked lists.
+ Each such list is called a "vocabulary". The list elements are called "words".
+Each word has a name, an associated action, and optionally some data. A
+particular word's action can be implemented by either a sequence of machine
+code or a sequence of other words. Typically, only the most basic primitive
+operations (add, subtract, branch, copy, etc.) are implemented as machine
+code words.
+<p> The Forth dictionary is incrementally compiled in a layered fashion. Each
+layer is internally complete and self-consistent as far as it goes. </p>
+<h4>The C Wrapper</h4>
+ The same Forth dictionary image can run either as a standalone program on
+the target machine (when it is fulfilling the functions of Open Firmware)
+or as a user program under Linux or another operating system. In this latter
+mode, it requires help from an external program that is called the "C wrapper".
+ The "C wrapper" is an executable program that is compiled from C source
+code. Its job is to provide basic system services like I/O and memory allocation,
+isolating the system-independent Forth dictionary from operating-system-specific
+details such as the system's executable file format.
+<p> The compilation process for the Forth dictionary depends on this technique
+of running Forth as a user process. A basic Forth system runs under Linux
+with the help of the C wrapper program, extends itself by compiling source
+code from files, and saves the extended Forth dictionary into another file.
+ The process can be repeated as necessary, until the resulting file contains
+all the features that are needed for the Open Firmware system that is to
+run on the target system. It can then be embedded within the "firmware"
+dropin module. </p>
+<h4>The Forth Kernel - kernel.dic</h4>
+ The innermost layer is the Forth language kernel. It is a fully-functional
+implementation of the core ANS Forth language. It contains an interactive
+interpreter and an incremental compiler, so it is capable of extending itself
+by compiling new words into its dictionary.
+<p> The Forth kernel implementation contains MIPS machine code sequences,
+so its binary image is specific to the MIPS-32 instruction set architecture.
+The kernel does not contain any code that is specific to particular MIPS processor
+variants or to particular system architectures. It uses only user-level
+MIPs instructions. </p>
+<p> The Forth kernel source code is very stable and almost never needs to
+be changed in order to port Open Firmware to a new platform. The only time
+the kernel source needs to change is to port Open Firmware to a new instruction
+set architecture, and even then most of the kernel files remain unchanged.
+</p>
+<p> The compilation directory for the Forth kernel is fm/cwrapper/mips/build.
+The command for compiling it is </p>
+<pre> build kernel<br></pre>
+ In most cases, you won't need to execute this command explicitly, because
+higher-level builder scripts will do it automatically if necessary. The name
+of the kernel image file is "kernel.dic". The builder script for compiling
+it is "fm/cwrapper/mips/kernel.bth" .
+<h4>(The Metacompiler)</h4>
+ The kernel is compiled from source code that is written in a combination
+of high-level Forth and assembly language. The assembly language code uses
+a simplified postfix syntax that is very easy to parse, so the assembler
+is very simple and small. The program that compiles the Forth kernel is
+called a "metacompiler". It processes source code that is very similar to
+the source code accepted by an ordinary Forth incremental compiler, but the
+metacompiler can do some extra things:
+<ul>
+ <li>It can create a new self-contained Forth system that is separate from
+itself, rather than just being able to add on to an existing Forth dictionary.
+ </li>
+ <li>It can cross-compile a Forth kernel for an instruction set other than
+the instruction set on which the metacompiler is running. </li>
+ <li>It can handle forward references transparently. </li>
+</ul>
+ However, the metacompiler does have one important limitation - it cannot
+handle arbitrary data constructs defined by means of CREATE and DOES>
+(these are advanced Forth features). This limitation makes it difficult
+to metacompile the entire Open Firmware system as one monolithic unit.
+<p> The metacompiler and the simple assembler are both included in the "builder"
+program that is described later. </p>
+<h4>Extended Forth - tools.dic</h4>
+ The layer above the kernel is called "tools.dic", named for the file that
+contains it. Tools.dic is an extended Forth programming environment that
+contains a number of useful tools such as an incremental assembler, a source-level
+debugger, a callfinder, a wordfinder, a line editor with history and command
+completion, and numerous other extensions that go beyond the basic words
+defined by ANS Forth.
+<p> Tools.dic does not include any Open Firmware abstractions such as device
+tree, packages, or FCode. Those are in the next layer up. Tools.dic serves
+as a common Forth language base for both the remainder of the Open Firmware
+build process and also the builder program. </p>
+<p> The compilation directory for tools.dic is fm/cwrapper/mips/build. The
+command for compiling it is </p>
+<pre> build tools<br></pre>
+ In most cases, you won't need to execute this command explicitly, because
+higher-level builder scripts will do it automatically if necessary. The name
+of the image file is "tools.dic". The builder script for compiling it is
+"fm/cwrapper/mips/tools.bth" .
+<h4>Base Firmware - basefw.dic</h4>
+ The layer above tools.dic in the path to Open Firmware is "basefw.dic". Base
+firmware contains the platform-independent parts of the features defined
+by the Open Firmware standard, including the device tree, client interface,
+FCode evaluator, and support packages. It also includes numerous FirmWorks
+extensions such as TCP and filesystem support.
+<p> basefw.dic does not contain any code that is specific to the board-level
+architecture or the devices that may be present on a particular platform.
+Thus the same basefw.dic binary image file can often be used unchanged as
+the basis for building platform-specific Open Firmware implementations for
+multiple platforms that use the same CPU instruction set architecture (i.e.
+MIPS in this case). Porting to a new MIPS platform usually does not require
+modifications to basefw.dic </p>
+<p> Some code modules that are not platform-specific, and thus could be included
+in basefw.dic, are not included because the features that they implement are
+optional. The code itself is platform-independent, but the choice of whether
+or not to include it is platform-specific. </p>
+<p> The compilation directory for basefw.dic is fm/cwrapper/mips/build. The
+command for compiling it is </p>
+<pre> build basefw<br></pre>
+ In most cases, you won't need to execute this command explicitly, because
+higher-level builder scripts will do it automatically if necessary. The name
+of the image file is "basefw.dic". The builder script for compiling it is
+"fm/cwrapper/mips/basefw.bth" .
+<h4>The complete Open Firmware dictionary - fw.dic</h4>
+ The final layer is "fw.dic". It extends basefw.dic to include support for
+a specific target hardware platform. It includes device drivers for core
+devices like timers, interrupt controllers, bus bridges, diagnostic UARTs,
+FLASH chips, and NVRAM devices. It also includes information describing the
+physical address map and other system characteristics. It may include diagnostics
+for manufacturing, field service, and initial system checkout. Optional features
+like support for specific program image formats (e.g. ELF) and file system
+layouts (e.g. Linux ext2) are added at this level. Customer-specific code,
+such as new user interface commands for special system maintenance requirements,
+can be added as well.
+<p> "fw.dic", usually in compressed form, is the body of the "firmware" dropin
+module. </p>
+<p> Drivers for PCI bus devices like mass-storage or network interfaces can
+either be "hard-compiled" into fw.dic or attached externally as separate
+dropin modules in FCode format. The latter is often more convenient for
+devices that are not needed during the early phases of platform initialization.
+</p>
+<p> Most of the porting work for a new platform, apart from the very low
+level code in the "start" module as described above, is done at the fw.dic
+level. </p>
+<p> Even though it contains a great deal of code that is specific to the
+target hardware, it is still possible to run "fw.dic" under the compilation
+operating system via the C wrapper. "fw.dic" contains separate entry points
+and initialization sequences for the two environments (standalone execution
+on the target system and OS-hosted execution on the compilation system).
+The code that accesses target-specific devices is executed only if "fw.dic"
+is entered via its standalone entry point. </p>
+<p> This ability to run "fw.dic" in the OS environment can be quite convenient
+for debugging purposes, because you can use the built-in debugging facilities
+to inspect the code that has actually been compiled. It eliminates the need
+for listings of the compiled code or "dump" files. </p>
+<p> The compilation directory for basefw.dic is arch/mips/<i>platform</i>/build,
+where <i>platform</i> is the name of a directory for a specific target hardware
+platform. The command for compiling it is </p>
+<pre> build fw<br></pre>
+ In most cases, you won't need to execute this command explicitly, because
+the top-level builder script will do it automatically if necessary. The name
+of the image file is "fw.dic". The builder script for compiling it is "arch/mips/<i>platform</i>/fw.bth"
+.
+<h4>The top-level builder script - rom.bth</h4>
+ The file that contains the overall image of the entire contents of ROM (i.e.
+FLASH) is "rom.img". "rom.img" contains a sequence of dropin modules, including
+"resetjmp", "reset", "start", "inflate", "firmware", and usually several
+other modules containing things like FCode drivers for PCI devices.
+<p> The compilation directory for rom.img is arch/mips/<i>platform</i>/build,
+where <i>platform</i> is the name of a directory for a specific target hardware
+platform. The command for compiling it is </p>
+<pre> build rom<br></pre>
+ <b><i>This is the top-level command that you use to recompile Open Firmware.</i></b>
+The name of the image file is "rom.img". The builder script for compiling
+it is "arch/mips/<i>platform</i>/rom.bth" .
+<h3>How MIPS Processors Come Out of Reset</h3>
+ After reset, MIPS processors begin execution at the beginning of ROM at
+virtual address 0xbfc00000. That virtual address corresponds to the physical
+address 0x1fc00000. The virtual-to-physical translation results from the
+"kseg1" translation region, which maps virtual addresses 0xa0000000-0xbfffffff
+to physical addresses 0x0000000-0x1fffffff in uncached mode. Within that
+physical address range, the first half (0x00000000-0x0fffffff) is usually
+for RAM while the second half (0x10000000-0x1fffffff) is for I/O devices.
+<p> Early startup code typically runs from this uncached virtual address range
+until the caches and the memory have been initialized. Thereafter, for faster
+execution, code can be copied into memory where it can execute from the cached
+"kseg0" translation region, which maps the same physical address range to
+the virtual address range from 0x80000000-0x9fffffff. When running from
+kseg0, I/O accesses are still done through the kseg1 addresses, as it is
+rarely correct to cache I/O registers. (In some systems, the hardware permits
+the execution of ROM code in cached mode; on those systems, you can run from
+the kseg0 region before initializing memory.) </p>
+<p> The code at the reset vector must jump to some other location within a
+few instructions, because the other exception vectors are located at nearby
+addresses. The details vary somewhat across different MIPS processors, but
+as a general rule the first 32 instruction locations are always available
+for the reset code. The top end of the ROM exception vector area is typically
+at offset 0x3ff from the beginning of ROM, so the code in the first 32 instructions
+typically jumps to other code at offset 0x400 or above. </p>
+<h3>The Builder</h3>
+ The FirmWorks "builder" program is an integrated tool for managing the Open
+Firmware compilation process. It has these features:
+<ul>
+ <li>Dependency manager (similar in spirit to Unix "make") that
+ <ul>
+ <li>Recompiles only those layers whose source has changed </li>
+ <li>Automatically generates dependency lists during compilation </li>
+ <li>Tracks the files used to help with release engineering tasks </li>
+ </ul>
+ </li>
+ <li>Native and/or cross assemblers </li>
+ <li>Metacompiler for cross-compiling Forth kernels </li>
+ <li>Dropin module creation and inspection tools </li>
+ <li>FCode tokenizer </li>
+ <li>FCode detokenizer </li>
+ <li>General-purpose Forth interpreter/compiler/environment </li>
+</ul>
+
+<h4>Builder scripts - .bth files</h4>
+ Builder scripts look very similar to Forth source code, because the builder
+is just a Forth compiler with the extensions listed above. It is possible
+to convert an ordinary Forth source file into a builder script simply by
+adding two lines near the beginning of the file.
+<p> Builder scripts have the filename extension ".bth", which makes it possible
+for the builder to locate them automatically. Ordinary Forth source code
+files have the extension ".fth". The wildcard pattern "*th" matches both
+Forth source files and builder scripts, which is often convenient when using
+"grep" to search for a particular string. </p>
+<p> Each ".bth" file pertains to a single object file (in contrast to a Makefile,
+which can list numerous "targets" in a single file). There can be (and usually
+are) several ".bth" files in one directory, each pertaining to one target
+object. The base name of the ".bth" file is the same as the base name of
+the target object; for example, if the target image filename is "rom.img",
+the builder script filename is "rom.bth". </p>
+<p> The ".bth" file need not be in the directory where the target will be
+built; when the builder needs to recompile a target object, it will search
+upward from the build directory until it finds an appropriately-named ".bth"
+file. The main purpose of this is to segregate source files and object files
+in different directories. The "keep searching upwards" rule can be used to
+good effect by having a generic ".bth" file in a higher level directory (e.g.
+at the "/mips" level, but specific platforms that need something other than
+the default can override it by making their own version at a lower directory
+level.</p>
+<h4>Builder dependency lines</h4>
+<h4> </h4>
+<p> The only structural difference between a builder script and an ordinary
+Forth source code file is the addition of a few dependency lines near the
+beginning of the file. Those dependency lines give the builder information
+like: </p>
+<ul>
+ <li>Which Forth dictionary file serves as the base for the next phase of
+compilation. </li>
+ <li>Which instruction set architecture is required for compilation </li>
+ <li>Which input files, other than Forth source code files, the script depends
+on. (The builder can automatically determine dependencies on Forth source
+code files.) </li>
+</ul>
+ For example, here are the dependency lines at the beginning of fw.bth.
+<pre>dictionary: ${BP}/cpu/mips/build/basefw.dic<br>command: &mipsfth &dictionary &this<br>build-now<br></pre>
+ The "dictionary:" line says an up-to-date version of the dictionary file
+"${BP}/fm/cwrapper/mips/build/basefw.dic" is needed in order to perform the
+compilation that is defined by the rest of this builder script. If that
+dictionary file is missing or out-of-date with respect to a files it depends
+on, the builder will automatically build it first. "${BP}" is a C wrapper
+macro that expands to the base directory of the firmware source tree. The
+C wrapper automatically locates that base directory by searching up the tree
+from the current build directory.
+<p> The "command:" line tells which operating system command to use to recompile
+the object that this builder script pertains to. In general, it can be any
+shell command, but it is often of the form shown. "&mipsfth" is a builder
+macro that expands to the name of the C wrapper program that is appropriate
+for compiling MIPS code. "&dictionary" expands to the file named on
+the preceding "dictionary:" line, and "&this" expands to the name fo
+the current builder script file. If the object to be compiled is out of
+date with respect to a dependency, that command line (after macro expansion)
+is executed. In this case, the MIPS C wrapper executable program would be
+run, passing to it as command line arguments the name of the base dictionary
+file and the name of the builder script file. </p>
+<p> "build-now" tells the builder that there are no more dependency lines;
+it causes the builder to proceed to check the dependencies and to perform
+any necessary recompillatin. </p>
+<p> The normal Forth compiler treats builder dependency lines as comments.
+The rest of a builder script after the builder lines file contains the Forth
+source code to be compiled. Often that source code consists primarily of
+"fload <i>filename</i>" commands, so the script mostly sequences the compilation
+of other (ordinary) Forth srouce code files. However, that is just a weak
+convention; builder scripts can and do contain arbitrary Forth code after
+the builder command lines. </p>
+<p> The only other type of dependency line that is typically used is "in:
+<i>filename</i>". That line, of which there can be many instances, tells
+the builder that the object to be compiled has a dependency on the indicated
+file. "in:" lines are only necessary for files that are not Forth source
+files. Typically they are used for binary images like pretokenized FCode
+binary files, prebuilt dropin modules, or object files compiled by other
+language processors. </p>
+<h4>Builder .log files</h4>
+ When the Forth compiler writes out a file (typically a ".dic" dictionary
+file), it also writes out a ".log" file with the same base name. That ".log"
+file lists the names and timestamps of all the files that were opened during
+the compilation. (This logging functionality is actually implemented by the
+C wrapper program.) The builder uses the .log files to check dependencies.
+This is how the dependencies are maintained automatically.
+<p> The log files can be deleted at any time without losing any critical
+information. If a log file is missing, the builder won't try to avoid an
+unnecessary recompilation by checking direct dependencies; it will just recompile
+the target anyway. It will, however, first recursively check dependencies
+listed on "dictionary:" and "in:" lines, recompiling them first if necessary.
+</p>
+<h4>The "build" command</h4>
+ The "build" command invokes the builder. "build" itself is a shell script
+whose main function is to locate the correct C wrapper file and builder dictionary
+("native.dic") for the OS and instruction set of the compilation host machine.
+ The builder dictionary files are located in "bin/<i>CPU</i>/native.dic",
+where <i>CPU</i> is the name of the instruction set that the builder dictionary
+runs on. The C wrapper executable files are in "bin/<i>CPU</i>/<i>os</i>/forth",
+where <i>os</i> is an operating system name like "linux". The "build" shell
+script works out the correct values for <i>CPU</i> and <i>os</i> and sets
+the HOSTDIR environment variable to <i>path</i>/bin/<i>CPU</i>/<i>os</i>,
+where <i>path</i> is the path to the root of the Open Firmware source tree.
+ Then it runs the appropriate C wrapper ("forth") with the appropriate build
+dictionary file ("native.dic"), like this:
+<pre> ${HOSTDIR}/forth ${HOSTDIR}/../native.dic <i>arg</i>
+</pre>
+ <i>arg</i> is the argument that was on the "build" command line. It is the
+name of the top-level target object that is to be compiled. The extension
+can be present or absent; "build rom" and "build rom.img" are equivalent.
+<p> If <i>arg</i> is omitted, the builder will run in interactive mode, giving
+you an "ok" prompt from which you can issue Forth commands to invoke any
+of the other builder features. Or you can just use it as a Forth interpreter.
+</p>
+<h3>Language Alternatives for the Start Module</h3>
+ Since its job is to configure and initialize the memory controller, the
+"start" module can be written in any language that can generate code that
+doesn't need RAM memory. The pros and cons of several language choices are
+given below.
+<h4>Forth</h4>
+ Forth code requires a stack to operate, so it's not a viable candidate for
+coding the "start" module.
+<h4>C</h4>
+ With a lot of care, it's possible to write C code that doesn't need memory.
+ You have to use exactly the right compiler flags, limit the number of variables
+and the nesting depth of subroutine calls, and make sure the variables are
+allocated to registers. Even then you often have to edit the assembly language
+output to remove the stack preamble code at the top level. If you switch
+to a new version of the compiler toolchain, you often have to go back and
+change something to keep a memory dependency from creeping in.
+<p> Another technique is to use the cache, without memory backing, as variable
+storage and stack for the C code. That, too, requires some trickery, mastery
+of the compiler switches, and usually some in-line assembly code. But it
+can be worthwhile if the memory controller is so complicated that programming
+it in assembly language is just too difficult. </p>
+<h4>Forth Assembler</h4>
+ The FirmWorks builder program includes a
+<a href=assembler.html>MIPS assembler</a>.
+The syntax is unconventional
+(it is postfix, so the operands are mentioned before the operands),
+but the assembler is small and predictable. You can easily make macros
+so you don't have to write out canned sequences explicitly every time.
+The assembler also has built-in structured conditional macros that mimic
+Forth control flow constructs ( e.g. ... IF ... ELSE ... THEN), so you
+don't have explictly write branch instructions and keep track of labels.
+<p> The Forth assembler is missing some of the more esoteric new MIPS
+instructions, but it's relatively easy to extend it, or you can just insert
+the opcode in the code as a hex number.
+The assembler won't reorder code, so you have to be careful
+with MIPS delayed branches. </p>
+<p> The assembler is well integrated with the builder facilities for
+creating dropin modules, so it's easy to package the resulting binary code
+in the dropin module format. </p>
+<h4>GNU Assembler</h4>
+ The GNU assembler can generate arbitrary machine code sequences as needed.
+ You can assemble the code into an ELF file, extract just the code into an
+raw image file, then use the builder to encapsulate that raw image into a
+dropin module. The disadvantage of this approach is the need to maintain
+an installation of the GNU toolchain in conjunction with the Open Firmware
+build environment (many organizations will be using the GNU toolchain anyway,
+so this may not be a severe disadvantage). One advantage is that many people
+are already familiar with the GNU assembler.
+<h3>Examples</h3>
+
+<h3>Sample fw.bth</h3>
+
+<h3>Dropin Module Format</h3>
+
+<h3>Nanoforth</h3>
+
+</body>
+</html>
Added: cpu/mips/sys.fth
===================================================================
--- cpu/mips/sys.fth (rev 0)
+++ cpu/mips/sys.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,99 @@
+purpose: C wrapper low-level I/O interface
+\ See license at end of file
+
+\ Low-level I/O interface for use with a C "wrapper" program.
+\ The C program provides the Forth kernel with an array of entry-points
+\ into C subroutines for performing the actual system calls.
+\ This scheme should be reasonably compatible with nearly any Unix
+\ implementation. The only difference would be in the implementation of
+\ "syscall", which has to look up the address of the actual system call
+\ C routine in the system call table provided to it by the C program loader.
+\ It then has to convert the stack arguments into the same form as is
+\ expected by the C system call routines. This obviously depends on the
+\ details of the C calling sequence, but should not be too hard because
+\ C compilers usually pass arguments on the stack.
+\ Syscall is defined in the kernel, because it is needed for basics like
+\ key and emit.
+
+decimal
+
+/l ualloc-t dup equ syscall-user#
+user syscall-vec \ long address of system call vector
+nuser sysretval
+
+\ I/O for running under an OS with a C program providing actual I/O routines
+
+meta
+code syscall ( <args> call# -- <args> )
+ \ Get address of system call table
+ 'user syscall-vec t9 lw
+ bubble
+ t9 tos tos addu
+ tos 0 t9 lw \ Address of routine
+
+ sp 0 $a0 lw \ Get some arguments
+ sp 4 $a1 lw
+ sp 8 $a2 lw
+
+ t9 ra jalr
+ sp 12 $a3 lw \ Delay slot
+
+ v0 'user sysretval sw \ Save the result
+
+ sp tos pop \ Fix stack
+c;
+: retval ( -- return_value ) sysretval @ ;
+: lretval ( -- l.return_value ) sysretval l@ ;
+
+nuser errno \ The last system error code
+: error? ( return-value -- return-value error? )
+ dup 0< dup if 60 syscall retval errno ! then ( return-value flag )
+;
+
+\ Rounds down to a block boundary. This causes all file accesses to the
+\ underlying operating system to occur on disk block boundaries. Some
+\ systems (e.g. CP/M) require this; others which don't require it
+\ usually run faster with alignment than without.
+
+\ Aligns to a 512-byte boundary
+hex
+: _falign ( l.byte# fd -- l.aligned ) drop 1ff invert and ;
+: _dfalign ( d.byte# fd -- d.aligned ) drop swap 1ff invert and swap ;
+
+th 1b4 is file-protection \ rw-rw-r-- Unix file protection code
+
+: sys-init-io ( -- )
+ install-wrapper-io
+ install-disk-io
+ \ Don't poll the keyboard under Unix; block waiting for a key
+ ['] (key ['] key (is
+;
+' sys-init-io is init-io
+
+: sys-init ; \ Environment initialization chain
+' sys-init is init-environment
+decimal
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/target.fth
===================================================================
--- cpu/mips/target.fth (rev 0)
+++ cpu/mips/target.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,296 @@
+purpose: Metacompiler target configuration for MIPS
+\ See license at end of file
+
+only forth also meta definitions
+defer init-relocation-t
+defer set-relocation-bit-t
+
+decimal
+
+h# c000 constant max-kernel \ Maximum size of the kernel
+
+only forth also meta assembler definitions
+: normal ( -- ) \ Perform target-dependent assembler initialization
+;
+
+only forth also meta definitions
+
+: lobyte h# 0ff and ;
+: hibyte 8 >> lobyte ;
+
+2 constant /w-t
+4 constant /l-t
+/l-t constant /n-t
+/l-t constant /a-t
+/a-t constant /thread-t
+/l-t constant /token-t
+/l-t constant /link-t
+/token-t constant /defer-t
+/n-t h# 800 * constant user-size-t
+/n-t h# 100 * constant ps-size-t
+/n-t h# 100 * constant rs-size-t
+/l-t constant /user#-t
+
+\ 32 bit host Forth compiling 32-bit target Forth
+: l->n-t ; immediate
+: n->l-t ; immediate
+: n->n-t ; immediate
+: s->l-t ; immediate
+
+: c!-t ( n adr -- ) >hostaddr c! ;
+: c@-t ( adr -- n ) >hostaddr c@ ;
+
+[ifdef] little-endian-t
+\ little-endian versions
+: w!-t ( n add -- ) over lobyte over c!-t ca1+ swap hibyte swap c!-t ;
+: l!-t ( l add -- ) >r lwsplit swap r@ w!-t r> /w-t + w!-t ;
+: w@-t ( target-address -- n ) dup c@-t swap 1+ c@-t 8 << or ;
+: l@-t ( target-address -- n ) dup >r /w-t + w@-t r> w@-t swap wljoin ;
+[else]
+\ big-endian versions
+: w!-t ( n add -- ) over hibyte over c!-t ca1+ swap lobyte swap c!-t ;
+: l!-t ( l add -- ) >r lwsplit r@ w!-t r> /w-t + w!-t ;
+: w@-t ( target-address -- n ) dup c@-t 8 << swap 1+ c@-t or ;
+: l@-t ( target-address -- n ) dup >r /w-t + w@-t r> w@-t wljoin ;
+[then]
+
+: !-t ( n add -- ) l!-t ;
+: @-t ( target-address -- n ) l@-t ;
+
+\ Store target data types into the host address space.
+: c-t! ( c host-address -- ) c! ;
+[ifdef] little-endian-t
+: w-t! ( w host-address -- )
+ over hibyte over ca1+ c-t! swap lobyte swap c-t!
+;
+: l-t! ( l host-address -- ) >r lwsplit r@ /w-t + w-t! r> w-t! ;
+[else]
+: w-t! ( w host-address -- )
+ over hibyte over c-t! ca1+ swap lobyte swap c-t!
+;
+: l-t! ( l host-address -- ) >r lwsplit r@ w-t! r> /w-t + w-t! ;
+[then]
+: n-t! ( n host-address -- ) l-t! ;
+
+: c-t@ ( host-address -- c ) c@ ;
+[ifdef] little-endian-t
+: w-t@ ( host-address -- w ) >r r@ c-t@ r> 1+ c-t@ bwjoin ;
+: l-t@ ( host-address -- l ) >r r@ w-t@ r> /w-t + w-t@ wljoin ;
+[else]
+: w-t@ ( host-address -- w ) >r r@ 1+ c-t@ r> c-t@ bwjoin ;
+: l-t@ ( host-address -- l ) >r r@ /w-t + w-t@ r> w-t@ wljoin ;
+[then]
+
+\ Next 3 are machine-independent
+: c,-t ( byte -- ) here-t dup set-swap-bit-t 1 allot-t c!-t ;
+: w,-t ( word -- ) here-t /w-t allot-t w!-t ;
+: l,-t ( long -- ) here-t /l-t allot-t l!-t ;
+
+: ,-t ( n -- ) l,-t ; \ for 32 bit stacks
+: ,user#-t ( user# -- ) l,-t ;
+
+: a@-t ( target-address -- target-address ) l@-t ;
+: a!-t ( token target-address -- ) ( set-relocation-bit-t ) l!-t ;
+: token@-t ( target-address -- target-acf ) a@-t ;
+: token!-t ( acf target-address -- ) a!-t ;
+
+: rlink@-t ( occurrence -- next-occurrence ) a@-t ;
+: rlink!-t ( next-occurrence occurrence -- ) token!-t ;
+
+
+\ Machine independent
+: a,-t ( adr -- ) here-t /a-t allot-t a!-t ;
+: token,-t ( token -- ) here-t /token-t allot-t token!-t ;
+
+\ These versions of linkx-t are for absolute links
+: link@-t ( target-address -- target-address' ) a@-t ;
+: link!-t ( target-address target-address -- ) a!-t ;
+: link,-t ( target-address -- ) a,-t ;
+
+: a-t@ ( host-address -- target-address )
+[ also forth ]
+ dup origin here within over up@ dup user-size + within or if
+[ previous ]
+ l@
+ else
+ hostaddr> a@-t
+ then
+;
+: a-t! ( target-address host-address -- )
+[ also forth ]
+ dup origin here within over up@ dup user-size + within or if
+[ previous ]
+ l!
+ else
+ hostaddr> a!-t
+ then
+;
+: rlink-t@ ( host-adr -- target-adr ) a-t@ ;
+: rlink-t! ( target-adr host-adr -- ) a-t! ;
+
+: token-t@ ( host-address -- target-acf ) a-t@ ;
+: token-t! ( target-acf host-address -- ) a-t! ;
+: link-t@ ( host-address -- target-address ) a-t@ ;
+: link-t! ( target-address host-address -- ) a-t! ;
+
+\ Machine independent
+: a-t, ( target-address -- ) here /a-t allot a-t! ;
+: token-t, ( target-address -- ) here /token-t allot token-t! ;
+: >body-t ( cfa-t -- pfa-t )
+ \ The code fields of DOES> and ;CODE words contain an extra token
+ " dodoes" ['] labels $vfind if
+ execute
+ over token@-t = if /token-t + then
+ else
+ drop
+ then
+ /token-t +
+;
+
+1 constant #threads-t
+create threads-t #threads-t 1+ /link-t * allot
+
+: $hash-t ( adr len voc-ptr -- thread )
+ -rot nip #threads-t 1- and /thread-t * +
+;
+
+\ Should allocate these dynamically.
+\ The dictionary space should be dynamically allocated too.
+
+\ The user area image lives in the host address space.
+\ We wish to store into the user area with -t commands so as not
+\ to need separate words to store target items into host addresses.
+\ That is why user+ returns a target address.
+
+\ Machine Independent
+
+0 constant userarea-t
+: setup-user-area ( -- )
+ user-size-t alloc-mem is userarea-t
+ userarea-t user-size-t erase
+;
+
+: >user-t ( cfa-t -- user-adr-t )
+ >body-t
+ @-t
+ userarea-t +
+;
+
+: n>link-t ( anf-t -- alf-t ) /link-t - ;
+: l>name-t ( alf-t -- anf-t ) /link-t + ;
+
+decimal
+/l constant #align-t
+/l constant #talign-t
+/l constant #linkalign-t
+/l constant #acf-align-t
+: aligned-t ( n1 -- n2 ) #align-t 1- + #align-t negate and ;
+: acf-aligned-t ( n1 -- n2 ) #acf-align-t 1- + #acf-align-t negate and ;
+
+\ NullFix bl -> 0
+: align-t ( -- )
+ begin here-t #align-t 1- and while 0 c,-t repeat
+;
+: talign-t ( -- )
+ begin here-t #talign-t 1- and while 0 c,-t repeat
+;
+: linkalign-t ( -- )
+ begin here-t #linkalign-t 1- and while 0 c,-t repeat
+;
+: acf-align-t ( -- ) talign-t ;
+
+: entercode ( -- )
+ only forth also labels also meta also mips-assembler
+\ assembler
+ [ also mips-assembler ] here delay-barrier ! [ previous ]
+;
+
+\ Next 5 are Machine Independent
+: cmove-t ( from to-t n -- )
+ 0 do over c@ over c!-t 1+ swap 1+ swap loop 2drop
+;
+: place-cstr-t ( adr len cstr-adr-t -- cstr-adr-t )
+ >r tuck r@ swap cmove-t ( len ) r@ + 0 swap c!-t r>
+;
+: "copy-t ( from to-t -- )
+ over c@ 2+ cmove-t
+;
+: toggle-t ( addr-t n -- ) swap >r r@ c@-t xor r> c!-t ;
+
+: clear-threads-t ( hostaddr -- )
+ #threads-t /link-t * bounds do
+ origin-t i link-t!
+ /link +loop
+;
+: initmeta ( -- )
+\ init-relocation-t
+ threads-t #threads-t /link-t * bounds do
+ origin-t i link-t!
+ /link +loop
+ threads-t current-t !
+;
+
+\ For compiling branch offsets used by control constructs.
+\ These compile relative branches.
+
+/l-t constant /branch
+: branch! ( offset addr-t -- )
+ over - ( from offset ) swap
+ l!-t
+;
+: branch, ( offset -- )
+ here-t -
+ l,-t
+;
+
+\ Store actions for some data structures. This has to be in this
+\ file because it depends on the location of the user area (in some
+\ versions, the user area has to be in the dictionary for
+\ relocation to work right, but in other versions, the user area
+\ is elsewhere. Ultimately, separate relocation for the user area is
+\ needed.
+
+: isuser ( n acf -- ) >user-t n-t! ;
+: istuser ( acf1 acf -- ) >user-t token-t! ;
+: isvalue ( n acf -- ) >user-t n-t! ;
+: isdefer ( acf acf -- ) >user-t token-t! ;
+
+: thread-t! ( thread adr -- ) link-t! ;
+
+only forth also meta also definitions
+: install-target-assembler ( -- )
+ [ assembler ]
+\ ['] dp-t is asmdp
+ ['] here-t is here
+ ['] allot-t is asm-allot
+ ['] l@-t is asm@
+ ['] l!-t is asm!
+ [ meta ]
+;
+: install-host-assembler ( -- )
+ [ assembler ] resident [ meta ]
+;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/testasm.fth
===================================================================
--- cpu/mips/testasm.fth (rev 0)
+++ cpu/mips/testasm.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,94 @@
+purpose: Load file for running the MIPS assembler under C Forth 83
+\ See license at end of file
+
+: l>d 0 ;
+
+alias ul. u.
+alias headerless noop
+alias headerless0 noop
+alias headers noop
+
+\ cd /home/forthware/wmb/fm/extend/mips
+
+fload assem.fth
+fload disassem.fth
+
+: label create mips-assembler ;
+: code
+ create
+ d# 306 here body> ! \ 305 is the primitive number for deferred words
+ also mips-assembler
+;
+: next [ also mips-assembler ] $31 jr nop [ previous ] ;
+: end-code previous ;
+: c; next end-code ;
+
+also mips-assembler definitions
+alias s0 $16
+alias s1 $17
+alias s2 $18
+alias s3 $19
+alias s4 $20
+alias s5 $21
+alias s6 $22
+alias s7 $23
+alias t0 $8
+alias t1 $9
+alias t2 $10
+alias t3 $11
+alias t4 $12
+alias t5 $13
+alias t6 $14
+alias t7 $15
+
+.( XXX I don't know which register the compiler will use for the Forth) cr
+.( stack pointer) cr
+
+: base s2 ; : up s3 ; : tos s4 ; : ip s5 ; : rp s6 ; : sp ??? ;
+previous definitions
+hex
+
+\ Example - this is almost
+code xcmove ( src dst cnt -- )
+ sp 0 tos lw \ cnt into tos
+ sp 8 t0 lw \ Src into t0
+ sp 4 t1 lw \ Dst into t1
+ sp 3 /n* sp addiu \ Pop stack
+
+ t0 tos t2 addu \ t2 = src limit
+
+ t0 t2 <> if
+ nop
+
+ begin
+ t0 0 t3 lbu \ Load byte
+ t0 1 t0 addiu \ (load delay) Increment src
+ t3 t1 0 sb \ Store byte
+ t0 t2 = until
+ t1 1 t1 addiu \ (delay) Increment dst
+ then
+c;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/tickint.fth
===================================================================
--- cpu/mips/tickint.fth (rev 0)
+++ cpu/mips/tickint.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,49 @@
+purpose: Use the MIPS R4000 count/compare registers for the tick interrupt
+\ See license at end of file
+
+: tick-interrupt ( level -- )
+ drop
+ tick-counts compare@ + dup compare! ( next-count ) \ Setup next tick
+
+ \ If the count is already ahead of the comparator, the ticker has slipped
+ \ badly, so we advance the tick in order to avoid a really long interval.
+ count@ - 0< if tick-counts count@ + compare! then
+
+ tick-msecs ms/tick + to tick-msecs
+ ?call-os
+ check-alarm
+;
+
+0 value tick-counts
+: (set-tick-limit) ( #msecs -- )
+ to ms/tick
+ ms/tick ms-factor * to tick-counts
+ tick-counts count@ + compare!
+ ['] tick-interrupt 7 interrupt-handler!
+ 7 enable-interrupt
+;
+' (set-tick-limit) to set-tick-limit
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/tools.bth
===================================================================
--- cpu/mips/tools.bth (rev 0)
+++ cpu/mips/tools.bth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,57 @@
+purpose: Load file for Forth toolkit, without firmware
+\ See license at end of file
+
+dictionary: ${BP}/cpu/mips/build/kernel.dic
+command: &mipsfth &dictionary &this
+build-now
+
+' $report-name is include-hook
+\ ' noop is include-hook
+\ : rn (cr 2dup type 15 spaces ; ' rn is include-hook
+
+fload ${BP}/forth/lib/fwsetup.fth
+
+\ Variables controlling inclusion of optional packages.
+
+transient
+
+\ false value keep-headers? \ ~ 30K bytes
+true value keep-headers? \ ~ 30K bytes
+true value word-finders? \ ~ .5K bytes
+true value command-completion? \ ~ 1K bytes
+true value assembler? \ ~ 5K bytes
+true value symdebug? \ ~ 1K bytes
+false value help? \ ~ 5K bytes
+true value forth-debug? \ ~ 1K bytes
+true value elf32-support? \ ~ 1K bytes
+
+resident
+
+fload ${BP}/forth/lib/loadcomm.fth \ CPU-independent Forth tools
+fload ${BP}/cpu/mips/loadmach.fth \ CPU and OS-specific extensions
+
+cr .( --- Saving tools.dic --- ) " tools.dic" $save-forth cr
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/traps.fth
===================================================================
--- cpu/mips/traps.fth (rev 0)
+++ cpu/mips/traps.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,131 @@
+purpose: RAM base exception handlers
+\ See license at end of file
+
+only forth also hidden also forth definitions
+
+headerless
+
+\ Exception: Vector offset
+\ TLB refill 0x000
+\ 64TLB refill 0x080
+\ Cache error 0x100
+\ Others 0x180
+
+: 'vector ( exception# -- addr ) h# 80 * ;
+
+\ XXX Need work
+label vec0-generic
+
+ 8 k0 mfc0 \ get BADVADDR
+\ _GET_CURRENT(k1) \ get current task ptr
+ k0 d# 22 k0 srl \ get PGD only bits
+\ k1 THREAD_PGDIR k1 lw \ get task PG_DIR
+ k0 2 k0 sll
+ k1 k0 k1 addu \ add PGD offset
+ 4 k0 mfc0 \ get CONTEXT
+ k0 0 k0 lw
+ k0 1 k0 srl \ get PTE offset
+ k0 h# ff8 k0 and
+ k1 k0 k1 addu \ add PTE offset
+ k1 0 k0 lw \ get PTE
+ k1 4 k1 lw
+ k0 6 k0 srl \ convert to EntryLo format
+ k1 6 k1 srl
+ 2 k0 mtc0 \ set EntryLo
+ 3 k1 mtc0
+ nop
+ tlbwr \ write random tlb entry
+ nop nop nop
+ eret \ return from trap
+ nop
+
+end-code
+
+label vec1-generic
+ 4 k1 mfc0 \ get CP0_CONTEXT
+ k1 1 k1 dsra
+ k1 0 k0 lwu
+ k1 4 k1 lwu
+ k0 6 k0 dsrl \ Convert to EntryLo format
+ k1 6 k1 dsrl
+ 2 k0 dmtc0 \ set EntryLo0
+ 3 k1 dmtc0 \ set EntryLo1
+ nop
+ tlbwr
+ nop nop nop
+ eret
+ nop
+end-code
+
+: .cacherr ( CacheErr -- )
+ dup h# 8000.0000 and if ." data;" else ." instruction;" then
+ dup h# 2000.0000 and if ." data field error;" then
+ dup h# 1000.0000 and if ." tag field error;" then
+ dup h# 0800.0000 and if ." error on first doubleword;" then
+ dup h# 0400.0000 and if ." error on SysAD bus;" then
+ h# 0200.0000 and if ." error on one cache" else ." error on both caches" then
+;
+
+: cache-error-handler ( -- )
+ ." Cache error at address: " errorepc@ .x
+ ." (" cacherr@ .cacherr ." )" cr
+ begin again
+;
+
+label vec2-generic
+ here 8 + bal \ ra = Absolute address of next instruction
+ here origin - 4 + k1 set \ k1 = relative address of this instruction
+ ra k1 base subu \ k1 address of Forth kernel
+
+ 'body main-task up li \ User pointer address
+
+ \ Set up Forth stacks
+ 'user sp0 sp lw
+ 'user rp0 rp lw
+
+ \ Account for the presence of the top of stack register
+ sp /n sp addiu
+
+ np@ origin- np set
+ np base np addu
+
+ 'body cache-error-handler ip set
+ ip base ip addu
+c;
+
+0 value vector-base
+: install-handler ( handler exception# -- )
+ ( exception# ) 'vector vector-base + >r
+ ( handler ) lwsplit
+ h# 3c1b.0000 or r@ 0 + instruction! \ lui k1,handler.hi
+ h# 377b.0000 or r@ 4 + instruction! \ ori k1,k1,handler.lo
+ h# 0360.0008 r@ 8 + instruction! \ jr k1
+ 0 r> h# c + instruction! \ nop
+;
+
+headers
+only forth also definitions
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/unalign.fth
===================================================================
--- cpu/mips/unalign.fth (rev 0)
+++ cpu/mips/unalign.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,95 @@
+purpose: Unaligned memory access operations for bi-endian MIPS
+\ See license at end of file
+
+0 value in-little-endian?
+
+code unaligned-l@ (s adr -- l )
+ 'user in-little-endian? $at lw
+ tos t0 move \ bubble
+ $at 0 <> if \ Little endian
+ nop \ delay
+ t0 3 tos lwl
+ else \ Big endian
+ t0 0 tos lwr \ delay
+
+ t0 0 tos lwl
+ t0 3 tos lwr
+ then
+c;
+: unaligned-@ (s adr -- l ) unaligned-l@ ;
+code unaligned-w@ (s adr -- w )
+ 'user in-little-endian? $at lw
+ tos t0 move \ Bubble
+ $at 0 <> if \ Little endian
+ t0 1 t2 lb \ Delay
+ t0 0 t1 lb
+ t2 8 tos sll
+ else \ Big endian
+ tos t1 tos or \ Delay
+
+ t0 0 tos lb
+ bubble
+ tos 8 tos sll
+ tos t2 tos or
+ then
+c;
+code unaligned-l! (s n adr -- )
+ 'user in-little-endian? $at lw
+ sp 0 t0 lw \ Bubble
+ $at 0 <> if \ Little endian
+ nop \ Delay
+ t0 tos 3 swl
+ else \ Big endian
+ t0 tos 0 swr \ Delay
+
+ t0 tos 0 swl
+ t0 tos 3 swr
+ then
+ sp 4 tos lw
+ sp 8 sp addiu
+c;
+: unaligned-d! ( d adr -- )
+ >r in-little-endian? if swap then
+ r@ unaligned-! r> na1+ unaligned-!
+;
+
+: unaligned-! (s n adr -- ) unaligned-l! ;
+code unaligned-w! (s w adr -- )
+ 'user in-little-endian? $at lw
+ sp 0 t0 lw \ Bubble
+ $at 0 <> if \ Little endian
+ t0 8 t1 srl \ Delay
+ t0 tos 0 sb
+ else \ Big endian
+ t1 tos 1 sb \ Delay
+
+ t0 tos 1 sb
+ t1 tos 0 sb
+ then
+ sp 4 tos lw
+ sp 8 sp addiu
+c;
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/virtaddr.fth
===================================================================
--- cpu/mips/virtaddr.fth (rev 0)
+++ cpu/mips/virtaddr.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,37 @@
+purpose: Virtual addresses for generic MIPS system
+\ See license at end of file
+
+headerless
+
+0 value fw-virt-base \ Setup later after we know the memory size
+h# 10.0000 value fw-virt-size
+
+headers
+
+kseg0 h# 20.0000 + ' load-base set-config-int-default
+
+0 value load-limit \ Top address of area at load-base (set later)
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/mips/zipcrc.fth
===================================================================
--- cpu/mips/zipcrc.fth (rev 0)
+++ cpu/mips/zipcrc.fth 2009-05-25 20:35:46 UTC (rev 1201)
@@ -0,0 +1,66 @@
+purpose: ZIP CRC calculation
+\ See license at end of file
+
+\ Load this before pkg/zipcrc.ftg
+
+headers
+
+transient
+only forth also assembler also definitions
+alias blen t0
+alias badr t1
+alias table t2
+alias crc tos
+alias eadr t3
+alias i t4
+alias crc' t5
+only forth also definitions
+resident
+
+code ($crc) ( crc table-adr adr len -- crc' )
+ tos blen move
+ sp badr pop
+ sp table pop
+ sp crc pop
+
+ blen 0 = if nop next then \ Exit if len=0
+
+ badr blen eadr addu \ Compute end loop condition
+ begin
+ badr 0 i lbu \ Get next byte
+ crc i i xor \ crc ^ byte
+ i h# ff i andi \ index
+ i 2 i sll \ index * 4
+ i table i add
+ i 0 crc' lw \ Lookup in table
+ crc 8 crc srl \ Shift old crc
+ badr 1 badr addiu \ Increment address
+ badr eadr = until
+ crc' crc crc xor \ Merge new bits
+
+c;
+
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
1
0
r1200 - in cpu: . mips mips/Linux mips/atlas mips/bonito mips/broadcom mips/broadcom/avx
by svn＠openfirmware.info 25 May '09
by svn＠openfirmware.info 25 May '09
25 May '09
Author: wmb
Date: 2009-05-25 22:33:07 +0200 (Mon, 25 May 2009)
New Revision: 1200
Added:
cpu/mips/
cpu/mips/Linux/
cpu/mips/Linux/build
cpu/mips/QEMU/
cpu/mips/atlas/
cpu/mips/atlas/build/
cpu/mips/bonito/
cpu/mips/bonito/build/
cpu/mips/broadcom/
cpu/mips/broadcom/avx/
cpu/mips/broadcom/avx/build/
cpu/mips/build/
cpu/mips/cobalt/
Log:
MIPS - preliminary checkin of MIPS version. Some things aren't quite ready yet...
Added: cpu/mips/Linux/build
===================================================================
--- cpu/mips/Linux/build (rev 0)
+++ cpu/mips/Linux/build 2009-05-25 20:33:07 UTC (rev 1200)
@@ -0,0 +1 @@
+link /home/wmb/ofwmips/cpu/mips/Linux/mipsforth
\ No newline at end of file
Property changes on: cpu/mips/Linux/build
___________________________________________________________________
Added: svn:special
+ *
1
0
r1199 - cpu/arm cpu/arm/beagle cpu/arm/beagle/build cpu/arm/openmoko cpu/arm/openmoko/build dev dev/omap
by svn＠openfirmware.info 24 May '09
by svn＠openfirmware.info 24 May '09
24 May '09
Author: wmb
Date: 2009-05-24 13:01:02 +0200 (Sun, 24 May 2009)
New Revision: 1199
Added:
cpu/arm/beagle/
cpu/arm/beagle/beagle.bth
cpu/arm/beagle/build/
cpu/arm/beagle/build/Makefile
cpu/arm/beagle/traps.fth
cpu/arm/openmoko/
cpu/arm/openmoko/build/
cpu/arm/openmoko/build/Makefile
cpu/arm/openmoko/openmoko.bth
dev/omap/
dev/omap/diaguart.fth
Modified:
cpu/arm/traps.fth
Log:
ARM - added Beagle Board / Gumstix Overo support, and the start of OpenMoko
Added: cpu/arm/beagle/beagle.bth
===================================================================
--- cpu/arm/beagle/beagle.bth (rev 0)
+++ cpu/arm/beagle/beagle.bth 2009-05-24 11:01:02 UTC (rev 1199)
@@ -0,0 +1,90 @@
+purpose: Load file for OFW on ARM beagleboard
+\ See license at end of file
+
+dictionary: ${BP}/cpu/arm/build/basefw.dic
+command: &armforth &dictionary &this
+build-now
+
+" beagle.tag" r/w create-file drop tag-file !
+
+\ ' $report-name is include-hook
+
+use-movable-vector-base \ CortexA8 CPU core has a movable vector base
+
+h# 8.0000 constant initial-heap-size
+
+: (initial-heap) ( -- adr len ) limit initial-heap-size ;
+' (initial-heap) to initial-heap
+
+
+fload ${BP}/dev/omap/diaguart.fth \ OMAP UART
+h# 49020000 to uart-base \ UART# base address on beagleboard
+
+fload ${BP}/forth/lib/sysuart.fth \ Set console I/O vectors to UART
+
+
+\ Install the simple UART driver from the standalone I/O init chain
+: stand-init-io ( -- )
+ stand-init-io
+ inituarts install-uart-io
+;
+
+0 [if] \ This turns off an LED; it's useful for startup debugging
+code usr1-off
+ begin
+ set r1,0x49056090
+ set r2,0x00400000
+ str r2,[r1]
+ again
+c;
+[then]
+
+\ This is some glue code to convert the machine setup that QEMU gives us
+\ to the setup that start-forth (see arm/boot.fth) wants.
+\ We get here via a call instruction at origin+8, which is inserted below
+
+code stand-cold-code ( r0: 0 r1: board-id r2: &kernel-args lr: &aif_header+8c )
+ here origin 8 + put-call \ Insert call instruction
+
+ \ Put the arguments in safe registers
+ sub r6,lr,#0x8c \ r6 points to header (lr set by code at origin)
+ mov r7,#0 \ r7: functions
+ add r8,r6,0x200000 \ r8: memtop - 2MiB above load address
+ \ r9 is up
+ mov r10,#0 \ r10: argc
+ mov r11,r2 \ r11: argv (kernel args)
+ mov r12,`initial-heap-size` \ r12: initial-heap-size
+
+ b 'code start-forth \ Branch to the generic startup code
+end-code
+
+
+tag-file @ fclose tag-file off
+
+fload ${BP}/cpu/arm/saverom.fth \ Save the dictionary for standalone startup
+
+.( --- Saving beagle.rom --- ) cr " beagle.rom" $save-rom
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Property changes on: cpu/arm/beagle/beagle.bth
___________________________________________________________________
Added: svn:executable
+ *
Added: cpu/arm/beagle/build/Makefile
===================================================================
--- cpu/arm/beagle/build/Makefile (rev 0)
+++ cpu/arm/beagle/build/Makefile 2009-05-24 11:01:02 UTC (rev 1199)
@@ -0,0 +1,59 @@
+OS := $(shell uname)
+
+BASEDIR= `(cd ../../../..; pwd;)`
+TAGFILES= ../../build/*.tag *.tag
+CLIENTDIR=../../../../clients
+CLIENTPROGS=
+
+all: beagle.rom tags
+
+beagle.tag: beagle.rom
+
+tags: beagle.tag
+ @${BASEDIR}/forth/lib/toctags ${BASEDIR} ${TAGFILES}
+
+beagle.rom: FORCE build ${CLIENTPROGS}
+ ./build $@
+
+../../${OS}/forth:
+ @make -C ../../${OS} forth
+
+../../build/inflate.bin:
+ @make -C ../../build inflate.bin
+
+build: ../../${OS}/forth
+ @ln -sf ../../${OS}/forth build
+
+clean:
+ rm -f *.dic *.log headers *~ *.elf *.di *.img builton.fth build *.rom *.version
+
+clean-all: clean
+ @make -C ../../build clean
+ @make -C ../../${OS} clean
+
+.PHONY: FORCE clean all clean-all
+
+# LICENSE_BEGIN
+# Copyright (c) 2009 FirmWorks
+#
+# Permission is hereby granted, free of charge, to any person obtaining
+# a copy of this software and associated documentation files (the
+# "Software"), to deal in the Software without restriction, including
+# without limitation the rights to use, copy, modify, merge, publish,
+# distribute, sublicense, and/or sell copies of the Software, and to
+# permit persons to whom the Software is furnished to do so, subject to
+# the following conditions:
+#
+# The above copyright notice and this permission notice shall be
+# included in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+# LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+# OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+# WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+#
+# LICENSE_END
+
Property changes on: cpu/arm/beagle/build/Makefile
___________________________________________________________________
Added: svn:executable
+ *
Added: cpu/arm/beagle/traps.fth
===================================================================
--- cpu/arm/beagle/traps.fth (rev 0)
+++ cpu/arm/beagle/traps.fth 2009-05-24 11:01:02 UTC (rev 1199)
@@ -0,0 +1,114 @@
+purpose: Save the processor state after an exception - hardware version
+\ See license at end of file
+
+only forth also hidden also forth definitions
+
+\ The common subroutines on which this depends are defined in
+\ cpu/arm/register.fth
+
+headerless
+
+\ This is the first part of the exception handling sequence and the last
+\ half of the exception restart sequence. It is executed in exception state.
+
+label hw-save-state
+ \ On entry: r13: scratch r14: PC from old mode
+
+ \ Check for second half of (restart, if so restore all the registers
+ \ from the save area and return from the exception.
+
+ 'code (restart drop restart-offset + ( offset )
+ adr r13,* \ Address of trap in (restart
+
+ dec r14,1cell \ Point to the trapped instruction
+ cmp r13,r14
+
+ adr r13,'body main-task \ Get user pointer address
+ ldr r13,[r13] \ Get user pointer
+ ldr r13,[r13,`'user# cpu-state`] \ State save address
+
+ beq 'body restart-common
+
+ stmia r13,{r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12}
+
+ mov r0,r13 \ Move cpu-state pointer into r0
+ mov r4,#0 \ Set r4 to 0 to indicate no user abort
+ b 'body save-common
+end-code
+
+defer init-vector-base
+' noop to init-vector-base
+
+defer vector-base
+0 value fixed-vector-base
+' fixed-vector-base to vector-base
+
+: hw-install-handler ( handler exception# -- )
+ vector-base swap la+ ( handler vector-adr )
+
+ \ Put "ldr pc,[pc,40-8]" in exception vector at vector-base + (exception# * 4 )
+ h# e59ff038 over instruction! ( handler vector-adr )
+
+ \ Put handler address in address table at vector-base + 40 + (exception# * 4)
+ h# 40 + l!
+;
+: hw-catch-exception ( exception# -- ) hw-save-state swap install-handler ;
+
+\ Some ARM CPUs, such as CortexA8, let you move the vector base anywhere
+code vector-base@ ( -- adr )
+ psh tos,sp
+ mrc p15,0,tos,cr12,cr0,0
+c;
+
+code vector-base! ( adr --- )
+ mcr p15,0,tos,cr12,cr0,0
+ pop tos,sp
+c;
+
+h# 80 buffer: ram-vector-base-buf
+: move-vector-base ( -- ) ram-vector-base-buf h# 20 round-up vector-base! ;
+
+\ Execute this at compile time for processors that need it.
+\ Ideally we would detect the vector base register at run time
+\ but I don't know how yet.
+: use-movable-vector-base ( -- )
+ ['] vector-base@ to vector-base
+ ['] move-vector-base to init-vector-base
+;
+
+: stand-init-io ( -- )
+ stand-init-io
+ ['] (restart is restart
+ ['] hw-install-handler is install-handler
+ ['] hw-catch-exception is catch-exception
+ init-vector-base
+ catch-exceptions
+ 2 catch-exception \ Software interrupt (we don't catch this under DEMON)
+;
+
+headers
+only forth also definitions
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Property changes on: cpu/arm/beagle/traps.fth
___________________________________________________________________
Added: svn:executable
+ *
Added: cpu/arm/openmoko/build/Makefile
===================================================================
--- cpu/arm/openmoko/build/Makefile (rev 0)
+++ cpu/arm/openmoko/build/Makefile 2009-05-24 11:01:02 UTC (rev 1199)
@@ -0,0 +1,58 @@
+OS := $(shell uname)
+
+BASEDIR= `(cd ../../../..; pwd;)`
+TAGFILES= ../../build/*.tag *.tag
+CLIENTDIR=../../../../clients
+CLIENTPROGS=
+
+all: openmoko.rom tags
+
+openmoko.tag: openmoko.rom
+
+tags: openmoko.tag
+ @${BASEDIR}/forth/lib/toctags ${BASEDIR} ${TAGFILES}
+
+openmoko.rom: FORCE build ${CLIENTPROGS}
+ ./build $@
+
+../../${OS}/forth:
+ @make -C ../../${OS} forth
+
+../../build/inflate.bin:
+ @make -C ../../build inflate.bin
+
+build: ../../${OS}/forth
+ @ln -sf ../../${OS}/forth build
+
+clean:
+ rm -f *.dic *.log headers *~ *.elf *.di *.img builton.fth build *.rom *.version
+
+clean-all: clean
+ @make -C ../../build clean
+ @make -C ../../${OS} clean
+
+.PHONY: FORCE clean all clean-all
+
+# LICENSE_BEGIN
+# Copyright (c) 2009 FirmWorks
+#
+# Permission is hereby granted, free of charge, to any person obtaining
+# a copy of this software and associated documentation files (the
+# "Software"), to deal in the Software without restriction, including
+# without limitation the rights to use, copy, modify, merge, publish,
+# distribute, sublicense, and/or sell copies of the Software, and to
+# permit persons to whom the Software is furnished to do so, subject to
+# the following conditions:
+#
+# The above copyright notice and this permission notice shall be
+# included in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+# LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+# OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+# WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+#
+# LICENSE_END
Added: cpu/arm/openmoko/openmoko.bth
===================================================================
--- cpu/arm/openmoko/openmoko.bth (rev 0)
+++ cpu/arm/openmoko/openmoko.bth 2009-05-24 11:01:02 UTC (rev 1199)
@@ -0,0 +1,100 @@
+purpose: Load file for OFW on ARM beagleboard
+\ See license at end of file
+
+dictionary: ${BP}/cpu/arm/build/basefw.dic
+command: &armforth &dictionary &this
+build-now
+
+" beagle.tag" r/w create-file drop tag-file !
+
+\ ' $report-name is include-hook
+
+h# 8.0000 constant initial-heap-size
+
+: (initial-heap) ( -- adr len ) limit initial-heap-size ;
+' (initial-heap) to initial-heap
+
+
+\ fload ${BP}/dev/diaguartbb.fth \ beagleboard UART3
+fload ${BP}/cpu/arm/beagle/diaguartbb.fth \ beagleboard UART3
+\ h# 50000000 to uart-base \ UART# base address on beagleboard
+h# 50004000 to uart-base \ UART# base address on beagleboard
+\ h# 50008000 to uart-base \ UART# base address on beagleboard
+
+fload ${BP}/forth/lib/sysuart.fth \ Set console I/O vectors to UART
+
+patch noop catch-exceptions stand-init-io
+patch drop hw-catch-exception stand-init-io
+
+h# 5000.8000 value uart-base
+: fifo-stat@ ( -- n ) uart-base h# 18 + l@ ;
+: rxtx-stat@ ( -- n ) uart-base h# 10 + l@ ;
+
+\ Install the simple UART driver from the standalone I/O init chain
+: stand-init-io ( -- )
+ ( [char] A h# 5000.0023 c! ) [char] a h# 5000.0020 c!
+ ( [char] B h# 5000.4023 c! ) [char] b h# 5000.4020 c!
+ ( [char] C h# 5000.8023 c! ) [char] c h# 5000.8020 c!
+ begin again
+ stand-init-io
+\ inituarts install-uart-io
+;
+
+\ This is some glue code to convert the machine setup that QEMU gives us
+\ to the setup that start-forth (see arm/boot.fth) wants.
+\ We get here via a call instruction at origin+8, which is inserted below
+
+code stand-cold-code ( r0: 0 r1: board-id r2: &kernel-args lr: &aif_header+8c )
+ here origin 8 + put-call \ Insert call instruction
+
+ \ Put the arguments in safe registers
+ sub r6,lr,#0x8c \ r6 points to header (lr set by code at origin)
+ mov r7,#0 \ r7: functions
+ add r8,r6,0x200000 \ r8: memtop - 2MiB above load address
+ \ r9 is up
+ mov r10,#0 \ r10: argc
+ mov r11,r2 \ r11: argv (kernel args)
+ mov r12,`initial-heap-size` \ r12: initial-heap-size
+
+\ XXX FB hack
+\ set r1,0x08800000 \ memtop of 2MB above load address
+\ set r0,0x10000
+\ set r2,0xaa
+\ begin
+\ decs r0,1
+\ strgeb r2,[r1],#1
+\ < until
+
+ b 'code start-forth \ Branch to the generic startup code
+end-code
+
+
+tag-file @ fclose tag-file off
+
+fload ${BP}/cpu/arm/saverom.fth \ Save the dictionary for standalone startup
+
+.( --- Saving openmoko.rom --- ) cr " openmoko.rom" $save-rom
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Modified: cpu/arm/traps.fth
===================================================================
--- cpu/arm/traps.fth 2009-05-14 08:55:20 UTC (rev 1198)
+++ cpu/arm/traps.fth 2009-05-24 11:01:02 UTC (rev 1199)
@@ -36,20 +36,52 @@
b 'body save-common
end-code
-: hw-install-handler ( handler exception# -- )
- \ Put "ldr pc,[pc,40-8]" in exception vector at 0 + (exception# * 4)
- h# e59ff038 over /l* instruction! ( exception# )
+defer init-vector-base
+' noop to init-vector-base
- \ Put handler address in address table at 40 + (exception# * 4)
- h# 40 swap la+ l!
+defer vector-base
+0 value fixed-vector-base
+' fixed-vector-base to vector-base
+
+: hw-install-handler ( handler exception# -- )
+ vector-base swap la+ ( handler vector-adr )
+
+ \ Put "ldr pc,[pc,40-8]" in exception vector at vector-base + (exception# * 4 )
+ h# e59ff038 over instruction! ( handler vector-adr )
+
+ \ Put handler address in address table at vector-base + 40 + (exception# * 4)
+ h# 40 + l!
;
: hw-catch-exception ( exception# -- ) hw-save-state swap install-handler ;
+\ Some ARM CPUs, such as CortexA8, let you move the vector base anywhere
+code vector-base@ ( -- adr )
+ psh tos,sp
+ mrc p15,0,tos,cr12,cr0,0
+c;
+
+code vector-base! ( adr --- )
+ mcr p15,0,tos,cr12,cr0,0
+ pop tos,sp
+c;
+
+h# 80 buffer: ram-vector-base-buf
+: move-vector-base ( -- ) ram-vector-base-buf h# 20 round-up vector-base! ;
+
+\ Execute this at compile time for processors that need it.
+\ Ideally we would detect the vector base register at run time
+\ but I don't know how yet.
+: use-movable-vector-base ( -- )
+ ['] vector-base@ to vector-base
+ ['] move-vector-base to init-vector-base
+;
+
: stand-init-io ( -- )
stand-init-io
['] (restart is restart
['] hw-install-handler is install-handler
['] hw-catch-exception is catch-exception
+ init-vector-base
catch-exceptions
2 catch-exception \ Software interrupt (we don't catch this under DEMON)
;
@@ -58,7 +90,7 @@
only forth also definitions
\ LICENSE_BEGIN
-\ Copyright (c) 1997 FirmWorks
+\ Copyright (c) 2009 FirmWorks
\
\ Permission is hereby granted, free of charge, to any person obtaining
\ a copy of this software and associated documentation files (the
Added: dev/omap/diaguart.fth
===================================================================
--- dev/omap/diaguart.fth (rev 0)
+++ dev/omap/diaguart.fth 2009-05-24 11:01:02 UTC (rev 1199)
@@ -0,0 +1,64 @@
+purpose: Diagnostic (before console installation) access to serial port
+\ See license at end of file
+
+\ For the OMAP's UART
+
+d# 48000000 constant uart-clock-frequency
+
+[ifndef] uart@
+
+h# 49020000 value uart-base \ Virtual address of UART; set later
+: uart@ ( reg# -- byte ) /l* uart-base + l@ ; \ Read from a UART register
+: uart! ( byte reg# -- ) /l* uart-base + l! ; \ Write from a UART register
+
+[then]
+
+: baud ( baud-rate -- )
+ uart-clock-frequency d# 16 / swap rounded-/ ( baud-rate-divisor )
+
+ begin 5 uart@ h# 40 and until \ Wait until transmit done
+
+ 3 uart@ dup >r h# 80 or 3 uart! \ divisor latch access bit on
+ dup h# ff and 0 uart! 8 >> 1 uart! \ Write lsb and msb
+ r> 3 uart! \ Restore old state
+;
+
+: inituarts ( -- )
+\ 3 3 uart! \ 8 bits, no parity
+\ 7 2 uart! \ Clear and enable FIFOs
+\ d# 38400 baud
+\ d# 9600 baud
+\ d# 115200 baud
+;
+
+: ukey? ( -- flag ) 5 uart@ 1 and 0<> ; \ Test for rcv character
+: uemit? ( -- flag ) 5 uart@ h# 20 and 0<> ; \ Test for xmit ready
+: ubreak? ( -- flag ) 5 uart@ h# 10 and 0<> ; \ Test for received break
+: clear-break ( -- ) 5 uart@ drop ; \ Clear break indication
+
+: ukey ( -- char ) begin ukey? until 0 uart@ ; \ Receive a character
+: uemit ( char -- ) begin uemit? until 0 uart! ; \ Transmit a character
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Property changes on: dev/omap/diaguart.fth
___________________________________________________________________
Added: svn:executable
+ *
1
0
Author: wmb
Date: 2009-05-14 10:55:20 +0200 (Thu, 14 May 2009)
New Revision: 1198
Added:
cpu/x86/pc/olpc/via/dramtiming.fth
Modified:
cpu/x86/pc/olpc/via/demodram.fth
cpu/x86/pc/olpc/via/ioinit.fth
cpu/x86/pc/olpc/via/romreset.bth
Log:
Via - checkpoint with new timing computation code - not finished yet.
Modified: cpu/x86/pc/olpc/via/demodram.fth
===================================================================
--- cpu/x86/pc/olpc/via/demodram.fth 2009-05-14 08:19:39 UTC (rev 1197)
+++ cpu/x86/pc/olpc/via/demodram.fth 2009-05-14 08:55:20 UTC (rev 1198)
@@ -14,7 +14,8 @@
\ Must use "CPU delay" to make sure VLINK is dis-connect
0 7 devfunc 47 00 04 mreg end-table d# 20 wait-us
0 3 devfunc 90 07 07 mreg end-table d# 20 wait-us \ First set DRAM Freq to invalid
- 0 3 devfunc 90 07 04 mreg end-table d# 20 wait-us \ 266 MHz
+\ 0 3 devfunc 90 07 03 mreg end-table d# 20 wait-us \ 200 MHz ATEST
+ 0 3 devfunc 90 07 04 mreg end-table d# 20 wait-us \ 266 MHz !ATEST
0 3 devfunc 6b d0 c0 mreg end-table d# 20 wait-us \ PLL Off
0 3 devfunc 6b 00 10 mreg end-table d# 20 wait-us \ PLL On
0 3 devfunc 6b c0 00 mreg end-table \ Adjustments off
@@ -24,10 +25,45 @@
\ TimingSetting.c
0 3 devfunc
- 61 ff 55 mreg \ Trfc, Trrd
- 62 ff 8a mreg \ CL, Trp, Tras
- 63 ff 49 mreg \ Twr, Twtr, Trtp
- 64 ff 66 mreg \ Trp, Trcd
+[ifdef] phoenix-timings
+ 61 ff 55 mreg \ Trfc: 0x15+8 = 29 * 3.75 = 108.75 ns, Trrd: 01 -> 3T
+ 62 ff 8a mreg \ Tras: 8+5=13 *3.75=48.75, 8bank-timing constraint, CL 2+2=4
+ 63 ff 49 mreg \ Twr:2+2=4 *3.75=15, Trtp:1+2=3 *3.75=11.25, Twtr:1+2=3 *3.75=11.25
+ 64 ff 66 mreg \ Trp 5, Trcd 5
+[then]
+[ifdef] coreboot-timings
+ 61 ff 54 mreg \ Trfc: 0x14+8 = 28 * 3.75 = 105.00 ns, Trrd: 01 -> 3T
+ 62 ff 7a mreg \ Tras: 7+5=12 *3.75=45.00, 8bank-timing constraint, CL 2+2=4
+ 63 ff 40 mreg \ Twr:2+2=4 *3.75=15, Trtp:0+2=2 *3.75=7.5, Twtr:0+2=2 *3.75=7.5
+ 64 ff 44 mreg \ Trp 2+2=4, Trcd 2+2=4
+[then]
+[ifdef] compute-timings
+\ The subtractions below (e.g. "2 -") account for the way that numbers are
+\ encoded in bit fields - e.g. 00b means 2T, 01b means 3T, etc.
+\ The shifts below (e.g. "6 <<") move the value into the correct bit position.
+
+ 61 3f Trfc ns>tck 8 - mreg \ Trfc: ceil(127.50/5) = 26 - 8 = 0x12
+ 61 c0 Trrd ns>tck 2 - 6 << mreg \ Trrd: ceil( 7.50/5) = 2 - 0 = 0x00
+
+\ 61 ff 12 mreg \ Trfc, Trrd Trfc = 0x39+8 = 65 Trrd=4T ceil(7.5ns/5ns)
+
+ 62 07 TCL 2 - mreg \ CL 3
+ 62 08 08 mreg \ 8-bank timing constraint
+ 62 f0 Tras ns>tck 5 - 4 << mreg \ Tras: ceil( 40.00/5) = 8 - 5 = 0x03
+
+\ 62 ff 3a mreg \ CL, 8-bank constraint, Tras Tras = 8T (3+5=8)
+
+ 63 e0 Twr ns>tck 2 - 5 << mreg \ Twr: ceil( 15.00/5) = 3 - 2 = 0x01
+ 63 08 Trtp ns>tck 2 - 3 << mreg \ Trtp: ceil( 7.00/5) = 2 - 2 = 0x00
+ 63 03 Twtr ns>tck 2 - mreg \ Twtr: ceil( 10.00/5) = 2 - 2 = 0x00
+
+\ 63 ff 20 mreg \ Twr, Twtr, Trtp Twr=3T (15ns/5), Twtr=2T (10/5) Trtp=2T ceil(7.5/5)
+
+ 64 0e Trp ns>tck 2 - 1 << mreg \ Trp: ceil( 15.00/5) = 3 - 2 = 0x01
+ 64 e0 Trcd ns>tck 2 - 5 << mreg \ Trcd: ceil( 15.00/5) = 3 - 2 = 0x01
+
+\ 64 ff 22 mreg \ Trp 3, Trcd 3
+[then]
end-table
\ DRDR_BL.c
@@ -154,6 +190,7 @@
h# 11 port80
+forth #ranks 2 >= assembler [if]
0 3 devfunc
40 ff 00 mreg \ Rank 1 top back to 0 to work on other ranks
@@ -164,14 +201,15 @@
end-table
DDRinit #) call
+[then]
+forth #ranks 3 >= assembler [if]
0 3 devfunc
41 ff 00 mreg \ Rank 1 top back to 0 to work on other ranks
end-table
h# 14 port80
-0 [if] \ This is for a DIMM in the other socket
0 3 devfunc
54 ff 00 mreg \ Disable ranks 0,1
55 ff a0 mreg \ Enable Rank 2
@@ -183,6 +221,11 @@
0 3 devfunc
42 ff 00 mreg \ Rank 2 top back to 0 to work on other ranks
+ end-table
+[then]
+
+forth #ranks 4 >= assembler [if]
+ 0 3 devfunc
54 ff 00 mreg \ Disable ranks 0,1
55 ff 0b mreg \ Enable Rank 3
43 ff 10 mreg \ Rank 3 top
@@ -197,7 +240,8 @@
[then]
0 3 devfunc
- 69 03 03 mreg \ Reinstate page optimizations (03) - FF #ranks
+ 69 03 03 mreg \ Reinstate page optimizations (03) - FF #ranks !ATEST
+\ 69 c3 c3 mreg \ Reinstate page optimizations (03) - FF #ranks ATEST 8-bank interleave
\ RankMap.c
\ DRAMBankInterleave
@@ -205,29 +249,37 @@
87 ff 00 mreg \ Channel B #banks or some such - FF BA
\ SizingMATypeM
- 50 ff 20 mreg \ MA Map type - ranks 0/1 type 1 - 2 bank bits, 10 column bits
+ 50 ff 20 mreg \ MA Map type - ranks 0/1 type 1 - 2 bank bits, 10 column bits !ATEST
+\ 50 ff a1 mreg \ 1T Command Rate, RMA Map type - ranks 0/1 type 5 - 3 bank bits, 14 row bits, 10 col bits ATEST
51 ff 60 mreg \ "Reserved"
52 ff 33 mreg \ Bank interleave on A17, A18, and
- 53 ff 3f mreg \ A19 (but BA2 off because 4 banks), Rank interleave on A20 and A21
+ 53 ff 3f mreg \ A19 (but BA2 off because 4 banks), Rank interleave on A20 and A21 !ATEST
+\ 53 ff bf mreg \ BA2 on (80), A19, Rank interleave on A20 and A21 ATEST
\ Different interleave bits might improve performance on some workloads
- 54 ff 89 mreg \ Rank map A 0/1
+ 54 ff 89 mreg \ Rank map A 0/1 !ATEST
+\ 54 ff 80 mreg \ Rank map A 0/1 ATEST Rank 0 only
55 ff 00 mreg \ Rank map A 2/3
56 ff 00 mreg \ Rank map B ?
57 ff 00 mreg \ Rank map B ?
- 40 ff 04 mreg \ Rank top 0
- 41 ff 08 mreg \ Rank top 1
+ 40 ff 04 mreg \ Rank top 0 !ATEST
+\ 40 ff 10 mreg \ Rank top 0 ATEST 1 GiB
+ 41 ff 08 mreg \ Rank top 1 !ATEST
+\ 41 ff 00 mreg \ Rank top 1 ATEST
+
42 ff 00 mreg \ Rank top 2
43 ff 00 mreg \ Rank top 3
48 ff 00 mreg \ Rank base 0
- 49 ff 04 mreg \ Rank base 1
+ 49 ff 04 mreg \ Rank base 1 !ATEST
+\ 49 ff 00 mreg \ Rank base 1 ATEST
4a ff 00 mreg \ Rank base 2
4b ff 00 mreg \ Rank base 3
end-table
- 20 8f60 config-wb \ DRAM Bank 7 ending address - controls DMA upstream
+ 20 8f60 config-wb \ DRAM Bank 7 ending address - controls DMA upstream !ATEST
+\ 40 8f60 config-wb \ DRAM Bank 7 ending address - controls DMA upstream ATEST
0388 config-rb ax bx mov 0385 config-setup bx ax mov al dx out \ Copy Low Top from RO reg 88 to reg 85
0388 config-rb ax bx mov 8fe5 config-setup bx ax mov al dx out \ Copy Low Top from RO reg 88 to SB Low Top e5
@@ -261,7 +313,8 @@
\ FinalSetting.c
\ RefreshCounter
- 6a ff 86 mreg \ Refresh interval - FF frequency
+ 6a ff 86 mreg \ Refresh interval - FF frequency !ATEST
+\ 6a ff ca mreg \ Refresh interval - FF frequency ATEST
\ DRAMRegFinalValue
60 00 d0 mreg \ Fast turn-around
Added: cpu/x86/pc/olpc/via/dramtiming.fth
===================================================================
--- cpu/x86/pc/olpc/via/dramtiming.fth (rev 0)
+++ cpu/x86/pc/olpc/via/dramtiming.fth 2009-05-14 08:55:20 UTC (rev 1198)
@@ -0,0 +1,40 @@
+d# 5.00 value Tck
+\ Compute ceil(ns/tck)
+: ns>tck ( ns -- tck ) Tck + 1- Tck / ;
+
+
+[ifdef] xo-board
+\ DDR-400 timings for HY5PS1G4831C
+d# 5.00 to Tck
+
+d# 127.50 constant Trfc
+d# 7.50 constant Trrd
+d# 3 constant TCL
+d# 40.00 constant Tras
+d# 15.00 constant Twr
+d# 7.50 constant Trtp
+d# 10.00 constant Twtr
+d# 15.00 constant Trp
+d# 15.00 constant Trcd
+
+1 constant #ranks
+8 constant #banks
+[then]
+
+[ifdef] demo-board
+\ DDR-533 timings for Micron MT8HTF6464HDY DIMM
+d# 3.75 to Tck
+
+d# 105.00 constant Trfc
+d# 10.00 constant Trrd
+d# 4 constant TCL
+d# 45.00 constant Tras
+d# 15.00 constant Twr
+d# 7.50 constant Trtp
+d# 7.00 constant Twtr
+d# 15.00 constant Trp
+d# 15.00 constant Trcd
+
+2 constant #ranks
+4 constant #banks
+[then]
Modified: cpu/x86/pc/olpc/via/ioinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/ioinit.fth 2009-05-14 08:19:39 UTC (rev 1197)
+++ cpu/x86/pc/olpc/via/ioinit.fth 2009-05-14 08:55:20 UTC (rev 1198)
@@ -179,8 +179,8 @@
bc ff 00 mreg \ SPI MMIO Base Address 15:8 (address is fed30000)
bd ff d3 mreg \ SPI MMIO Base Address 23:16
be ff fe mreg \ SPI MMIO Base Address 31:24
- d0 f0 00 mreg \ SMBUS IO Base Address low (port is 4100)
- d1 ff 41 mreg \ SMBUS IO Base Address high
+ d0 f0 00 mreg \ SMBUS IO Base Address low (port is 0500)
+ d1 ff 05 mreg \ SMBUS IO Base Address high
d2 0f 01 mreg \ Enable SMBUS and set other characteristics
e2 80 80 mreg \ Inhibit C4 during USB isochronous transaction
e4 ff a0 mreg \ Enable short C3/C4 (80), select various multi-function pins
Modified: cpu/x86/pc/olpc/via/romreset.bth
===================================================================
--- cpu/x86/pc/olpc/via/romreset.bth 2009-05-14 08:19:39 UTC (rev 1197)
+++ cpu/x86/pc/olpc/via/romreset.bth 2009-05-14 08:55:20 UTC (rev 1198)
@@ -56,6 +56,8 @@
fload ${BP}/cpu/x86/pc/olpc/via/startmacros.fth \ Via-oriented startup macros
+fload ${BP}/cpu/x86/pc/olpc/via/dramtiming.fth
+
start-assembling
hex
1
0
Author: wmb
Date: 2009-05-14 10:19:39 +0200 (Thu, 14 May 2009)
New Revision: 1197
Modified:
dev/via/unichrome/vgamodes.fth
Log:
Via text mode - improve the hsync adjustment value for better display centering.
Modified: dev/via/unichrome/vgamodes.fth
===================================================================
--- dev/via/unichrome/vgamodes.fth 2009-05-14 08:18:39 UTC (rev 1196)
+++ dev/via/unichrome/vgamodes.fth 2009-05-14 08:19:39 UTC (rev 1197)
@@ -15,7 +15,7 @@
: ext-textmode
use-vga-dac
h# ff h# e crt! h# ff h# f crt! \ Move the hardware cursor off-screen
- h# 04 h# 33 crt! \ Hsync adjustment
+ h# 01 h# 33 crt! \ Hsync adjustment
h# 10 h# 35 crt! \ Clear extended bits that can't be on for this mode's size
h# 00 h# 15 seq! \ Not using graphics modes
h# 0c h# 16 seq! \ FIFO
1
0
Author: wmb
Date: 2009-05-14 10:18:39 +0200 (Thu, 14 May 2009)
New Revision: 1196
Modified:
cpu/x86/pc/olpc/build/
cpu/x86/pc/olpc/via/build/
Log:
svn ignore some files.
Property changes on: cpu/x86/pc/olpc/build
___________________________________________________________________
Modified: svn:ignore
- build
ofw.elf
builton.fth
*.rom
*.bin
*.version
forth
sourceurl
*.md5
*.public
*.stamp
*.aml
*.dsl
multicast-nand
users
tags
fw.tag
+ build
ofw.elf
builton.fth
*.rom
*.bin
*.version
forth
sourceurl
*.md5
*.public
*.stamp
*.aml
*.dsl
multicast-nand
users
tags
fw.tag
memtest
Property changes on: cpu/x86/pc/olpc/via/build
___________________________________________________________________
Modified: svn:ignore
- *.txt
*.public
*.rom
*.version
tags
sourceurl
*.tag
build
builton.fth
VIA.ROM
+ *.txt
*.public
*.rom
*.version
tags
sourceurl
*.tag
build
builton.fth
VIA.ROM
*.bin
memtest
1
0