r1204 - cpu/x86/pc cpu/x86/pc/olpc/via dev/mmc/sdhci

Author: wmb
Date: 2009-05-28 01:07:49 +0200 (Thu, 28 May 2009)
New Revision: 1204

Added:
   cpu/x86/pc/olpc/via/startgtlinit.fth
   dev/mmc/sdhci/sdhcixo.bth
Modified:
   cpu/x86/pc/olpc/via/addrs.fth
   cpu/x86/pc/olpc/via/config.fth
   cpu/x86/pc/olpc/via/demodram.fth
   cpu/x86/pc/olpc/via/devices.fth
   cpu/x86/pc/olpc/via/dramtiming.fth
   cpu/x86/pc/olpc/via/fw.bth
   cpu/x86/pc/olpc/via/ioinit.fth
   cpu/x86/pc/olpc/via/olpc.bth
   cpu/x86/pc/olpc/via/romreset.bth
   cpu/x86/pc/olpc/via/sd8686.bth
   cpu/x86/pc/olpc/via/startcacheasram.fth
   cpu/x86/pc/olpc/via/startdraminit.fth
   cpu/x86/pc/olpc/via/startgfxinit.fth
   cpu/x86/pc/olpc/via/starthostctl.fth
   cpu/x86/pc/olpc/via/startmacros.fth
   cpu/x86/pc/olpc/via/versions.fth
   cpu/x86/pc/ramtest.fth
   cpu/x86/pc/resetend.fth
Log:
OLPV VIA version - checkpoint build that works on XO 1.5 Atest boards.


Modified: cpu/x86/pc/olpc/via/addrs.fth
===================================================================
--- cpu/x86/pc/olpc/via/addrs.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/addrs.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -8,7 +8,8 @@
 \ h# fffe.0000   constant rom-pa	\ Physical address of boot ROM
 \ h#    2.0000   constant /rom		\ Size of boot ROM
 rom-pa         constant dropin-base
-[else]
+[then]
+[ifdef] xo-board
 h# fff0.0000   constant rom-pa		\ Physical address of boot ROM
 h#   10.0000   constant /rom		\ Size of boot ROM
 rom-pa  h# 1.0000 +  constant dropin-base
@@ -18,7 +19,8 @@
 
 dropin-base h# 20 +  constant ResetBase	\ Location of "reset" dropin in ROM
 
-h# 1bc0.0000 value    fw-pa     \ Changed in probemem.fth
+\ h# 1bc0.0000 value    fw-pa     \ Changed in probemem.fth
+h#  bc0.0000 value    fw-pa     \ Changed in probemem.fth
 h#   20.0000 constant /fw-ram
 [then]
 

Modified: cpu/x86/pc/olpc/via/config.fth
===================================================================
--- cpu/x86/pc/olpc/via/config.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/config.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -3,7 +3,9 @@
 
 create olpc             \ OLPC-specific build
 
-create demo-board
+create compute-timings
+\ create demo-board
+create xo-board
 
 \ --- The environment that "boots" us ---
 \ - Image Format - Example Media - previous stage bootloader
@@ -11,9 +13,9 @@
 \ - OBMD format - ROM - direct boot from ROM
 create rom-loaded
 
-create coreboot-loaded
+\ create coreboot-loaded
 
-create virtual-mode
+\ create virtual-mode
 create addresses-assigned  \ Define if base addresses are already assigned
 \ create serial-console      \ Define to default to serial port for console
 create pc

Modified: cpu/x86/pc/olpc/via/demodram.fth
===================================================================
--- cpu/x86/pc/olpc/via/demodram.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/demodram.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -14,8 +14,13 @@
    \ Must use "CPU delay" to make sure VLINK is dis-connect
    0 7 devfunc  47 00 04 mreg  end-table  d# 20 wait-us
    0 3 devfunc  90 07 07 mreg  end-table  d# 20 wait-us  \ First set DRAM Freq to invalid
+[ifdef] demo-board
+   0 3 devfunc  90 07 04 mreg  end-table  d# 20 wait-us  \ 266 MHz !ATEST
+[then]
+[ifdef] xo-board
 \  0 3 devfunc  90 07 03 mreg  end-table  d# 20 wait-us  \ 200 MHz ATEST
-   0 3 devfunc  90 07 04 mreg  end-table  d# 20 wait-us  \ 266 MHz !ATEST
+   0 3 devfunc  90 e7 03 mreg  end-table  d# 20 wait-us  \ 200 MHz ATEST
+[then]
    0 3 devfunc  6b d0 c0 mreg  end-table  d# 20 wait-us  \ PLL Off
    0 3 devfunc  6b 00 10 mreg  end-table  d# 20 wait-us  \ PLL On
    0 3 devfunc  6b c0 00 mreg  end-table  \ Adjustments off
@@ -49,17 +54,22 @@
 
    62 07  TCL  2 -              mreg   \ CL 3
    62 08  08                    mreg   \ 8-bank timing constraint
+\ !!!
    62 f0  Tras ns>tck 5 - 4 <<  mreg   \ Tras: ceil( 40.00/5) = 8     - 5 = 0x03
 
 \  62 ff 3a mreg  \ CL, 8-bank constraint, Tras  Tras = 8T (3+5=8)
 
    63 e0  Twr  ns>tck 2 - 5 <<  mreg   \ Twr:  ceil( 15.00/5) = 3     - 2 = 0x01
-   63 08  Trtp ns>tck 2 - 3 <<  mreg   \ Trtp: ceil(  7.00/5) = 2     - 2 = 0x00
+\ !!!
+   63 08  Trtp ns>tck 2 - 3 <<  mreg   \ Trtp: ceil(  7.50/5) = 2     - 2 = 0x00
+\ !!!
    63 03  Twtr ns>tck 2 -       mreg   \ Twtr: ceil( 10.00/5) = 2     - 2 = 0x00
 
 \  63 ff 20 mreg  \ Twr, Twtr, Trtp  Twr=3T (15ns/5), Twtr=2T (10/5)  Trtp=2T ceil(7.5/5)
 
+\ !!!
    64 0e  Trp  ns>tck 2 - 1 <<  mreg   \ Trp:  ceil( 15.00/5) = 3     - 2 = 0x01
+\ !!!
    64 e0  Trcd ns>tck 2 - 5 <<  mreg   \ Trcd: ceil( 15.00/5) = 3     - 2 = 0x01
 
 \  64 ff 22 mreg  \ Trp 3, Trcd 3
@@ -69,6 +79,7 @@
 \ DRDR_BL.c
 \  DRAMDRDYsetting
    0 2 devfunc
+[ifdef] demo-board
    60 ff aa mreg  \ DRDY Timing Control 1 for Read Line
    61 ff 0a mreg  \ DRDY Timing Control 2 for Read Line
    62 ff 00 mreg  \ Reserved, probably channel B
@@ -79,11 +90,25 @@
    67 ff 00 mreg  \ Reserved, probably channel B
    54 0a 08 mreg  \ Misc ctl 1 - special mode for DRAM cycles
    51 80 80 mreg  \ Last step - enable DRDY timing
+[then]
+[ifdef] xo-board
+   60 ff 2a mreg  \ DRDY Timing Control 1 for Read Line
+   61 ff 00 mreg  \ DRDY Timing Control 2 for Read Line
+   62 ff 00 mreg  \ Reserved, probably channel B
+   63 ff 15 mreg  \ DRDY Timing Control 1 for Read QW
+   64 ff 00 mreg  \ DRDY Timing Control 2 for Read QW
+   65 ff 00 mreg  \ Reserved, probably channel B
+   66 ff 00 mreg  \ Burst DRDR Timing Control for Second cycle in burst
+   67 ff 00 mreg  \ Reserved, probably channel B
+   54 1e 1c mreg  \ Misc ctl 1 - special mode for DRAM cycles
+   51 ff f8 mreg  \ Last step - enable DRDY timing
+[then]
    end-table
 
 \  DRAMBurstLength
    0 3 devfunc
    6c 08 08 mreg  \ Burst length 8
+[ifdef] demo-board
 \ DrivingSetting.c
 \  DrivingODT
    d0 ff 88 mreg    \ Pull up/down Termination strength
@@ -120,6 +145,8 @@
 
 \  DRAMClkCtrl
 \   WrtDataPhsCtrl
+   70 ff 00 mreg \ Output delay
+   71 ff 04 mreg
    74 07 00 mreg \ DQS Phase Offset
    75 07 00 mreg \ DQ Phase Offset
    76 ef 07 mreg \ Write data Phase control
@@ -141,9 +168,87 @@
    78 3f 03 mreg \ DQS Input Capture Range Control A
    7a 0f 00 mreg \ Reserved
    7b 7f 20 mreg \ Read Data Phase Control
+[then]
 
-\   DCLKPhsCtrl
-   99 1e 12 mreg \ MCLKOA[4,3,0] outputs
+[ifdef] xo-board  \ DDR400
+\ DrivingSetting.c
+\  DrivingODT
+   d0 ff 88 mreg    \ Pull up/down Termination strength
+   d6 fc fc mreg    \ DCLK/SCMD/CS drive strength
+   d3 03 01 mreg    \ Compensation control - enable DDR Compensation
+   9f f3 00 mreg    \ 533,667,800: 11 SDRAM ODT Control 2 - Late extension values
+   d5 f0 00 mreg    \ DQ/DQS Burst and ODT Range Select - disable bursts for channel A
+   d7 c0 00 mreg    \ SCMD/MA Burst - Disable SDMD/MAA burst
+   d5 0f 05 mreg    \ Enable DRAM MD Pad ODT of Channel  A High 32 bits
+
+   9c ff e4 mreg    \ ODT Lookup table - XO uses ODT0 only
+   d4 3f 30 mreg    \ ChannelA MD ODT dynamic-on
+   9e ff 81 mreg    \ 533: 91 667: a1 800: a1 Enable Channel A differential DQS Input
+
+\  DrivingDQS,DQ,CS,MA,DCLK
+   e0 ff ee mreg \ DQS A
+   e2 ff ac mreg \ DQ A
+   e4 ff 44 mreg \ CS A
+   e8 ff 86 mreg \ MA A
+   e6 ff ff mreg \ MCLK A
+\  e1 ff ee mreg \ DQS B
+\  e3 ff ca mreg \ DQ B
+\  e5 ff 44 mreg \ CS B
+\  e9 ff 86 mreg \ MA B
+\  e7 ff ff mreg \ MCKL B
+
+\ ClkCtrl.c  (register tables in mainboard/via/6413e/DrivingClkPhaseData.c)
+\  DutyCycleCtrl
+   ec ff 30 mreg \ DQS/DQ Output duty control
+   ed ff 88 mreg \ 533: 84 667: 88 800: 88
+   ee ff 00 mreg \ 533: 00 667: 40 800: 40  DCLK Output duty control
+   ef 33 00 mreg \ DQ CKG Input Delay
+
+\  DRAMClkCtrl
+\   WrtDataPhsCtrl
+   70 ff 00 mreg \ Output delay
+   71 ff 05 mreg \ 533: 4 667: 6 800: 5
+   74 07 07 mreg \ DQS Phase Offset 533: 0 667: 0 800: 1
+   75 07 07 mreg \ DQ Phase Offset 533: 0 667: 0 800: 1
+   76 ef 06 mreg \ Write data Phase control  533: 7 667: 87 800: 80
+   8c 03 03 mreg \ DQS Output Control
+
+\   ClkPhsCtrlFBMDDR2
+   91 07 07 mreg \ DCLK Phase  533: 0 667: 1 800: 2
+   92 07 02 mreg \ CS/CKE Phase  533: 3 667: 3 800: 4
+   93 07 03 mreg \ SCMD/MA Phase  533: 4 667: 5 800: 6
+\ Channel B fields
+\  91 70 70 mreg \ DCLK Phase  533: 0 667: 10 800: 20
+\  92 70 20 mreg \ CS/CKE Phase  533: 30 667: 30 800: 40
+\  93 70 30 mreg \ SCMD/MA Phase  533: 40 667: 50 800: 60
+
+\   DQDQSOutputDlyCtrl
+   f0 77 00 mreg \ Group A0/1
+   f1 77 00 mreg \ Group A2/3
+   f2 77 00 mreg \ Group A4/5
+   f3 77 00 mreg \ Group A6/7
+
+   f4 77 00 mreg \ ?
+   f5 77 00 mreg \ ?
+   f6 77 00 mreg \ ?
+   f7 77 00 mreg \ ?
+
+\   DQSInputCaptureCtrl
+   77 bf 9b mreg \ DQS Input Delay - Manual, value from VIA's BIOS
+   78 3f 01 mreg \ 533: 3 667: 7 800: d  DQS Input Capture Range Control A
+   79 ff 83 mreg \ 533: 87 667: 89 800: 89
+   7a ff 00 mreg \ Reserved
+   7b ff 10 mreg \ 533: 20 667: 34 800: 34  Read Data Phase Control
+   8b ff 10 mreg \ 533: 20 667: 34 800: 34
+[then]
+
+\   DCLKPhsCtrl - depends on which clock outputs are used
+[ifdef] demo-board
+   99 1e 12 mreg \ MCLKOA[3,2,1,0] outputs
+[then]
+[ifdef] xo-board
+   99 1e 1e mreg \ MCLKOA[1,0] outputs
+[then]
    end-table
 
 \ DevInit.c
@@ -158,7 +263,7 @@
    54 ff 00 mreg \ default PR0=VR0; PR1=VR1
    55 ff 00 mreg \ default PR2=VR2; PR3=VR3
    56 ff 00 mreg \ default PR4=VR4; PR5=VR5
-   57 ff 00 mreg \ default PR4=VR4; PR5=VR5
+   57 ff 00 mreg \ default PR6=VR6; PR7=VR7
 
    60 ff 00 mreg \ disable fast turn-around
    65 ff d1 mreg \ AGP timer = D; Host timer = 1; (coreboot uses 9 for host timer)
@@ -166,7 +271,7 @@
    68 ff 0C mreg
    69 0F 04 mreg \ set RX69[3:0]=0000b
    6A ff 00 mreg \ refresh counter
-   6E 07 80 mreg \ must set 6E[7],or else DDR2  probe test will fail
+   6E 87 80 mreg \ must set 6E[7],or else DDR2  probe test will fail
    85 ff 00 mreg
    40 ff 00 mreg
    end-table
@@ -201,8 +306,14 @@
    end-table
 
    DDRinit #) call
+[else]
+   0 3 devfunc   
+   55 ff 00 mreg \ Disable ranks 2 and 3 and leave them off
+   end-table
 [then]
 
+   h# 12 port80
+
 forth  #ranks 3 >=  assembler  [if]
    0 3 devfunc
    41 ff 00 mreg \ Rank 1 top back to 0 to work on other ranks
@@ -224,6 +335,8 @@
    end-table
 [then]
 
+   h# 13 port80
+
 forth  #ranks 4 >=  assembler  [if]
    0 3 devfunc
    54 ff 00 mreg \ Disable ranks 0,1
@@ -239,96 +352,147 @@
    end-table
 [then]
 
+   h# 14 port80
+
    0 3 devfunc
-   69 03 03 mreg \ Reinstate page optimizations (03) - FF #ranks !ATEST
-\  69 c3 c3 mreg \ Reinstate page optimizations (03) - FF #ranks  ATEST 8-bank interleave
+forth #banks 8 = assembler [if]
+   69 c3 c3 mreg \ Reinstate page optimizations (03) 8-bank interleave (c0)
+[else]
+   69 c3 83 mreg \ Reinstate page optimizations (03) 4-bank interleave (80)
+[then]
 
+
 \ RankMap.c
 \  DRAMBankInterleave
 \   (see 69 above)
    87 ff 00 mreg \ Channel B #banks or some such - FF BA  
 \ SizingMATypeM
 
+
+[ifdef] compute-timings
+   50 ff  ma-type 5 <<  mreg
+[else]
    50 ff 20 mreg \ MA Map type - ranks 0/1 type 1 - 2 bank bits, 10 column bits !ATEST
+\ Check 1T command rate.  What controls it?
 \  50 ff a1 mreg \ 1T Command Rate, RMA Map type - ranks 0/1 type 5 - 3 bank bits, 14 row bits, 10 col bits ATEST
+[then]
+
    51 ff 60 mreg \ "Reserved"
    52 ff 33 mreg \ Bank interleave on A17, A18, and
-   53 ff 3f mreg \ A19 (but BA2 off because 4 banks), Rank interleave on A20 and A21  !ATEST
-\  53 ff bf mreg \ BA2 on (80), A19, Rank interleave on A20 and A21   ATEST
+
+forth #banks 8 =  [if]
+   53 ff bf mreg \ BA2 on (80), A19, Rank interleave on A20 and A21
+[else]
+   53 ff 3f mreg \ A19 (but BA2 off because 4 banks), Rank interleave on A20 and A21
+[then]
                  \ Different interleave bits might improve performance on some workloads
 
-   54 ff 89 mreg \ Rank map A 0/1   !ATEST
-\  54 ff 80 mreg \ Rank map A 0/1    ATEST  Rank 0 only
-   55 ff 00 mreg \ Rank map A 2/3
+forth #ranks 1 > assembler  [if]
+   54 ff 89 mreg \ Rank map A 0/1   Ranks 0 and 1
+[else]
+   54 ff 80 mreg \ Rank map A 0/1   Rank 0 only
+[then]
+
+forth #ranks 3 < assembler  [if]
+   55 ff 00 mreg \ Rank map A 2/3 2 & 3 off
+[then]
+forth #ranks 3 = assembler  [if]
+   55 ff a0 mreg \ Rank map A 2/3 2 on 3 off
+[else]
+   55 ff ab mreg \ Rank map A 2/3 2 & 3 on
+[then]
+
    56 ff 00 mreg \ Rank map B ?
    57 ff 00 mreg \ Rank map B ?
 
-   40 ff 04 mreg \ Rank top 0 !ATEST
-\  40 ff 10 mreg \ Rank top 0  ATEST  1 GiB
-   41 ff 08 mreg \ Rank top 1 !ATEST
-\  41 ff 00 mreg \ Rank top 1  ATEST
+   40 ff rank-top0 mreg \ Rank top 0  (register value in units of 64MB)
+   41 ff rank-top1 mreg \ Rank top 1
+   42 ff rank-top2 mreg \ Rank top 2
+   43 ff rank-top3 mreg \ Rank top 3
 
-   42 ff 00 mreg \ Rank top 2
-   43 ff 00 mreg \ Rank top 3
-
-   48 ff 00 mreg \ Rank base 0
-   49 ff 04 mreg \ Rank base 1 !ATEST
-\  49 ff 00 mreg \ Rank base 1  ATEST
-   4a ff 00 mreg \ Rank base 2
-   4b ff 00 mreg \ Rank base 3
+   48 ff rank-base0 mreg \ Rank base 0
+   49 ff rank-base1 mreg \ Rank base 1
+   4a ff rank-base2 mreg \ Rank base 2
+   4b ff rank-base3 mreg \ Rank base 3
    end-table
 
-   20 8f60 config-wb                    \ DRAM Bank 7 ending address - controls DMA upstream !ATEST
-\  40 8f60 config-wb                    \ DRAM Bank 7 ending address - controls DMA upstream  ATEST
+   h# 15 port80
+
+   total-size  8f60 config-wb  \ DRAM Bank 7 ending address - controls DMA upstream
    0388 config-rb  ax bx mov  0385 config-setup  bx ax mov  al dx out  \ Copy Low Top from RO reg 88 to reg 85
    0388 config-rb  ax bx mov  8fe5 config-setup  bx ax mov  al dx out  \ Copy Low Top from RO reg 88 to SB Low Top e5
 
-0 [if]  \ Very simple memtest
+\   d# 17 7 devfunc
+\   e6 ff 07 mreg \ Enable Top, High, and Compatible SMM
+\   end-table
+
+1 [if]  \ Very simple memtest
+long-offsets on
 ax ax xor
-h# 12345678 #  bx mov
-bx 0 [ax] mov
-h# 5555aaaa #  4 [ax] mov
-0 [ax] dx  mov
-dx bx cmp  =  if
-   ascii G report  ascii 2 report  h# 20 report
+h# 12345678 #  bx mov      \ Data value to write to address 0
+bx 0 [ax] mov              \ Write to address 0
+h# 5555aaaa #  h# 40 [ax] mov  \ Write 5555aaaa to address 0x40
+0 [ax] dx  mov             \ Read from address 0 into register EDX
+dx bx cmp  =  if           \ Compare expected value (EBX) with read value (EDX)
+   \ Compare succeeded
+\   ascii G report  ascii 2 report  h# 20 report  \ Display "G2 " - Good
 else
-   dx ax mov  dot #) call
-   ascii B report  ascii 2 report  h# 20 report
+   \ Compare failed
+   dx ax mov  dot #) call  \ Display read value
+   ascii B report  ascii 2 report  h# 20 report  \ Display "B2 " - Bad
+
+   h# ffff.0000 # ax mov   ax call  \ C Forth
+
    hlt
 then
 [then]
 
-\   d# 17 7 devfunc
-\   e6 ff 07 mreg \ Enable Top, High, and Compatible SMM
-\   end-table
+   h# 16 port80
 
 \ DQSSearch.c
 \  DRAMDQSOutputSearch
    0 3 devfunc
-   70 ff 00 mreg \ Output delay
-   71 ff 04 mreg
 
 \  DRAMDQSInputSearch
-   77 ff 00 mreg \ Input delay auto
+\  Leave the following set to the manual value.
+\  Eventually we should implement an auto-search
+\  77 ff 00 mreg \ Input delay auto
 
 \ FinalSetting.c
 \  RefreshCounter
+[ifdef] demo-board
    6a ff 86 mreg \ Refresh interval - FF frequency !ATEST
-\  6a ff ca mreg \ Refresh interval - FF frequency  ATEST
+[then]
+[ifdef] xo-board
+   6a ff 65 mreg \ Refresh interval - FF frequency  ATEST
+[then]
 
 \  DRAMRegFinalValue
     60 00 d0 mreg \ Fast turn-around
     66 30 80 mreg \ DRAMC queue = 4 (already set to 88 up above), park at last owner
     69 00 07 mreg \ Enable multiple page
+[ifdef] demo-board
     95 ff 0d mreg \ Self-refresh controls
-    96 f0 a0 mreg \ Auto self-refresh stuff
+[then]
+[ifdef] xo-board
+    95 ff 03 mreg \ Self-refresh controls, depends on #ranks
+[then]
+    96 f0 a0 mreg \ Enable pairwise by-rank self refresh, after 2 auto-refreshes
     fb ff 3e mreg \ Dynamic clocks
     fd ff a9 mreg \ Dynamic clocks
     fe ff 0f mreg \ Chips select power saving for self-refresh
     ff ff 3d mreg \ DSQB input delay, SCMD enabled
+[ifdef] demo-board
     96 0f 03 mreg \ Enable self-refresh for ranks 0 and 1
+[then]
+[ifdef] xo-board
+    96 0f 01 mreg \ Enable self-refresh for rank 0
+[then]
+
     end-table
     
+   h# 17 port80
+
 1 [if]
 ax ax xor
 h# 12345678 #  bx mov
@@ -337,5 +501,3 @@
 0 [ax] dx  mov
 dx bx cmp  <>  if  ascii B report  ascii A report  ascii D report  begin again  then
 [then]
-
-\ fload ${BP}/cpu/x86/pc/ramtest.fth

Modified: cpu/x86/pc/olpc/via/devices.fth
===================================================================
--- cpu/x86/pc/olpc/via/devices.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/devices.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -92,10 +92,10 @@
 
 \ Create a node below the top-level FLASH node to accessing the portion
 \ containing the dropin modules
-0 0  " 80000"  " /flash" begin-package
+0 0  " 10000"  " /flash" begin-package
    " dropins" device-name
 
-   h# 70000 constant /device
+   h# d0000 constant /device
    fload ${BP}/dev/subrange.fth
 end-package
 

Modified: cpu/x86/pc/olpc/via/dramtiming.fth
===================================================================
--- cpu/x86/pc/olpc/via/dramtiming.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/dramtiming.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -1,24 +1,61 @@
 d#   5.00 value Tck
+0 value #ranks
+0 value #banks
+0 value #row-bits 
+0 value #col-bits 
+
 \ Compute ceil(ns/tck)
 : ns>tck  ( ns -- tck )  Tck + 1-  Tck /  ;
 
+: ma-type  ( -- ma-type-code )
+   #banks 8 =  if     ( )
+      #col-bits 5 -   ( ma-type )
+      dup 7 u>        ( ma-type error? )
+   else               ( )
+      #col-bits 9 -   ( ma-type )
+      dup 3 u>        ( ma-type error? )
+   then
+   abort" Invalid MA type"
+;
 
+\ The 3 << is because of the 64-bit data width, i.e. 8 bytes, i.e. 1 << 3
+\ We compute carefully to prevent overflow or underflow
+: rank-size  ( -- rank-64mb )
+   1  #row-bits #col-bits + 3 + d# 20 - <<   ( bank-mb )
+   #banks *                                  ( rank-mb )
+   6 >>                                      ( rank-64mb )
+;
+
 [ifdef] xo-board
+.( Using XO timings) cr
+
 \ DDR-400 timings for HY5PS1G4831C
 d#   5.00 to Tck
 
 d# 127.50 constant Trfc
 d#   7.50 constant Trrd
+\ d#  10.00 constant Trrd
 d#      3 constant TCL
-d#  40.00 constant Tras
+\ d#  40.00 constant Tras
+ d#  45.00 constant Tras
 d#  15.00 constant Twr
-d#   7.50 constant Trtp
+ d#   7.50 constant Trtp
+\  d#  10.00 constant Trtp
 d#  10.00 constant Twtr
 d#  15.00 constant Trp
 d#  15.00 constant Trcd
 
-1 constant #ranks
-8 constant #banks
+1 to #ranks
+8 to #banks
+d# 10 to #col-bits
+d# 14 to #row-bits
+
+0 constant rank-base0  rank-size constant rank-top0
+0 constant rank-base1  0 constant rank-top1
+0 constant rank-base2  0 constant rank-top2
+0 constant rank-base3  0 constant rank-top3
+
+rank-size #ranks * constant total-size
 [then]
 
 [ifdef] demo-board
@@ -35,6 +72,16 @@
 d#  15.00 constant Trp
 d#  15.00 constant Trcd
 
-2 constant #ranks
-4 constant #banks
+2 to #ranks
+4 to #banks
+d# 10 to #col-bits
+\ d# 14 to #row-bits
+
+0         constant rank-base0  rank-size              constant rank-top0
+rank-top0 constant rank-base1  rank-base0 rank-size + constant rank-top1
+
+0 constant rank-base2  0 constant rank-top2
+0 constant rank-base3  0 constant rank-top3
+
+rank-size #ranks * constant total-size
 [then]

Modified: cpu/x86/pc/olpc/via/fw.bth
===================================================================
--- cpu/x86/pc/olpc/via/fw.bth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/fw.bth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -470,7 +470,6 @@
 
 fload ${BP}/cpu/x86/pc/olpc/via/memtest.fth
 
-[ifdef] Later
 fload ${BP}/ofw/wifi/wifi-cfg.fth
 support-package: supplicant
 fload ${BP}/ofw/wifi/loadpkg.fth
@@ -481,6 +480,7 @@
 ;
 ' olpc-ssids to default-ssids
 
+[ifdef] Later
 fload ${BP}/cpu/x86/pc/olpc/nandcastui.fth
 fload ${BP}/cpu/x86/pc/olpc/wifichannel.fth
 fload ${BP}/cpu/x86/pc/olpc/fsupdate.fth

Modified: cpu/x86/pc/olpc/via/ioinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/ioinit.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/ioinit.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -69,11 +69,13 @@
    8f 09 01 mreg  \ Falling edge trigger on slot 3 output clock under high speed
 [ifdef] demo-board
    99 ff f9 mreg  \ Two slots
-[else]
+[then]
+[ifdef] xo-board
    99 ff fa mreg  \ Three slots
 [then]
    end-table
 
+0 [if]
    d# 15 0 devfunc  \ EIDE tuning
    40 02 02 mreg  \ Enable primary channel
    4a ff 5e mreg  \ Drive1 timing
@@ -86,6 +88,7 @@
 \  d4 ac 24 mreg  \ Config 3
    d4 bc 34 mreg  \ Config 3 - 10 res be like Phx
    end-table
+[then]
 
    \ USB Tuning
    d# 16 0 devfunc  \ UHCI Ports 0,1
@@ -128,6 +131,9 @@
 
    d# 17 0 devfunc  \ Bus control and power management
    40 44 44 mreg  \ Enable I/O Recovery time (40), Enable ports 4d0/4d1 for edge/level setting (04)
+[ifdef] xo-board
+   41 40 40 mreg  \ Enable fff0.0000-fff7.ffff ROM on LPC bus
+[then]
    42 fc f0 mreg  \ Various setting related to DMA line  buffers
    43 0f 0b mreg  \ Enable PCI delayed transactions (08), Write transaction timer (02), Read transaction timer (01)
 \  4d 01 01 mreg  \ Enable LPC TPM
@@ -135,6 +141,9 @@
    4e 18 18 mreg  \ Enable ports 74/75 for CMOS RAM access  - 10 res be like Phx
 \  50 40 40 mreg  \ Disable USB device mode
    50 c0 c0 mreg  \ Disable USB device mode - 80 res be like Phx
+[ifdef] xo-board
+   51 9f 88 mreg  \ Enable SDIO and internal RTC, disable card reader, int mouse & kbd
+[then]
    52 1b 19 mreg  \ No wait state between SIRQ transactions (10), Enable SIRQ (08), SIRQ frame is 6 clocks (3>1)
    53 80 80 mreg  \ Enable PC/PCI DMA
    55 ff a0 mreg  \ INTA and External General interrupt routing - INTA:IRQ10
@@ -160,16 +169,28 @@
    8a 9f 1f mreg  \ C-state auto switching with normal latencies
 [ifdef] demo-board
    8d 18 18 mreg  \ fast clock as throttle timer tick, hold SMI# low until event status cleared (FIXME for OLPC)
-[else]
+[then]
+[ifdef] xo-board
    8d 18 10 mreg  \ fast clock as throttle timer tick, do not hold SMI# low
 [then]
    
    94 ff 68 mreg  \ be like Phx
    95 ff c1 mreg  \ be like Phx
+[ifdef] demo-board
    97 ff 80 mreg  \ be like Phx 
+[then]
+[ifdef] xo-board
+   97 ff 81 mreg  \ GPIO4/5 not KBDT/KBCK
+[then]
 
    9b ff 88 mreg  \ 80 res be like Phx
+
+[ifdef] xo-board
+   9f ff 08 mreg  \ Slot 3 is SDIO, no pullup on KB/MS, fastest SD
+[then]
+[ifdef] demo-board
    9f ff ad mreg  \ be like Phx (slot 3 is Card Reader not SDIO)
+[then]
 
    b4 80 00 mreg  \ No positive decoding for UART1 ???
    b7 40 40 mreg  \ 40 res be like Phx
@@ -183,7 +204,12 @@
    d1 ff 05 mreg  \ SMBUS IO Base Address high
    d2 0f 01 mreg  \ Enable SMBUS and set other characteristics
    e2 80 80 mreg  \ Inhibit C4 during USB isochronous transaction
+[ifdef] demo-board
    e4 ff a0 mreg  \ Enable short C3/C4 (80), select various multi-function pins
+[then]
+[ifdef] xo-board
+   e4 ff c0 mreg  \ Enable short C3/C4 (80), select GPO10 (10) (USB_PWR_EN)
+[then]
    e5 60 60 mreg  \ Enable NM bus master as source of bus master status, enable NB int to wakeup from Cx
    e6 20 20 mreg  \ Enable USB Device Mode Bus Master as Break Event
    e7 80 80 mreg  \ Enable APIC Cycle Reflect to ALL Bus Master Activity Effective Signal

Modified: cpu/x86/pc/olpc/via/olpc.bth
===================================================================
--- cpu/x86/pc/olpc/via/olpc.bth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/olpc.bth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -9,6 +9,7 @@
 in: ${BP}/cpu/x86/pc/olpc/via/build/paging.di
 in: ${BP}/cpu/x86/pc/olpc/via/build/fw.dic
 in: ${BP}/dev/mmc/sdhci/build/sdhci2.fc
+in: ${BP}/dev/mmc/sdhci/build/sdhcixo.fc
 in: ${BP}/dev/mmc/sdhci/build/sdmmc.fc
 in: ${BP}/dev/mmc/sdhci/mv8686/build/mv8686.fc
 in: ${BP}/dev/usb2/hcd/ohci/build/ohci.fc
@@ -58,7 +59,7 @@
 " ${FW_VERSION}.rom" expand$  2dup lower  ( adr len )
 2dup type cr  ( adr len )
 $new-file
-[ifdef] Later
+[ifdef] xo-board
    " ec.img"                $add-file
 [then]
 
@@ -78,7 +79,8 @@
 
    " paging.di"             $add-file
    " ${BP}/cpu/x86/build/inflate.bin"        " inflate"         $add-dropin
-   " fw.img"   " firmware"  $add-deflated-dropin
+\   " fw.img"   " firmware"  $add-deflated-dropin
+   " fw.img"   " firmware"  $add-dropin
 
    " ${BP}/dev/usb2/hcd/ohci/build/ohci.fc"	" class0c0310"      $add-deflated-dropin
    " ${BP}/dev/usb2/hcd/ehci/build/ehci.fc"	" class0c0320"      $add-deflated-dropin
@@ -93,7 +95,12 @@
    " ${BP}/dev/pci/build/pcibridg.fc"            " class060400"   $add-deflated-dropin
 \   " ${BP}/dev/ide/build/leghier.fc"             " class01018a"   $add-deflated-dropin
    " ${BP}/dev/ide/build/idehier.fc"             " class01018a"   $add-deflated-dropin
+[ifdef] xo-board
+   " ${BP}/dev/mmc/sdhci/build/sdhcixo.fc"       " class080501"   $add-deflated-dropin
+[then]
+[ifdef] demo-board
    " ${BP}/dev/mmc/sdhci/build/sdhci2.fc"        " class080501"   $add-deflated-dropin
+[then]
    " ${BP}/dev/mmc/sdhci/build/sdmmc.fc"         " sdmmc"         $add-deflated-dropin
    " ${BP}/dev/mmc/sdhci/mv8686/build/mv8686.fc" " mv8686"        $add-deflated-dropin
    " sd8686_helper.bin"                          " helper_sd.bin" $add-deflated-dropin
@@ -101,9 +108,9 @@
 
    " builton.fth"                       " probe-"          $add-dropin
 
-   " ${BP}/clients/emacs/x86/emacs"             " emacs"         $add-deflated-dropin
-   " ${BP}/clients/emacs/x86/emacs.rc"          " emacs.rc"      $add-deflated-dropin
-   " ${BP}/clients/emacs/emacs.hlp"             " emacs.hlp"     $add-deflated-dropin
+\   " ${BP}/clients/emacs/x86/emacs"             " emacs"         $add-deflated-dropin
+\   " ${BP}/clients/emacs/x86/emacs.rc"          " emacs.rc"      $add-deflated-dropin
+\   " ${BP}/clients/emacs/emacs.hlp"             " emacs.hlp"     $add-deflated-dropin
 
    " ${BP}/ofw/fcode/memtest.fth"  " memtest.fth"          $add-deflated-dropin
 
@@ -164,6 +171,9 @@
    /rom h# 10000 - pad-file	\ coreboot init image must be in last FLASH block
    " coreboot.img"   $add-file
 [else]
+   /rom h# 10000 - pad-file	\ coreboot init image must be in last FLASH block
+   " cforth.img"     $add-file  \ Small Forth that runs from cache
+
    /rom h# 400 - pad-file	\ rmstart image must start 0x400 from end
    " rmstart.img"    $add-file
 

Modified: cpu/x86/pc/olpc/via/romreset.bth
===================================================================
--- cpu/x86/pc/olpc/via/romreset.bth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/romreset.bth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -52,7 +52,7 @@
 dropin-base /dcached - constant dcached-base
 
 h#   10.0000 constant ramtest-start
-h#   20.0000 constant ramtest-end
+h#  100.0000 constant ramtest-end
 
 fload ${BP}/cpu/x86/pc/olpc/via/startmacros.fth  \ Via-oriented startup macros
 
@@ -68,12 +68,16 @@
 
 fload ${BP}/cpu/x86/pc/romfind.fth	           \ find-dropin subroutine
 
+[ifdef] debug-startup
+fload ${BP}/cpu/x86/pc/dot.fth			   \ Numeric output subroutine
+fload ${BP}/cpu/x86/pc/olpc/via/startinteract.fth  \ emitpause subroutine
+[then]
+
 fload ${BP}/cpu/x86/pc/olpc/via/startusdelay.fth   \ microsecond delay subroutine
 fload ${BP}/cpu/x86/pc/olpc/via/startcfgio.fth     \ masked config write subroutine
 fload ${BP}/cpu/x86/pc/olpc/via/startdraminit.fth  \ DDRinit subroutine
 
 [ifdef] debug-startup
-fload ${BP}/cpu/x86/pc/dot.fth			   \ Numeric output subroutine
 fload ${BP}/cpu/x86/pc/olpc/via/startcominit.fth   \ cominit subroutine
 [then]
 
@@ -93,6 +97,10 @@
 
    00 8898 config-wb   \ Disable BIOS init timer GP3
 
+   08  00c config-wb   \ Cache line size D0F0
+   20  00d config-wb   \ PCI master latency timer D0F0
+   08  20c config-wb   \ Cache line size D0F2
+
 [ifdef] debug-startup
    cominit #) call
 [then]
@@ -120,14 +128,43 @@
    fload ${BP}/cpu/x86/pc/olpc/via/starthostctl.fth
    fload ${BP}/cpu/x86/pc/olpc/via/demodram.fth
 
-   char o report
-   h# 1e port80
+   fload ${BP}/cpu/x86/pc/olpc/via/startgfxinit.fth
 
+0 [if]  \ Fire up C Forth
+   dcached-base 6 +          0  206 set-msr   \ Dcache base address, write back
+   /dcached negate h# 800 +  f  207 set-msr   \ Dcache size
+   \ This region is for CForth
+   h# ffff.0000 6 +          0  208 set-msr   \ ROM base address
+   /icached negate h# 800 +  f  209 set-msr   \ Icache size
+
+   \ Access ROM to load it into the icache
+   h# ffff.0000 #  esi  mov
+   /icached 4 / #  ecx  mov
+   rep  eax lods
+
+   \ Access "RAM" area to load it into the dcache
+   dcached-base #  esi  mov
+   /dcached 4 / #  ecx  mov
+   rep  eax lods
+
+   \ Put the stack pointer at the top of the dcached area
+   dcached-base /dcached + 4 - #  esp  mov
+   ds ax mov  ax ss mov
+
+   h# ffff.0000 # ax mov  ax jmp
+[then]
+
+\  fload ${BP}/cpu/x86/pc/ramtest.fth
+
    fload ${BP}/cpu/x86/pc/olpc/via/startmtrrinit.fth
    \ Cache is now setup normally, backed by memory
-   'ebda # sp mov  \ Move stack to real memory
 
-   fload ${BP}/cpu/x86/pc/olpc/via/startgfxinit.fth
+   char o report
+   h# 1e port80
+
+\   fload ${BP}/cpu/x86/pc/olpc/via/startgtlinit.fth
+
+.( Not doing io init)
    fload ${BP}/cpu/x86/pc/olpc/via/ioinit.fth
 
 \ Enable the keyboard controller
@@ -137,6 +174,7 @@
 \   e2 2e port-wb   7 2f port-wb
 
    fload ${BP}/cpu/x86/pc/olpc/via/startmemtop.fth
+
    fload ${BP}/cpu/x86/pc/olpc/via/startcpuspeed.fth
 
    h# 1f port80

Modified: cpu/x86/pc/olpc/via/sd8686.bth
===================================================================
--- cpu/x86/pc/olpc/via/sd8686.bth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/sd8686.bth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -5,6 +5,9 @@
 
 fload ${BP}/cpu/x86/pc/olpc/via/versions.fth
 
+" ${GET_WLAN}" expand$  nip  [if]
+   " ${GET_WLAN}" expand$ $sh
+[else]
 " rm -f sd8686.bin sd8686_helper.bin" expand$ $sh
 
 " wget -q http://dev.laptop.org/pub/firmware/libertas/sd8686-${WLAN_VERSION}.bin" expand$ $sh
@@ -18,6 +21,7 @@
 " md5sum -b sd8686_helper.bin | cmp - sd8686_helper.bin.md5" expand$ $sh
 
 " rm sd8686-${WLAN_VERSION}.bin.md5 sd8686_helper.bin.md5" expand$ $sh
+[then]
 
 \ This forces the creation of a .log file, so we don't re-fetch
 writing sd8686.version

Modified: cpu/x86/pc/olpc/via/startcacheasram.fth
===================================================================
--- cpu/x86/pc/olpc/via/startcacheasram.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/startcacheasram.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -14,7 +14,11 @@
    /dcached negate h# 800 +  f  201 set-msr   \ Dcache size
    dropin-base 6 +           0  202 set-msr   \ ROM base address
    /icached negate h# 800 +  f  203 set-msr   \ Icache size
+   \ This region is for CForth
+   h# ffff.0000 6 +          0  204 set-msr   \ ROM base address
+   /icached negate h# 800 +  f  205 set-msr   \ Icache size
 
+
    00000000.00000800.           2ff set-msr   \ Enable variable MTRRs in DefType   
 
 
@@ -22,7 +26,7 @@
 
    cld
 
-   \ Access ROM to load it into the dcache
+   \ Access ROM to load it into the icache
    dropin-base #  esi  mov
    /icached 4 / #  ecx  mov
    rep  eax lods

Modified: cpu/x86/pc/olpc/via/startdraminit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startdraminit.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/startdraminit.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -23,11 +23,30 @@
    loopa
    
    13 36b config-wb  \ SDRAM MRS Enable
-   101258 #) ax mov  \ Depends on Twr, CL, and Burst Length
+\  101258 #) ax mov  \ Depends on Twr, CL, and Burst Length
+   1021d8 #) ax mov  \ Depends on Twr, CL, and Burst Length
 
+0 [if]
+2024b
+011 BL 8
+1 BT interleave
+100 CL 4  Anck
+0 TM normal
+0 DLL rst no
+001 WR 2  write recov for autoprecharge
+      2 and 3 are possible for 400
+0 PD fast exit from active power down
+000 ???
+
+      12
+10 0000
+10 BA1,0 EMR2
+[then]
+
    21e00 #) ax mov   \ For 150 ohm; 75 ohm is 21c20
    20200 #) ax mov   \ For 150 ohm; 75 ohm is 21c20
 
+
    10 36b config-wb  \ SDRAM Normal
 
    ret

Modified: cpu/x86/pc/olpc/via/startgfxinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startgfxinit.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/startgfxinit.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -1,7 +1,7 @@
 \ UMARamSetting.c
 \  SetUMARam
    0 3 devfunc
-   99 ff 73 mreg \ 61 res be like Phx
+ \ 99 ff 73 mreg \ 61 res be like Phx
    a1 00 80 mreg \ Enable internal GFX
    a2 ff ee mreg \ Set GFX timers
    a4 ff 01 mreg \ GFX Data Delay to Sync with Clock

Added: cpu/x86/pc/olpc/via/startgtlinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startgtlinit.fth	                        (rev 0)
+++ cpu/x86/pc/olpc/via/startgtlinit.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -0,0 +1,59 @@
+\ After-the-fact tweaks to ROMSIP values
+0 2 devfunc
+   70 ff 55 mreg
+   71 ff aa mreg
+   72 ff 66 mreg
+   73 ff cc mreg
+   74 00 00 mreg
+   75 0f 04 mreg
+   76 00 00 mreg
+   77 00 00 mreg
+   78 00 00 mreg
+   79 80 00 mreg
+   7a 00 00 mreg
+   7b 00 00 mreg
+   a0 f1 70 mreg
+   a1 ff d6 mreg
+   a2 ff 88 mreg
+   a3 03 00 mreg
+   a4 ff 77 mreg
+   a5 0f 07 mreg
+   a6 ff 77 mreg
+   a7 ff 77 mreg
+   a8 ff 77 mreg
+   a9 ff 77 mreg
+   aa 1c 04 mreg
+   af ff 77 mreg
+   ac ff 77 mreg
+   ad ff 77 mreg
+   ae ff 77 mreg
+   af ff 77 mreg
+   b0 ff 77 mreg
+   b1 ff 77 mreg
+   b2 ff 77 mreg
+   b3 ff 77 mreg
+   b4 ff 77 mreg
+   b5 ff 77 mreg
+   b6 ff 77 mreg
+   b7 ff 77 mreg
+   b8 ff 77 mreg
+   b9 ff 77 mreg
+   ba ff 77 mreg
+   bb ff 77 mreg
+   bc 00 00 mreg
+   bd 1f 14 mreg
+   be ff 77 mreg
+   bf ff 77 mreg
+   c0 b7 10 mreg
+   c1 b7 14 mreg
+   c2 b7 14 mreg
+   c3 ff 75 mreg
+   c4 b7 10 mreg
+   c5 b7 14 mreg
+   c6 b7 20 mreg
+   c7 b7 14 mreg
+   c8 00 00 mreg
+   c9 00 00 mreg
+   ca b7 10 mreg
+   cb b7 04 mreg
+end-table

Modified: cpu/x86/pc/olpc/via/starthostctl.fth
===================================================================
--- cpu/x86/pc/olpc/via/starthostctl.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/starthostctl.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -17,6 +17,8 @@
    0 2 devfunc  \ HOST CPU CTL
    50 1f 08 mreg  \ Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
    51 ff 78 mreg  \ CPU I/F Ctrl-1: Disable Fast DRDY and RAW (coreboot uses 7c)
+\ Try the following value !!
+\  51 ff f8 mreg  \ CPU I/F Ctrl-1: Enable Fast DRDY and RAW (coreboot uses 7c) 
    52 cb cb mreg  \ CPU I/F Ctrl-2: Enable all for performance
    53 ff 44 mreg  \ Arbitration: Host/Master Occupancy timer = 4*4 HCLK
    54 1e 1c mreg  \ Misc Ctrl: Enable 8QW burst Mem Access
@@ -27,6 +29,9 @@
    5e ff 88 mreg  \ Bandwidth Timer
    5f 46 46 mreg  \ CPU Misc Ctrl
 
+[ifdef] xo-board
+   90 03 03 mreg  \ 5T faster Host to DRAM cycles
+[then]
    96 0b 0a mreg  \ Write Policy
    98 c1 41 mreg  \ Bandwidth Timer
    99 0e 06 mreg  \ CPU Misc Ctrl

Modified: cpu/x86/pc/olpc/via/startmacros.fth
===================================================================
--- cpu/x86/pc/olpc/via/startmacros.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/startmacros.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -1,4 +1,5 @@
 : devfunc  ( dev func -- )
+\   ." Device " over .d  ." function " dup .d  cr
    h# 100 *  swap h# 800 * or  h# 8000.0000 or
    [ also assembler ]
    # ebp mov  " masked-config-writes" evaluate  #) call
@@ -6,7 +7,10 @@
 ;
 : end-table  0 c,  ;
 
-: mreg  ( reg# and or -- )  rot c, swap c, c,  ;
+: mreg  ( reg# and or -- )
+\   2 pick .2  over .2  dup .2  cr  \ Display the setup values at compile time
+   rot c, swap c, c,
+;
 : wait-us  ( us -- )
    " # ax mov  usdelay #) call" evaluate
 ;

Modified: cpu/x86/pc/olpc/via/versions.fth
===================================================================
--- cpu/x86/pc/olpc/via/versions.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/olpc/via/versions.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -2,14 +2,16 @@
 
 \ The overall firmware revision
 macro: FW_MAJOR A
-macro: FW_MINOR 02c
+macro: FW_MINOR 03d
 
 \ The EC microcode
-macro: EC_VERSION e34
+macro: EC_VERSION a00
 
 \ Alternate command for getting EC microcode, for testing new versions.
 \ Temporarily uncomment the line and modify the path as necessary
-\ macro: GET_EC cp pq2e18c.img ec.img
+\ macro: GET_EC cp pq3a00.img ec.img
+\ macro: GET_EC cp "/c/Documents and Settings/Mitch Bradley/My Documents/OLPC/VIA/ecimage.bin" ec.img
+macro: GET_EC cp /via/ecimage.bin ec.img
 
 macro: KEYS mpkeys
 \ macro: KEYS testkeys
@@ -17,6 +19,10 @@
 \ The wireless LAN module firmware
 macro: WLAN_VERSION 9.70.7.p0
 
+\ Alternate command for getting WLAN firmware, for testing new versions.
+\ Temporarily uncomment the line and modify the path as necessary
+macro: GET_WLAN cp "/c/Documents and Settings/Mitch Bradley/My Documents/OLPC/DiskImages/sd8686-9.70.7.p0.bin" sd8686.bin; cp "/c/Documents and Settings/Mitch Bradley/My Documents/OLPC/DiskImages/sd8686_helper.bin" sd8686_helper.bin
+
 \ The bios_verify image
 macro: CRYPTO_VERSION 0.2
 

Modified: cpu/x86/pc/ramtest.fth
===================================================================
--- cpu/x86/pc/ramtest.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/ramtest.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -15,7 +15,35 @@
 begin
    0 [ax] bx mov
    ax bx cmp  <>  if
+      ax di mov
       ascii B report  ascii A report  ascii D report
+      di ax mov  dot #) call
+      0 [di] ax mov  dot #) call
+1 [if]  \ Fire up C Forth
+   dcached-base 6 +          0  206 set-msr   \ Dcache base address, write back
+   /dcached negate h# 800 +  f  207 set-msr   \ Dcache size
+   \ This region is for CForth
+   h# ffff.0000 6 +          0  208 set-msr   \ ROM base address
+   /icached negate h# 800 +  f  209 set-msr   \ Icache size
+
+   \ Access ROM to load it into the icache
+   h# ffff.0000 #  esi  mov
+   /icached 4 / #  ecx  mov
+   rep  eax lods
+
+   \ Access "RAM" area to load it into the dcache
+   dcached-base #  esi  mov
+   /dcached 4 / #  ecx  mov
+   rep  eax lods
+
+   \ Put the stack pointer at the top of the dcached area
+   dcached-base /dcached + 4 - #  esp  mov
+   ds ax mov  ax ss mov
+
+   h# ffff.0000 # ax mov  ax jmp
+[then]
+
+
       begin again
    then
    4 # ax add
@@ -37,11 +65,13 @@
 begin
    0 [ax] bx mov
    h# 55555555 # bx cmp  <>  if
+      ( bx ax mov  ) dot #) call
       ascii B report  ascii A report  ascii D report
+      h# ffff.0000 # ax mov  ax jmp  \ CForth
       begin again
    then
    4 # ax add
-   ramtest-end ax # cmp
+   ramtest-end #  ax  cmp
 0= until
 ascii G report  ascii o report  ascii o report  ascii d report
 carret report  linefeed report

Modified: cpu/x86/pc/resetend.fth
===================================================================
--- cpu/x86/pc/resetend.fth	2009-05-27 22:58:18 UTC (rev 1203)
+++ cpu/x86/pc/resetend.fth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -110,8 +110,10 @@
       inflate-base #  ax  mov	\ Base address of inflater
       ax call			\ Inflate the firmware
    else
+      ax push
       h# 26 # al mov  al h# 80 # out
       ascii h report
+      ax pop
 
       \ The firmware dropin isn't compressed, so we just copy it to RAM
       4 [ax]          cx  mov	\ Length of firmware (byte-swapped)
@@ -119,8 +121,8 @@
 
       d# 32 [ax]      si  lea	\ si: Base address of firmware code in dropin
       fw-virt-base #  di  mov	\ Firmware RAM address (destination)
-      cld  rep byte movs	\ Copy the firmware
 
+      cx 2 # shr  cld  rep movs \ Copy the firmware
       ascii m report
    then
    long-offsets off

Added: dev/mmc/sdhci/sdhcixo.bth
===================================================================
--- dev/mmc/sdhci/sdhcixo.bth	                        (rev 0)
+++ dev/mmc/sdhci/sdhcixo.bth	2009-05-27 23:07:49 UTC (rev 1204)
@@ -0,0 +1,29 @@
+purpose: Load file for SDHCI (Secure Digital Host Controller Interface)
+
+command: &tokenize &this
+build-now
+
+silent on
+
+begin-tokenizing sdhcixo.fc
+
+FCode-version2
+fload ${BP}/dev/mmc/sdhci/sdhci.fth
+
+init
+
+new-device
+   2 encode-int " reg" property
+   " sdmmc" " $load-driver" eval drop
+finish-device
+
+new-device
+   1 encode-int " reg" property
+   " mv8686" " $load-driver" eval drop
+finish-device
+
+
+fload ${BP}/dev/mmc/sdhci/selftest.fth
+end0
+
+end-tokenizing