openfirmware January 2011

openfirmware@openfirmware.info

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[commit] r2119 - forth/wrapper/zip
by repository service 19 Jan '11

19 Jan '11

Author: wmb Date: Wed Jan 19 08:05:12 2011 New Revision: 2119 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2119 Log: inflate.c - removed a small vestige of GPL code (a single #define) so the code is clean - based on stuff that Mark Adler's put in the public domain. Modified: forth/wrapper/zip/inflate.c Modified: forth/wrapper/zip/inflate.c ============================================================================== --- forth/wrapper/zip/inflate.c Tue Jan 18 22:41:32 2011 (r2118) +++ forth/wrapper/zip/inflate.c Wed Jan 19 08:05:12 2011 (r2119) @@ -70,12 +70,6 @@ [OK: Changes for Open Firmware by Mike Tuciarone, June 1994.] */ -/* gzip.h -- common declarations for all gzip modules - * Copyright (C) 1992-1993 Jean-loup Gailly. - * This is free software; you can redistribute it and/or modify it under the - * terms of the GNU General Public License, see the file COPYING. - */ - #define u_long unsigned long #define u_short unsigned short #define u_char unsigned char @@ -86,8 +80,7 @@ static int huft_fixed(); static int huft_dynamic(); -/* gzip flag byte */ -#define ORIG_NAME 0x08 /* bit 3 set: original file name present */ +#define FILENAME_PRESENT 0x08 /* flag byte bit meaning filename follows */ /* ROM * Workspace definitions @@ -207,7 +200,7 @@ flags = NEXTBYTE; for (n = 0; n < 6; ++n) (void) NEXTBYTE; - if (flags & ORIG_NAME) + if (flags & FILENAME_PRESENT) while (NEXTBYTE) ; }

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[commit] r2118 - cpu/arm/olpc/1.75/build cpu/x86/Linux forth/wrapper
by repository service 18 Jan '11

18 Jan '11

Author: wmb Date: Tue Jan 18 22:41:32 2011 New Revision: 2118 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2118 Log: ARM - More fixes to cross-build makefiles. Modified: cpu/arm/olpc/1.75/build/Makefile cpu/x86/Linux/Makefile forth/wrapper/wrapper.c Modified: cpu/arm/olpc/1.75/build/Makefile ============================================================================== --- cpu/arm/olpc/1.75/build/Makefile Tue Jan 18 22:18:33 2011 (r2117) +++ cpu/arm/olpc/1.75/build/Makefile Tue Jan 18 22:41:32 2011 (r2118) @@ -18,12 +18,15 @@ tags: ${ROMNAME}.tag @${BASEDIR}/forth/lib/toctags ${BASEDIR} ${TAGFILES} -${ROMNAME}.rom: FORCE build ${CLIENTPROGS} ${HOSTDIR}/forth +${ROMNAME}.rom: FORCE build ${CLIENTPROGS} ${HOSTDIR}/forth ${HOSTDIR}/armforth ./build $@ ${HOSTDIR}/forth: @make -C ${HOSTDIR} forth +${HOSTDIR}/armforth: + @make -C ${HOSTDIR} armforth + ../../build/inflate.bin: @make -C ../../build inflate.bin Modified: cpu/x86/Linux/Makefile ============================================================================== --- cpu/x86/Linux/Makefile Tue Jan 18 22:18:33 2011 (r2117) +++ cpu/x86/Linux/Makefile Tue Jan 18 22:41:32 2011 (r2118) @@ -45,9 +45,6 @@ %.o: ${ZIPDIR}/%.c ${CC} -c ${CFLAGS} -I${ZIPDIR} $< -o $@ -%.o: ${ARMDIR}/%.c - ${CC} -c ${ARMCFLAGS} $< -o $@ - # ARM simulator wrapper build rules ARMDIR = ${BP}/cpu/arm @@ -55,6 +52,9 @@ ARMSIMOBJS = wrapsim.o armsim.o logger.o ${ZIPOBJS} ARMTRACEOBJS = wrapsim.o armsim.trace.o logger.o ${ZIPOBJS} +%.o: ${ARMDIR}/%.c + ${CC} -c ${ARMCFLAGS} $< -o $@ + wrapsim.o: ${WRDIR}/wrapper.c ${CC} -c ${ARMCFLAGS} -c $< -o $@ Modified: forth/wrapper/wrapper.c ============================================================================== --- forth/wrapper/wrapper.c Tue Jan 18 22:18:33 2011 (r2117) +++ forth/wrapper/wrapper.c Tue Jan 18 22:41:32 2011 (r2118) @@ -1005,10 +1005,6 @@ # ifdef PPCSIM printf("PowerPC Instruction Set Simulator\n"); printf("Copyright 1994 FirmWorks All rights reserved\n"); -# elif ARMSIM - printf("ARM Instruction Set Simulator\n"); - printf("Copyright 1994 FirmWorks All rights reserved\n"); - printf("Copyright 2010 Apple, Inc. All rights reserved\n"); # endif loadaddr = (char *)m_alloc(dictsize);

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[commit] r2117 - in cpu: arm/build x86/Linux
by repository service 18 Jan '11

18 Jan '11

Author: wmb Date: Tue Jan 18 22:18:33 2011 New Revision: 2117 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2117 Log: ARM - Improvements in ARM cross-build makefiles. Deleted: cpu/x86/Linux/Makefile.armforth Modified: cpu/arm/build/Makefile cpu/x86/Linux/Makefile Modified: cpu/arm/build/Makefile ============================================================================== --- cpu/arm/build/Makefile Tue Jan 18 21:49:15 2011 (r2116) +++ cpu/arm/build/Makefile Tue Jan 18 22:18:33 2011 (r2117) @@ -2,7 +2,7 @@ OS := $(shell uname) HOSTCPU= $(shell ${BASEDIR}/forth/lib/hostcpu.sh) -HOSTDIR= ../${HOSTCPU}/${OS} +HOSTDIR= ../../${HOSTCPU}/${OS} BUILDSH= ${BASEDIR}/forth/lib/build.sh all: basefw.dic @@ -11,10 +11,13 @@ .PRECIOUS: builder.dic -../${OS}/forth: - @make -C ../${OS} forth +${HOSTDIR}/forth: + @make -C ${HOSTDIR} forth -build: +${HOSTDIR}/armforth: + @make -C ${HOSTDIR} armforth + +build: ${HOSTDIR}/forth ${HOSTDIR}/armforth @ln -sf ${BUILDSH} build # build: ../${OS}/forth Modified: cpu/x86/Linux/Makefile ============================================================================== --- cpu/x86/Linux/Makefile Tue Jan 18 21:49:15 2011 (r2116) +++ cpu/x86/Linux/Makefile Tue Jan 18 22:18:33 2011 (r2117) @@ -45,5 +45,27 @@ %.o: ${ZIPDIR}/%.c ${CC} -c ${CFLAGS} -I${ZIPDIR} $< -o $@ +%.o: ${ARMDIR}/%.c + ${CC} -c ${ARMCFLAGS} $< -o $@ + +# ARM simulator wrapper build rules + +ARMDIR = ${BP}/cpu/arm +ARMCFLAGS = -g -m32 -DARMSIM -DTARGET_ARM -DARM -DSIMNEXT +ARMSIMOBJS = wrapsim.o armsim.o logger.o ${ZIPOBJS} +ARMTRACEOBJS = wrapsim.o armsim.trace.o logger.o ${ZIPOBJS} + +wrapsim.o: ${WRDIR}/wrapper.c + ${CC} -c ${ARMCFLAGS} -c $< -o $@ + +armsim.trace.o: $(ARMDIR)/armsim.c + ${CC} -c ${ARMCFLAGS} -DTRACE=1 -c $< -o $@ + +armforth: ${ARMSIMOBJS} + ${CC} ${ARMSIMOBJS} -o $@ + +armforth.trace: ${ARMTRACEOBJS} + ${CC} ${ARMTRACEOBJS} -o $@ + clean: - @rm -f forth x86forth *.o *~ inflate.bin + @rm -f forth x86forth armforth *.o *~ inflate.bin

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[commit] r2116 - cpu/arm
by repository service 18 Jan '11

18 Jan '11

Author: wmb Date: Tue Jan 18 21:49:15 2011 New Revision: 2116 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2116 Log: ARM - initial checkin of ARM simulator. Added: cpu/arm/armsim.c Added: cpu/arm/armsim.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/armsim.c Tue Jan 18 21:49:15 2011 (r2116) @@ -0,0 +1,1199 @@ +// +// ARM32 Application-level simulator. +// +// +// Copyright (c) 2007 FirmWorks +// Copyright 2010 Apple, Inc. All rights reserved. +// See license at end. + +#include <stdio.h> +#include <stdlib.h> +#include <signal.h> + +typedef char s8; +typedef short s16; +typedef int s32; +typedef long long s64; +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +typedef unsigned long long u64; + +static u32 trace = 0; + +//#if TRACE +#define INSTR(a) if (trace) printf("%s -- %0x N%d Z%d C%d V%d %s\n", \ + a, COND, N, Z, C, V, cond ? "true" : "false"); \ + if (cond == 0) break +//#else +//#define INSTR(a) if (cond == 0) break +//#endif + +#define MAXMEM 0x80000 +#define MEM(type, adr) *(type *)(&mem[(adr)]) + +u32 r[16]; +#define SP r[13] +#define LR r[14] +#define PC r[15] + +void regdump(u32 instruction, u32 last_pc, u8 cr) +{ + printf(" 0 %08x 1 %08x 2 %08x 3 %08x\n", r[0], r[1], r[2], r[3]); + printf(" 4 %08x 5 %08x 6 %08x 7 %08x\n", r[4], r[5], r[6], r[7]); + printf(" 8 %08x 9 %08x a %08x b %08x\n", r[8], r[9], r[10], r[11]); + printf(" c %08x d %08x e %08x f %08x\n", r[12], r[13], r[14], r[15]); + printf("pc %08x lpc %08x i %08x ", PC - 8, last_pc, instruction); + if (cr) + putchar('\n'); +} + +#define UFIELD(lbit,nbits) ( (instruction << (31 - lbit)) >> (32 - nbits)) +#define SFIELD(lbit,nbits) ((long)(instruction << (31 - lbit)) >> (32 - nbits)) + +#define COND UFIELD(31, 4) +#define OP UFIELD(27, 7) +#define S UFIELD(20, 1) +#define L UFIELD(20, 1) +#define RD r[UFIELD(15, 4)] +#define RN r[UFIELD(19, 4)] +#define RM r[UFIELD( 3, 4)] +#define RS r[UFIELD(11, 4)] +#define TYPE UFIELD( 6, 2) +#define IMM5 UFIELD(11, 5) +#define OP1 UFIELD( 4, 1) +#define OP2 UFIELD( 7, 1) +#define ROT UFIELD(11, 4) +#define IMM8 UFIELD( 7, 8) +#define IMM24 UFIELD(23,24) +#define LINK UFIELD( 5, 1) +#define MSB UFIELD(20, 5) +#define LSB UFIELD(11, 5) +#define BXTYPE UFIELD( 7, 4) +#define IMM12 UFIELD(11,12) +#define IMM16 ((UFIELD(19, 4) << 12) | IMM12) +#define IMMHL ((UFIELD(11, 4) << 4) | UFIELD( 3, 4)) +#define P UFIELD(24, 1) +#define U UFIELD(23, 1) +#define W UFIELD(21, 1) + +// In BTGT we want to force a PC update. Since we don't implement Thumb +// the value "1" must always be invalid for last_pc. +struct { signed int imm24:24; } sext24; +#define BTGT { PC += sext24.imm24 = (IMM24 << 2); last_pc = 1; } + +#define ROTATE(imm, rot) (((imm) >> (rot)) | ((imm) << (32-(rot)))) +#define IMM32 ROTATE(IMM8, (ROT<<1)) + +#define SHSRC (OP1 ? RS : IMM5) +#define SHFT(res) \ +{ \ + switch (TYPE) { \ + case 0: res = RM << SHSRC; break; \ + case 1: res = RM >> SHSRC; break; \ + case 2: if (SHSRC == 0) { res = ((s32)(RM) < 0) ? -1 : 0; } else { res = (s32)(RM) >> SHSRC; } break; \ + case 3: res = ROTATE(RM, SHSRC); \ + } \ +} + +#define BF(sb, eb) ((u32)(((s32)0x80000000) >> (sb - eb))) >> (31 - sb); + +union { + u32 all; + struct { + u32 res :28; + u32 Vbit:1; + u32 Zbit:1; + u32 Cbit:1; + u32 Nbit:1; + } bits; +} APSR; + +#define N (APSR.bits.Nbit) +#define Z (APSR.bits.Zbit) +#define C (APSR.bits.Cbit) +#define V (APSR.bits.Vbit) + +// FIXME: We're skipping the V bit for now. + +/* Leave C alone. */ +#define UPCC(res) \ +{ \ + if (S) { \ + N = (res) >> 31; \ + Z = (res == 0); \ +/* FIXME - possible problem with C bit - should be set to carry output from shifter */ \ + } \ +} + +#define ADC(dest, a, b, c) \ +{ \ + temp = (a) + (b) + (c); \ + if (S) { \ + N = temp >> 31; \ + Z = temp == 0; \ + C = (temp < (a)) || ((c) && (temp == (a))); \ + V = ((((s32)(temp)^(s32)(a)) < 0) && (((s32)(a)^(s32)(b)) >= 0)); \ + } \ + dest = temp; \ +} + +#define SBB(dest, a, b, c) \ +{ \ + temp = (a) - (b) - (!(c)); \ + if (S) { \ + N = temp >> 31; \ + Z = temp == 0; \ + C = !(((a) < temp) || ((!(c)) && ((a) == temp))); \ + V = ((((s32)temp^(s32)(a)) < 0) && (((s32)(a)^(s32)(b)) < 0)); \ + } \ + dest = temp; \ +} + +#define UNIMP(s) \ +{ \ + printf("UNIMPLEMENTED '%s' op %02x s %d bxtype %02x\n", s, OP, S, BXTYPE); \ + regdump(instruction, last_pc, 1); \ + return; \ +} + +#define EVAL_COND(cc) \ +{ \ + switch (cc) { \ + case 0x0: cond = (Z == 1); break; \ + case 0x1: cond = (Z == 0); break; \ + case 0x2: cond = (C == 1); break; \ + case 0x3: cond = (C == 0); break; \ + case 0x4: cond = (N == 1); break; \ + case 0x5: cond = (N == 0); break; \ + case 0x6: cond = (V == 1); break; \ + case 0x7: cond = (V == 0); break; \ + case 0x8: cond = (C == 1 && Z == 0); break; \ + case 0x9: cond = (C == 0 || Z == 1); break; \ + case 0xa: cond = (N == V); break; \ + case 0xb: cond = (N != V); break; \ + case 0xc: cond = (Z == 0 && N == V); break; \ + case 0xd: cond = (Z == 1 || N != V); break; \ + case 0xe: cond = (1); break; \ + case 0xf: cond = (0xf); break; \ + } \ +} + +u32 instruction; +u32 last_pc; + +void simhandler(int sig) +{ + extern void restoremode(); + + psignal(sig, "forth"); + regdump(instruction, last_pc, 1); + restoremode(); + exit(1); +} + + // alf = find(adr, len, link, origin); +u32 * +find(u8 *adr, u32 len, u32 *link, void *origin) +{ + u8 *wp, *np; + u32 namelen; + + while (link != origin) { + link -= 1; // Move from code field to link field + np = (u8 *)link - 1; + namelen = (*np) & 0x1f; + if (namelen == len) { + np -= namelen; + wp = adr; + while (namelen--) { + if (*np++ != *wp++) { + break; + } + } + if (namelen == -1) { + return (link); + } + } + link = (u32 *)*link; + } + return ((u32 *)0); +} + +void +simulate(u8 *mem, u32 start, u32 header, u32 syscall_vec, + u32 memtop, u32 argc, u32 argv) +{ + // register u32 instruction; + register u32 res; + register u32 cond; + register u32 temp; + u32 indent = 0; + u32 name; + u32 namelen; + // u32 last_pc; + + signal(SIGBUS, simhandler); + signal(SIGSEGV, simhandler); + + APSR.all = 0; + PC = start + 8; // Stupid ARM. + r[0] = header; + r[1] = 0; // Tell Forth it is using the simulator + r[2] = memtop; + r[3] = argc; + SP = memtop; + *((u32 *)SP) = argv; + + while (1) { + instruction = MEM(u32, PC - 8); + last_pc = PC; +//#if TRACE + if (trace) + regdump(instruction, last_pc, 0); +//#endif + EVAL_COND(COND); + if (cond == 0xf) + UNIMP("unconditional"); + switch (OP) { +case 0x00: if (OP1 == 0 || OP2 == 0) { + INSTR("and"); SHFT(res); RD = RN & res; UPCC(RD); break; + } + switch (BXTYPE) { + case 0x9: INSTR("mul"); RN = RS * RM; UPCC(RN); break; + // P=0, U=0, bit22=0, W=0 - post-index, add offset, register, no writeback + case 0xb: + if (L) { + INSTR("ldrh"); + RD = MEM(u16, RN); + RN = RN + RM; + } else { + INSTR("strh"); + MEM(u16, RN) = RD; + RN = RN + RM; + } + break; + case 0xd: + if (L) { + INSTR("ldrsb"); + RD = MEM(s8, RN); + RN = RN + RM; + } else { + UNIMP("ldrd"); + } + break; + case 0xf: if (L) { + INSTR("ldrsh"); + RD = MEM(s16, RN); + RN = RN + RM; + } else { + UNIMP("strd"); + } + break; + default: UNIMP("BXTYPE"); break; + } break; +case 0x01: if (OP1 == 0 || OP2 == 0) { + INSTR("eor"); SHFT(res); RD = RN ^ res; UPCC(RD); break; + } + switch (BXTYPE) { + case 0x9: UNIMP("mla"); break; + // P=0, U=0, bit22=0, W=1 - post-index, add offset, register, writeback - UNPREDICTABLE (P=0, W=1) + case 0xb: UNIMP("ldrh"); break; // UNPREDICTABLE + case 0xd: UNIMP("ldrd"); break; // UNPREDICTABLE + case 0xf: UNIMP("ldrsh"); break; // UNPREDICTABLE + } break; +case 0x02: if (OP1 == 0 || OP2 == 0) { + INSTR("sub"); SHFT(res); SBB(RD, RN, res, 1); break; + } + switch (BXTYPE) { + // P=0, U=0, bit22=1, W=0 - post-index, add offset, immediate, no writeback + case 0xb: + if (L) { + INSTR("ldrh"); + RD = MEM(u16, RN); + RN = RN + IMMHL; + } else { + INSTR("strh"); + MEM(u16, RN) = RD; + RN = RN + IMMHL; + } + break; + case 0xd: + if (L) { + INSTR("ldrsb"); + RD = MEM(s8, RN); + RN = RN + IMMHL; + } else { + UNIMP("ldrd"); + } + break; + case 0xf: if (L) { + INSTR("ldrsh"); + RD = MEM(s16, RN); + RN = RN + IMMHL; + } else { + UNIMP("strd"); + } + break; + default: UNIMP("BXTYPE"); break; + } break; +case 0x03: if (OP1 == 0 || OP2 == 0) { + INSTR("rsb"); SHFT(res); SBB(RD, res, RN, 1); break; + } else { + switch (BXTYPE) { + case 0x1: + case 0x3: + case 0x5: + case 0x7: INSTR("rsb"); SHFT(res); SBB(RD, res, RN, 1); break; + case 0x9: UNIMP("mls"); break; + // P=0, U=0, bit22=1, W=1 - post-index, add offset, immediate, writeback - UNPREDICTABLE (P=0, W=1) + case 0xb: UNIMP("ldrh"); break; // UNPREDICTABLE + case 0xd: UNIMP("ldrd"); break; // UNPREDICTABLE + case 0xf: UNIMP("ldrsh"); break; // UNPREDICTABLE + } break; + } break; +case 0x04: if (OP1 == 0 || OP2 == 0) { + INSTR("add"); SHFT(res); ADC(RD, RN, res, 0); break; + } + switch (BXTYPE) { + // P=0, U=1, bit22=0, W=0 - post-index, subtract offset, register, no writeback + case 0xb: + if (L) { + INSTR("ldrh"); + RD = MEM(u16, RN); + RN = RN - RM; + } else { + INSTR("strh"); + MEM(u16, RN) = RD; + RN = RN - RM; + } + break; + case 0xd: + if (L) { + INSTR("ldrsb"); + RD = MEM(s8, RN); + RN = RN - RM; + } else { + UNIMP("ldrd"); + } + break; + case 0xf: if (L) { + INSTR("ldrsh"); + RD = MEM(s16, RN); + RN = RN - RM; + } else { + UNIMP("strd"); + } + break; + default: UNIMP("BXTYPE"); break; + } break; +case 0x05: if (OP1 == 0 || OP2 == 0) { + INSTR("adc"); SHFT(res); ADC(RD, RN, res, C); break; + } + switch (BXTYPE) { + // P=0, U=1, bit22=0, W=1 - post-index, subtract offset, register, writeback - UNPREDICTABLE (P=0, W=1) + case 0xb: UNIMP("ldrh"); break; // UNPREDICTABLE + case 0xd: UNIMP("ldrd"); break; // UNPREDICTABLE + case 0xf: UNIMP("ldrsh"); break; // UNPREDICTABLE + default: UNIMP("BXTYPE"); break; + } break; +case 0x06: if (OP1 == 0 || OP2 == 0) { + INSTR("sbc"); SHFT(res); +// printf("sbc RN %x res %x ~res %x C %x -- ", RN, res, ~(res), C); +// ADC(RD, RN, ~(res), C); +// printf("res %x\n", RD); +// printf("sbc RN %x res %x ~res %x C %x -- ", RN, res, ~(res), C); + SBB(RD, RN, res, C); +// printf("res %x\n", RD); +break; + } else { + switch (BXTYPE) { + case 0x1: + case 0x3: + case 0x5: + case 0x7: INSTR("sbc"); SHFT(res); SBB(RD, res, RN, C); break; + case 0x9: UNIMP("smull"); break; + // P=0, U=1, bit22=1, W=0 - post-index, subtract offset, immediate, no writeback + case 0xb: + if (L) { + INSTR("ldrh"); + RD = MEM(u16, RN); + RN = RN - IMMHL; + } else { + INSTR("strh"); + MEM(u16, RN) = RD; + RN = RN - IMMHL; + } + break; + case 0xd: + if (L) { + INSTR("ldrsb"); + RD = MEM(s8, RN); + RN = RN - IMMHL; + } else { + UNIMP("ldrd"); + } + break; + case 0xf: if (L) { + INSTR("ldrsh"); + RD = MEM(s16, RN); + RN = RN - IMMHL; + } else { + UNIMP("strd"); + } + break; + default: UNIMP("BXTYPE"); break; + } break; + } break; +case 0x07: if (OP1 == 0 || OP2 == 0) { + INSTR("rsc"); SHFT(res); SBB(RD, res, RN, C); break; + } else { + switch (BXTYPE) { + case 0x1: + case 0x3: + case 0x5: + case 0x7: INSTR("rsc"); SHFT(res); SBB(RD, res, RN, C); break; + case 0x9: UNIMP("smlal"); break; + // P=0, U=1, bit22=1, W=1 - post-index, subtract offset, immediate, writeback - UNPREDICTABLE (P=0, W=1) + case 0xb: UNIMP("ldrh"); break; // UNPREDICTABLE + case 0xd: UNIMP("ldrd"); break; // UNPREDICTABLE + case 0xf: UNIMP("ldrsh"); break; // UNPREDICTABLE + default: UNIMP("BXTYPE"); break; + } break; + } break; +case 0x08: switch (BXTYPE) { + case 0x0: INSTR("mrs"); RD = APSR.all; break; + case 0x5: UNIMP("qadd"); break; + case 0x8: + case 0xa: + case 0xc: + case 0xe: UNIMP("smlabb"); break; + // P=1, U=0, bit22=0, W=0 - offset/pre-index, subtract offset, register, no writeback + case 0xb: + if (L) { + INSTR("ldrh"); + RD = MEM(u16, RN - RM); + } else { + INSTR("strh"); + MEM(u16, RN - RM) = RD; + } + break; + case 0xd: + if (L) { + INSTR("ldrsb"); + RD = MEM(s8, RN - RM); + } else { + UNIMP("ldrd"); + } + break; + case 0xf: if (L) { + INSTR("ldrsh"); + RD = MEM(s16, RN - RM); + } else { + UNIMP("strd"); + } + break; + default: UNIMP("BXTYPE"); break; + } break; +case 0x09: switch (BXTYPE) { + case 0x0: UNIMP("msr"); break; + case 0x1: INSTR("bx"); PC = RM; break; + case 0x2: INSTR("bxj"); PC = RM; break; + case 0x3: INSTR("blx"); if (LINK) LR = PC - 4; PC = RM; break; + case 0x5: UNIMP("qsub"); break; + case 0x7: UNIMP("bkpt"); break; + case 0x8: + case 0xa: + case 0xc: + case 0xe: UNIMP("smlawb"); break; + // P=1, U=0, bit22=0, W=1 - offset/pre-index, subtract offset, register, writeback + case 0xb: + if (L) { + INSTR("ldrh"); + temp = RN - RM; + RD = MEM(u16, temp); + RN = temp; + } else { + INSTR("strh"); + temp = RN - RM; + MEM(u16, temp) = RD; + RN = temp; + } + break; + case 0xd: + if (L) { + INSTR("ldrsb"); + temp = RN - RM; + RD = MEM(s8, temp); + RN = temp; + } else { + UNIMP("ldrd"); + } + break; + case 0xf: if (L) { + INSTR("ldrsh"); + temp = RN - RM; + RD = MEM(s16, temp); + RN = temp; + } else { + UNIMP("strd"); + } + break; + default: UNIMP("BXTYPE"); break; + } break; +case 0x0a: if (OP1 == 0 || OP2 == 0) { + INSTR("cmp"); SHFT(res); SBB(res, RN, res, 1); break; + } + switch (BXTYPE) { + case 0x5: UNIMP("qdadd"); break; + case 0x8: + case 0xa: + case 0xc: + case 0xe: UNIMP("smlalbb"); break; + // P=1, U=0, bit22=1, W=0 - offset/pre-index, subtract offset, immediate, no writeback + case 0xb: + if (L) { + INSTR("ldrh"); + RD = MEM(u16, RN - IMMHL); + } else { + INSTR("strh"); + MEM(u16, RN - IMMHL) = RD; + } + break; + case 0xd: + if (L) { + INSTR("ldrsb"); + RD = MEM(s8, RN - IMMHL); + } else { + UNIMP("ldrd"); + } + break; + case 0xf: if (L) { + INSTR("ldrsh"); + RD = MEM(s16, RN - IMMHL); + } else { + UNIMP("strd"); + } + break; + default: UNIMP("BXTYPE"); break; + } break; +case 0x0b: if (OP1 == 0 || OP2 == 0) { + if (S) { + INSTR("cmn"); SHFT(res); ADC(res, RN, res, 0); break; + } else { + // "You don't need this instruction anyway." + // --mjterave(a)gmail.com + UNIMP("clz"); break; + } + } + switch (BXTYPE) { + case 0x5: UNIMP("qdsub"); break; + case 0x8: + case 0xa: + case 0xc: + case 0xe: UNIMP("smulbb"); break; + // P=1, U=0, bit22=1, W=1 - offset/pre-index, subtract offset, immediate, writeback + case 0xb: + if (L) { + INSTR("ldrh"); + temp = RN - IMMHL; + RD = MEM(u16, temp); + RN = temp; + } else { + INSTR("strh"); + temp = RN - IMMHL; + MEM(u16, temp) = RD; + RN = temp; + } + break; + case 0xd: + if (L) { + INSTR("ldrsb"); + temp = RN - IMMHL; + RD = MEM(s8, temp); + RN = temp; + } else { + UNIMP("ldrd"); + } + break; + case 0xf: if (L) { + INSTR("ldrsh"); + temp = RN - IMMHL; + RD = MEM(s16, temp); + RN = temp; + } else { + UNIMP("strd"); + } + break; + default: UNIMP("BXTYPE"); break; + } break; +case 0x0c: if (OP1 == 0 || OP2 == 0) { + INSTR("orr"); SHFT(res); RD = RN | res; UPCC(res); break; + } else { + switch (BXTYPE) { + case 0x1: + case 0x3: + case 0x5: + case 0x7: INSTR("orr"); SHFT(res); RD = RN | res; UPCC(res); + break; + case 0x9: UNIMP("ldrex"); break; + // P=1, U=0, bit22=0, W=0 - offset/pre-index, subtract offset, register, no writeback + case 0xb: + if (L) { + INSTR("ldrh"); + RD = MEM(u16, RN + RM); + } else { + INSTR("strh"); + MEM(u16, RN + RM) = RD; + } + break; + case 0xd: + if (L) { + INSTR("ldrsb"); + RD = MEM(s8, RN + RM); + } else { + UNIMP("ldrd"); + } + break; + case 0xf: if (L) { + INSTR("ldrsh"); + RD = MEM(s16, RN + RM); + } else { + UNIMP("strd"); + } + break; + default: UNIMP("BXTYPE"); break; + } break; + } break; +case 0x0d: switch (BXTYPE) { + case 0x0: + if (instruction == 0xe1a00000) { + INSTR("nop"); break; + } else if (IMM5 == 0) { + if (instruction == 0xe1a0f009) { // mov pc,up i.e. the part of NEXT at the end of each code word + INSTR("NEXT"); + } else { + INSTR("mov"); + } + RD = RM; UPCC(RD); break; + } /* else fall through */ + case 0x8: + case 0x1: INSTR("lsl"); SHFT(RD); UPCC(RD); break; + case 0x2: + case 0xa: + case 0x3: INSTR("lsr"); SHFT(RD); UPCC(RD); break; + case 0x4: + case 0xc: + case 0x5: INSTR("asr"); SHFT(RD); UPCC(RD); break; + case 0x6: + case 0xe: + case 0x7: INSTR("ror"); SHFT(RD); UPCC(RD); break; + case 0x9: UNIMP("ldrexd"); break; + // P=1, U=1, bit22=0, W=1 - offset/pre-index, add offset, register, writeback + case 0xb: + if (L) { + INSTR("ldrh"); + temp = RN + RM; + RD = MEM(u16, temp); + RN = temp; + } else { + INSTR("strh"); + temp = RN + RM; + MEM(u16, temp) = RD; + RN = temp; + } + break; + case 0xd: + if (L) { + INSTR("ldrsb"); + temp = RN + RM; + RD = MEM(s8, temp); + RN = temp; + } else { + UNIMP("ldrd"); + } + break; + case 0xf: if (L) { + INSTR("ldrsh"); + temp = RN + RM; + RD = MEM(s16, temp); + RN = temp; + } else { + UNIMP("strd"); + } + break; + default: UNIMP("BXTYPE"); break; + }; break; +case 0x0e: if (OP1 == 0 || OP2 == 0) { + INSTR("bic"); SHFT(res); RD = RN & ~res; UPCC(RD); break; + } + switch (BXTYPE) { + case 0x9: UNIMP("ldrexb"); break; + // P=1, U=1, bit22=1, W=0 - offset/pre-index, add offset, immediate, no writeback + case 0xb: + if (L) { + INSTR("ldrh"); + RD = MEM(u16, RN + IMMHL); + } else { + INSTR("strh"); + MEM(u16, RN + IMMHL) = RD; + } + break; + case 0xd: + if (L) { + INSTR("ldrsb"); + RD = MEM(s8, RN + IMMHL); + } else { + UNIMP("ldrd"); + } + break; + case 0xf: if (L) { + INSTR("ldrsh"); + RD = MEM(s16, RN + IMMHL); + } else { + UNIMP("strd"); + } + break; + } break; +case 0x0f: if (OP1 == 0 || OP2 == 0) { + INSTR("mvn"); SHFT(res); RD = ~res; UPCC(RD); break; + } else { + switch (BXTYPE) { + case 0x9: UNIMP("ldrexh"); break; + // P=1, U=1, bit22=1, W=1 - offset/pre-index, add offset, immediate, writeback + case 0xb: + if (L) { + INSTR("ldrh"); + temp = RN + IMMHL; + RD = MEM(u16, temp); + RN = temp; + } else { + INSTR("strh"); + temp = RN + IMMHL; + MEM(u16, temp) = RD; + RN = temp; + } + break; + case 0xd: + if (L) { + INSTR("ldrsb"); + temp = RN + IMMHL; + RD = MEM(s8, temp); + RN = temp; + } else { + UNIMP("ldrd"); + } + break; + case 0xf: if (L) { + INSTR("ldrsh"); + temp = RN + IMMHL; + RD = MEM(s16, temp); + RN = temp; + } else { + UNIMP("strd"); + } + break; + default: UNIMP("BXTYPE"); break; + } break; + } break; +case 0x10: INSTR("and"); RD = RN & IMM32; UPCC(RD); break; +case 0x11: INSTR("eor"); RD = RN ^ IMM32; UPCC(RD); break; +case 0x12: INSTR("sub"); SBB(RD, RN, IMM32, 1); break; +case 0x13: INSTR("rsb"); SBB(RD, IMM32, RN, 1); break; +case 0x14: /* if (instruction == 0xe2809020) trace = 0; */ + INSTR("add"); ADC(RD, RN, IMM32, 0); break; +case 0x15: INSTR("adc"); ADC(RD, RN, IMM32, C); break; +case 0x16: INSTR("sbc"); SBB(RD, IMM32, RN, C); break; +case 0x17: INSTR("rsc"); SBB(RD, IMM32, RN, C); break; +case 0x18: INSTR("mov"); RD = IMM16; break; +case 0x19: switch (BXTYPE) { + case 0x0: INSTR("nop"); break; + case 0x1: + INSTR("wrc"); + if (RN == -2) { + printf("Tracing on\n"); + trace = 1; + } else if (RN == -1) { +// trace = 1; +// printf("find %x %x %x %x\n",r[2], r[1], r[0], r[3]); + // alf = find(u8 *adr, u32 len, u32 *link, void *origin); + r[0] = (u32)find((u8 *)r[2], r[1], (u32 *)r[0], (u8 *)r[3]); +// printf("returns %x\n", r[0]); + } else { + /* Handle Forth wrapper calls - the call# is in RN */ + r[0] = (*(long (*) ())(*(long *)(syscall_vec + RN))) + (r[0],r[1],r[2],r[3],r[4],r[5]); + } + break; + + case 0xf: UNIMP("dbg"); break; + default: UNIMP("msr"); break; + } break; +case 0x1a: if (S) { + INSTR("cmp"); SBB(res, RN, IMM32, 1); break; + } else { + INSTR("movt"); RD = (IMM16 << 16) | (RD & 0xffff); break; + } +case 0x1b: INSTR("cmn"); ADC(res, RN, IMM32, 0); break; +case 0x1c: INSTR("orr"); RD = RN | IMM32; UPCC(RD); break; +case 0x1d: INSTR("mov"); RD = IMM32; UPCC(RD); break; +case 0x1e: INSTR("bic"); RD = RN & (~IMM32); UPCC(RD); break; +case 0x1f: INSTR("mvn"); RD = ~IMM32; UPCC(RD); break; +case 0x20: +case 0x21: if (L) { + INSTR("ldr"); RD = MEM(u32, RN); RN -= IMM12; + } else { + INSTR("str"); MEM(u32, RN) = RD; RN -= IMM12; + } break; +case 0x22: +case 0x23: if (L) { + INSTR("ldrb"); RD = MEM(u8, RN); RN -= IMM12; + } else { + INSTR("strb"); MEM(u8, RN) = RD; RN -= IMM12; + } break; +case 0x24: if (L) { + if (UFIELD(19, 4) == 0xd) { + INSTR("pop"); RD = MEM(u32, RN); RN += IMM12; + } else { + if (instruction == 0xe49cf004) { // ldr pc,[ip],#4 i.e. the guts of NEXT + INSTR("DONEXT"); + } else if (instruction == 0xe49ca004) { // ldr tos,[ip],#4 i.e. the guts of (lit) and (') + INSTR("DOLIT"); + } else { + if (instruction == 0xe49bc004) { indent--; if (indent < 0) indent = 0; } + INSTR("ldr"); + } + RD = MEM(u32, RN); RN += IMM12; + if (trace) { + // If NEXT or ('), show the name of the word + if ((instruction == 0xe49cf004) || (instruction == 0xe49ca004)) { + name = RD - 5; + // If name is not in the dictionary area, it is probably a numeric literal + if (name >= r[9] && ((name - r[9]) < 0x100000)) { + namelen = *(char *)name & 0x3f; + name = name - namelen; + // Indent with * for EMACS outline mode - handy for hiding subordinate calls +// for (temp = 0; temp < indent; temp++) +// putchar('*'); + while (namelen--) + putchar(*(char *)name++); + printf(" Stack: %x %x %x %x indent %x\n" , + ((u32 *)r[13])[2], ((u32 *)r[13])[1], ((u32 *)r[13])[0], r[10], indent); + } + } + } + } + } else { + INSTR("str"); MEM(u32, RN) = RD; RN += IMM12; + } break; +case 0x25: if (L) { + INSTR("ldr"); RD = MEM(u32, RN); RN += IMM12; + } else { + INSTR("str"); MEM(u32, RN) = RD; RN += IMM12; + } break; +case 0x26: +case 0x27: if (L) { + INSTR("ldrb"); RD = MEM(u8, RN); RN += IMM12; + } else { + INSTR("strb"); MEM(u8, RN) = RD; RN += IMM12; + } break; +case 0x28: if (L) { + INSTR("ldr"); RD = MEM(u32, RN - IMM12); break; + } else { + INSTR("str"); MEM(u32, RN - IMM12) = RD; break; + } break; +case 0x29: if (L) { + INSTR("ldr"); RN -= IMM12; RD = MEM(u32, RN); break; + } else { + if (instruction == 0xe52bc004) indent++; // DOCOLON + INSTR("str"); RN -= IMM12; MEM(u32, RN) = RD; + break; + } break; +case 0x2a: if (L) { + INSTR("ldrb"); RD = MEM(u8, RN - IMM12); break; + } else { + INSTR("strb"); MEM(u8, RN - IMM12) = RD; break; + } break; +case 0x2b: if (L) { + INSTR("ldrb"); RN -= IMM12; RD = MEM(u8, RN); break; + } else { + INSTR("strb"); RN -= IMM12; MEM(u8, RN) = RD; break; + } break; +case 0x2c: if (L) { + INSTR("ldr"); RD = MEM(u32, RN + IMM12); break; + } else { + INSTR("str"); MEM(u32, RN + IMM12) = RD; break; + } break; +case 0x2d: if (L) { + INSTR("ldr"); RN += IMM12; RD = MEM(u32, RN); break; + } else { + INSTR("str"); RN += IMM12; MEM(u32, RN) = RD; break; + } break; +case 0x2e: if (L) { + INSTR("ldrb"); RD = MEM(u8, RN + IMM12); break; + } else { + INSTR("strb"); MEM(u8, RN + IMM12) = RD; break; + } break; +case 0x2f: if (L) { + INSTR("ldrb"); RN += IMM12; RD = MEM(u8, RN); break; + } else { + INSTR("strb"); RN += IMM12; MEM(u8, RN) = RD; break; + } break; +case 0x30: +case 0x31: if (OP1) { + UNIMP("mcr"); break; + } else if (L) { + INSTR("ldr"); SHFT(res); RD = MEM(u32, RN); RN -= res; break; + } else { + INSTR("str"); SHFT(res); MEM(u32, RN) = RD; RN -= res; break; + } break; +case 0x32: +case 0x33: if (OP1) { + UNIMP("mcr"); break; + } else if (L) { + INSTR("ldrb"); SHFT(res); RD = MEM(u8, RN); RN -= res; break; + } else { + INSTR("strb"); SHFT(res); MEM(u8, RN) = RD; RN -= res; break; + } break; +case 0x34: +case 0x35: if (OP1) { + UNIMP("mcr"); break; + } else if (L) { + INSTR("ldr"); SHFT(res); RD = MEM(u32, RN); RN += res; break; + } else { + INSTR("str"); SHFT(res); MEM(u32, RN) = RD; RN += res; break; + } break; +case 0x36: +case 0x37: if (OP1) { + UNIMP("mcr"); break; + } else if (L) { + INSTR("ldrb"); SHFT(res); RD = MEM(u8, RN); RN += res; break; + } else { + INSTR("strb"); SHFT(res); MEM(u8, RN) = RD; RN += res; break; + } break; +case 0x38: if (OP1) { + UNIMP("smlad"); break; + } else if (L) { + INSTR("ldr"); SHFT(res); RD = MEM(u32, RN - res); break; + } else { + INSTR("str"); SHFT(res); MEM(u32, RN - res) = RD; break; + } break; +case 0x39: if (L) { + INSTR("ldr"); SHFT(res); RN -= res; RD = MEM(u32, RN); break; + } else { + INSTR("str"); SHFT(res); RN -= res; MEM(u32, RN) = RD; break; + } break; +case 0x3a: if (OP1) { + UNIMP("smlald"); break; + } else if (L) { + INSTR("ldrb"); SHFT(res); RD = MEM(u8, RN - res); break; + } else { + INSTR("strb"); SHFT(res); MEM(u8, RN - res) = RD; break; + } break; +case 0x3b: if (L) { + INSTR("ldrb"); SHFT(res); RN -= res; RD = MEM(u8, RN); break; + } else { + INSTR("strb"); SHFT(res); RN -= res; MEM(u8, RN) = RD; break; + } +case 0x3c: if (L) { + INSTR("ldr"); SHFT(res); RD = MEM(u32, RN + res); break; + } else { + INSTR("str"); SHFT(res); MEM(u32, RN + res) = RD; break; + } +case 0x3d: if (OP1) { + UNIMP("sbfx"); break; + } else if (L) { + INSTR("ldr"); SHFT(res); RN += res; RD = MEM(u32, RN); break; + } else { + INSTR("str"); SHFT(res); RN += res; MEM(u32, RN) = RD; break; + } break; +case 0x3e: if (OP1) { + if (UFIELD(3, 4) == 0xf) { + INSTR("bfc"); RD &= ~BF(MSB, LSB); + } else { + INSTR("bfi"); + RD &= ~BF(MSB, LSB); + RD |= RN & ~BF(MSB, LSB); + } + } else if (L) { + INSTR("ldrb"); SHFT(res); RD = MEM(u8, RN + res); + } else { + INSTR("strb"); SHFT(res); MEM(u8, RN + res) = RD; + } break; +case 0x3f: if (L) { + INSTR("ldrb"); SHFT(res); RN += res; RD = MEM(u8, RN); break; + } else { + INSTR("strb"); SHFT(res); RN += res; MEM(u8, RN) = RD; break; + } break; +case 0x40: +case 0x41: { u32 base = RN; + u32 reglist = UFIELD(15, 16); + s32 reg; + if (L) { + INSTR("ldmda"); + } else { + INSTR("stmda"); + } + for (reg = 15; reg >= 0; reg--) { + if ((1 << reg) & reglist) { + if (L) { + r[reg] = MEM(u32, base); + } else { + MEM(u32, base) = r[reg]; + } + base -= 4; + } + } + if (W) RN = base; + } break; +case 0x42: UNIMP("xxx"); +case 0x43: UNIMP("xxx"); +case 0x44: +case 0x45: { u32 base = RN; + u32 reglist = UFIELD(15, 16); + s32 reg; + if (L) { + INSTR("ldm"); + } else { + INSTR("stm"); + } + for (reg = 0; reg < 16; reg++) { + if ((1 << reg) & reglist) { + if (L) { + r[reg] = MEM(u32, base); + } else { + MEM(u32, base) = r[reg]; + } + base += 4; + } + } + if (W) RN = base; + } break; +case 0x46: UNIMP("xxx"); +case 0x47: UNIMP("xxx"); +case 0x48: +case 0x49: { u32 base = RN; + u32 reglist = UFIELD(15, 16); + s32 reg; + if (L) { + INSTR("ldmdb"); + } else { + INSTR("stmdb"); + } + for (reg = 15; reg >= 0; reg--) { + if ((1 << reg) & reglist) { + base -= 4; + if (L) { + r[reg] = MEM(u32, base); + } else { + MEM(u32, base) = r[reg]; + } + } + } + if (W) RN = base; + } break; +case 0x4a: UNIMP("xxx"); break; +case 0x4b: UNIMP("xxx"); break; +case 0x4c: +case 0x4d: { u32 base = RN + 4; + u32 reglist = UFIELD(15, 16); + s32 reg; + if (L) { + INSTR("ldmib"); + } else { + INSTR("stmib"); + } + for (reg = 0; reg < 16; reg++) { + if ((1 << reg) & reglist) { + if (L) { + r[reg] = MEM(u32, base); + } else { + MEM(u32, base) = r[reg]; + } + base += 4; + } + } + if (W) RN = base; + } break; +case 0x4e: UNIMP("xxx"); break; +case 0x4f: UNIMP("xxx"); break; +case 0x50: +case 0x51: +case 0x52: +case 0x53: +case 0x54: +case 0x55: +case 0x56: +case 0x57: INSTR("b"); BTGT; break; +case 0x58: +case 0x59: +case 0x5a: +case 0x5b: +case 0x5c: +case 0x5d: +case 0x5e: +case 0x5f: INSTR("bl"); LR = PC - 4; BTGT; break; +case 0x60: +case 0x61: UNIMP("stc"); break; +case 0x62: UNIMP("mcrr"); break; +case 0x63: +case 0x64: +case 0x65: +case 0x66: +case 0x67: +case 0x68: +case 0x69: +case 0x6a: +case 0x6b: +case 0x6c: +case 0x6d: +case 0x6e: UNIMP("stc"); break; +case 0x6f: UNIMP("ldc"); break; +case 0x70: +case 0x71: +case 0x72: +case 0x73: +case 0x74: +case 0x75: +case 0x76: +case 0x77: UNIMP("cdp"); break; +case 0x78: +case 0x79: +case 0x7a: +case 0x7b: +case 0x7c: +case 0x7d: +case 0x7e: +case 0x7f: UNIMP("svc"); break; + } // switch (OP) + if (PC == last_pc) + PC += 4; + else // branch or move + PC += 8; + } // while (1) +} + +// LICENSE_BEGIN +// Copyright (c) 2007 FirmWorks +// Copyright 2010 Apple, Inc. All rights reserved. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be +// included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +// LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +// OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +// WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// +// LICENSE_END

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[commit] r2115 - cpu/x86/Linux
by repository service 18 Jan '11

18 Jan '11

Author: wmb Date: Tue Jan 18 21:37:18 2011 New Revision: 2115 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2115 Log: ARM - moving things around in the ARM cross-build arena, working toward seamless builds using the ARM simulator wrapper. Added: cpu/x86/Linux/Makefile.armforth - copied unchanged from r2097, cpu/x86/Linux/Makefile.armsim cpu/x86/Linux/armforth.qemu - copied unchanged from r2109, cpu/x86/Linux/armforth Deleted: cpu/x86/Linux/Makefile.armsim cpu/x86/Linux/armforth Copied: cpu/x86/Linux/Makefile.armforth (from r2097, cpu/x86/Linux/Makefile.armsim) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/x86/Linux/Makefile.armforth Tue Jan 18 21:37:18 2011 (r2115, copy of r2097, cpu/x86/Linux/Makefile.armsim) @@ -0,0 +1,56 @@ +# Wrapper makefile for x86 Mac OS X / Darwin + +BP=../../.. + +# Flags for the simulator version +OPT = -O +CFLAGS = -g -m32 -DARMSIM -DTARGET_ARM -DARM + +WRTAIL = forth/wrapper +WRDIR = ${BP}/${WRTAIL} +ZIPTAIL = ${WRTAIL}/zip +ZIPDIR = ${BP}/${ZIPTAIL} +ARMDIR = ${BP}/cpu/arm + +ZIPOBJS = zipmem.o deflate.o trees.o bits.o util.o inflate.o + +OBJS = wrapsim.o armsim.o logger.o ${ZIPOBJS} +TRACEOBJS = wrapsim.o armsim.trace.o logger.o ${ZIPOBJS} +SIMROMOBJS = simrom.o armsim.simrom.o + +all: armforth armforth.trace + +armforth: $(OBJS) + $(CC) $(LFLAGS) $(OBJS) -o $@ + +armforth.trace: $(TRACEOBJS) + $(CC) $(LFLAGS) $(TRACEOBJS) -o $@ + +simrom: $(SIMROMOBJS) + $(CC) $(LFLAGS) $(SIMROMOBJS) -o $@ + +wrapsim.o: ${WRDIR}/wrapper.c + ${CC} -c ${CFLAGS} $< -o $@ + +%.o: ${WRDIR}/%.c + ${CC} -c ${CFLAGS} $< -o $@ + +%.o: ${ZIPDIR}/%.c + ${CC} -c ${CFLAGS} -I${ZIPDIR} $< -o $@ + +armsim.o: $(ARMDIR)/armsim.c + $(CC) $(OPT) $(CFLAGS) -DARGREGS -DSIMNEXT -c $< -o $@ + +armsim.trace.o: $(ARMDIR)/armsim.c + $(CC) $(OPT) $(CFLAGS) -DARGREGS -DSIMNEXT -DTRACE=1 -c $< -o $@ + +armsim.simrom.o: $(ARMDIR)/armsim.c + $(CC) $(CFLAGS) -DARGREGS -DSIMNEXT -DTRACE=1 -DSIMROM -c $< -o $@ + +simrom.o: $(ARMDIR)/simrom.c + $(CC) $(CFLAGS) -DARGREGS -DSIMNEXT -DTRACE=1 -DSIMROM -c $< -o $@ + +clean: + @rm -f *.o armforth armforth.trace + +FRC: Copied: cpu/x86/Linux/armforth.qemu (from r2109, cpu/x86/Linux/armforth) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/x86/Linux/armforth.qemu Tue Jan 18 21:37:18 2011 (r2115, copy of r2109, cpu/x86/Linux/armforth) @@ -0,0 +1,11 @@ +#!/bin/sh + +# The "-0 $0" below causes the wrapper to skip arguments +# before the -0, so the program name appears to be the +# name of this script ($0). That makes the logger put the +# this script name in the "command: " line, instead of +# putting cpu/arm/Linux/armforth.static, which is not +# directly executable in the cross environment, there. +# That makes fast-rebuilds from the .log file work right. + +qemu-arm ${BP}/cpu/arm/Linux/armforth.static -0 $0 $*

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[commit] r2114 - dev/ide
by repository service 18 Jan '11

18 Jan '11

Author: wmb Date: Tue Jan 18 21:33:01 2011 New Revision: 2114 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2114 Log: IDE driver - added a delay in the probe loop, helpful for some devices. Modified: dev/ide/generic.fth Modified: dev/ide/generic.fth ============================================================================== --- dev/ide/generic.fth Tue Jan 18 21:28:04 2011 (r2113) +++ dev/ide/generic.fth Tue Jan 18 21:33:01 2011 (r2114) @@ -393,6 +393,7 @@ first-open? if max#drives 0 do + d# 80 ms 0 i set-address get-drive-parms if set-drive-cfg then loop false to first-open? then

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[commit] r2113 - cpu/arm/olpc/1.75
by repository service 18 Jan '11

18 Jan '11

Author: wmb Date: Tue Jan 18 21:28:04 2011 New Revision: 2113 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2113 Log: OLPC XO-1.75 A2 pin muxing - use high pin drive with no internal pullups for SD and eMMC. Modified: cpu/arm/olpc/1.75/emmc.fth Modified: cpu/arm/olpc/1.75/emmc.fth ============================================================================== --- cpu/arm/olpc/1.75/emmc.fth Tue Jan 18 21:25:30 2011 (r2112) +++ cpu/arm/olpc/1.75/emmc.fth Tue Jan 18 21:28:04 2011 (r2113) @@ -1,12 +1,12 @@ \ XXX do we need to set the internal SD for fast drive in boardgpio.fth ? : select-internal-sd ( -- ) ." Using internal SD" cr - h# d8c3 d# 113 af! \ SD_CMD - h# d8c3 d# 126 af! \ SD_DATA2 - h# d8c3 d# 127 af! \ SD_DATA0 - h# d8c3 d# 130 af! \ SD_DATA3 - h# d8c3 d# 135 af! \ SD_DATA1 - h# d8c3 d# 138 af! \ SD_CLK + h# 18c3 d# 113 af! \ SD_CMD + h# 18c3 d# 126 af! \ SD_DATA2 + h# 18c3 d# 127 af! \ SD_DATA0 + h# 18c3 d# 130 af! \ SD_DATA3 + h# 18c3 d# 135 af! \ SD_DATA1 + h# 18c3 d# 138 af! \ SD_CLK h# c1 d# 111 af! \ eMMC_D0 as GPIO h# c1 d# 112 af! \ eMMC_CMD as GPIO h# c1 d# 151 af! \ eMMC_CLK as GPIO @@ -28,16 +28,16 @@ h# c0 d# 138 af! \ SD_CLK as GPIO \ XXX perhaps 18c2 for fast? - h# c2 d# 111 af! \ eMMC_D0 - h# c2 d# 112 af! \ eMMC_CMD - h# c2 d# 151 af! \ eMMC_CLK - h# c2 d# 162 af! \ eMMC_D6 - h# c2 d# 163 af! \ eMMC_D4 - h# c2 d# 164 af! \ eMMC_D2 - h# c2 d# 165 af! \ eMMC_D7 - h# c2 d# 166 af! \ eMMC_D5 - h# c2 d# 167 af! \ eMMC_D3 - h# c2 d# 168 af! \ eMMC_D1 + h# 18c2 d# 111 af! \ eMMC_D0 + h# 18c2 d# 112 af! \ eMMC_CMD + h# 18c2 d# 151 af! \ eMMC_CLK + h# 18c2 d# 162 af! \ eMMC_D6 + h# 18c2 d# 163 af! \ eMMC_D4 + h# 18c2 d# 164 af! \ eMMC_D2 + h# 18c2 d# 165 af! \ eMMC_D7 + h# 18c2 d# 166 af! \ eMMC_D5 + h# 18c2 d# 167 af! \ eMMC_D3 + h# 18c2 d# 168 af! \ eMMC_D1 d# 149 gpio-set \ Release eMMC_RST#

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[commit] r2112 - cpu/arm cpu/mips cpu/ppc cpu/x86 forth/kernel forth/lib
by repository service 18 Jan '11

18 Jan '11

Author: wmb Date: Tue Jan 18 21:25:30 2011 New Revision: 2112 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2112 Log: Kernel - fixed a longstanding inefficiency in the code that handles "is" / "to" for basic datatypes like value and defer. "to <value>" is now much faster, comparable in speed to "<variable> @". Modified: cpu/arm/kerncode.fth cpu/arm/kernel.bth cpu/mips/kerncode.fth cpu/ppc/kerncode.fth cpu/x86/kerncode.fth forth/kernel/kernel.fth forth/lib/decomp.fth Modified: cpu/arm/kerncode.fth ============================================================================== --- cpu/arm/kerncode.fth Mon Jan 17 22:58:06 2011 (r2111) +++ cpu/arm/kerncode.fth Tue Jan 18 21:25:30 2011 (r2112) @@ -133,6 +133,35 @@ meta definitions +code isdefer ( xt -- ) + ldr r0,[ip],1cell \ Get CFA of target word + ldr r0,[r0,1cell] \ Get user number + str tos,[r0,up] \ Store value + pop tos,sp \ Fix stack +c; +code isvalue ( n -- ) + ldr r0,[ip],1cell \ Get CFA of target word + ldr r0,[r0,1cell] \ Get user number + str tos,[r0,up] \ Store value + pop tos,sp \ Fix stack +c; +code isuser ( n -- ) + ldr r0,[ip],1cell \ Get CFA of target word + ldr r0,[r0,1cell] \ Get user number + str tos,[r0,up] \ Store value + pop tos,sp \ Fix stack +c; +code isconstant ( n -- ) + ldr r0,[ip],1cell \ Get CFA of target word + str tos,[r0,1cell] \ Store value + pop tos,sp \ Fix stack +c; +code isvariable ( n -- ) + ldr r0,[ip],1cell \ Get CFA of target word + str tos,[r0,1cell] \ Store value + pop tos,sp \ Fix stack +c; + code (lit) ( -- lit ) psh tos,sp ldr tos,[ip],1cell Modified: cpu/arm/kernel.bth ============================================================================== --- cpu/arm/kernel.bth Mon Jan 17 22:58:06 2011 (r2111) +++ cpu/arm/kernel.bth Tue Jan 18 21:25:30 2011 (r2112) @@ -31,7 +31,6 @@ [ifndef] arm-assembler \ Make sure we have the ARM assembler -order cr only forth also definitions fload ${BP}/forth/lib/bitops.fth Modified: cpu/mips/kerncode.fth ============================================================================== --- cpu/mips/kerncode.fth Mon Jan 17 22:58:06 2011 (r2111) +++ cpu/mips/kerncode.fth Tue Jan 18 21:25:30 2011 (r2112) @@ -207,6 +207,53 @@ meta definitions +code isdefer ( xt -- ) + ip t0 get + ip ainc + + t0 4 t0 lw \ Get user number + t0 up t0 addu \ User area address + tos base tos subu \ relocate xt + tos t0 0 sw \ Store value + sp ainc \ finish popping stack +c; + +code isuser ( xt -- ) + ip t0 get + ip ainc + + t0 4 t0 lw \ Get user number + t0 up t0 addu \ User area address + tos t0 0 sw \ Store value + sp ainc \ finish popping stack +c; + +code isvalue ( xt -- ) + ip t0 get + ip ainc + + t0 4 t0 lw \ Get user number + t0 up t0 addu \ User area address + tos t0 0 sw \ Store value + sp ainc \ finish popping stack +c; + +code isconstant ( xt -- ) + ip t0 get + ip ainc + + tos t0 4 sw \ Store value + sp ainc \ finish popping stack +c; + +code isvariable ( xt -- ) + ip t0 get + ip ainc + + tos t0 4 sw \ Store value + sp ainc \ finish popping stack +c; + \ dovariable constant dovariable \ dodoes constant dodoes Modified: cpu/ppc/kerncode.fth ============================================================================== --- cpu/ppc/kerncode.fth Mon Jan 17 22:58:06 2011 (r2111) +++ cpu/ppc/kerncode.fth Tue Jan 18 21:25:30 2011 (r2112) @@ -190,6 +190,39 @@ meta definitions +code isdefer ( xt -- ) + literal-to-t0 + lwz t0,/cf(t0) \ User number in t0 + stwx tos,t0,up + pop-tos +c; + +code isvalue ( n -- ) + literal-to-t0 + lwz t0,/cf(t0) \ User number in t0 + stwx tos,t0,up + pop-tos +c; + +code isuser ( n -- ) + literal-to-t0 + lwz t0,/cf(t0) \ User number in t0 + stwx tos,t0,up + pop-tos +c; + +code isconstant ( n -- ) + literal-to-t0 + stw tos,/cf(t0) + pop-tos +c; + +code isvariable ( n -- ) + literal-to-t0 + stw tos,/cf(t0) + pop-tos +c; + \ dovariable constant dovariable \ dodoes constant dodoes Modified: cpu/x86/kerncode.fth ============================================================================== --- cpu/x86/kerncode.fth Mon Jan 17 22:58:06 2011 (r2111) +++ cpu/x86/kerncode.fth Tue Jan 18 21:25:30 2011 (r2112) @@ -161,6 +161,39 @@ \ ---- Run-time words compiled by compiling words. +code isdefer ( xt -- ) + 0 [ip] ax mov ip ainc /cf [ax] ax mov ?bswap-ax up ax add \ data address in ax +[ifdef] big-endian-t + ax bx mov ax pop ?bswap-ax ax 0 [bx] mov +[else] + bx pop bx 0 [ax] mov +[then] +c; +code isvalue ( n -- ) + 0 [ip] ax mov ip ainc /cf [ax] ax mov ?bswap-ax up ax add \ data address in ax +[ifdef] big-endian-t + ax bx mov ax pop ?bswap-ax ax 0 [bx] mov +[else] + bx pop bx 0 [ax] mov +[then] +c; +code isuser ( n -- ) + 0 [ip] ax mov ip ainc /cf [ax] ax mov ?bswap-ax up ax add \ data address in ax +[ifdef] big-endian-t + ax bx mov ax pop ?bswap-ax ax 0 [bx] mov +[else] + bx pop bx 0 [ax] mov +[then] +c; +code isconstant ( n -- ) + 0 [ip] bx mov ip ainc + ax pop ?bswap-ax ax /cf [bx] mov +c; +code isvariable ( n -- ) + 0 [ip] bx mov ip ainc + ax pop ?bswap-ax ax /cf [bx] mov +c; + code bswap (s n1 -- n2 ) ax pop Modified: forth/kernel/kernel.fth ============================================================================== --- forth/kernel/kernel.fth Mon Jan 17 22:58:06 2011 (r2111) +++ forth/kernel/kernel.fth Tue Jan 18 21:25:30 2011 (r2112) @@ -1912,6 +1912,13 @@ ' ! token,-t \ constant ' ! token,-t \ variable +create is-ops + ' isdefer token,-t \ defer + ' isuser token,-t \ user variable + ' isvalue token,-t \ value + ' isconstant token,-t \ constant + ' isvariable token,-t \ variable + : associate ( acf -- true | index false ) word-type ( n ) word-types begin ( n adr ) @@ -1957,11 +1964,17 @@ [ifndef] run-time : do-is ( data acf -- ) - dup kerntype? if ( [data] acf ) - state @ if compile (is) token, else (is then - else ( [data] acf ) + dup associate if ( [data] acf ) to-hook - then + else ( [data] acf index ) + state @ if ( acf index ) + is-ops swap ta+ token@ ( acf is-token ) + token, token, ( ) + else ( data acf index ) + tuck data-locs +execute ( data index data-adr ) + swap !ops +execute ( ) + then ( ) + then ( ) ; \ is is the word that is actually used by applications : is \ name ( data -- ) Modified: forth/lib/decomp.fth ============================================================================== --- forth/lib/decomp.fth Mon Jan 17 22:58:06 2011 (r2111) +++ forth/lib/decomp.fth Tue Jan 18 21:25:30 2011 (r2112) @@ -300,7 +300,7 @@ headers : skip-(') ( ip -- ip' ) ta1+ ta1+ ; headerless -: .is ( ip -- ip' ) .cword dup token@ .name ta1+ ; +: .is ( ip -- ip' ) ." to " ta1+ dup token@ .name ta1+ ; : .string-tail ( ip -- ip' ) dup count type +str ; : .string ( ip -- ip' ) .cword .string-tail put" ; : .pstring ( ip -- ip' ) ?cr ." p" put" ta1+ .string-tail put" ; @@ -322,7 +322,7 @@ \ classify each word in a definition \ Common constant for sizing the three classes: -d# 30 constant #decomp-classes +d# 36 constant #decomp-classes #decomp-classes tassociative: execution-class ( token -- index ) ( 0 ) [compile] (lit) ( 1 ) [compile] ?branch @@ -337,9 +337,12 @@ ( 18 ) [compile] (endof) ( 19 ) [compile] (endcase) ( 20 ) [compile] ("s) ( 21 ) [compile] (is) ( 22 ) [compile] (dlit) ( 23 ) [compile] (llit) - ( 24 ) [compile] (n") ( 25 ) [compile] dummy - ( 26 ) [compile] dummy ( 27 ) [compile] dummy - ( 28 ) [compile] dummy ( 29 ) [compile] dummy + ( 24 ) [compile] (n") ( 25 ) [compile] isdefer + ( 26 ) [compile] isuser ( 27 ) [compile] isvalue + ( 28 ) [compile] isconstant ( 29 ) [compile] isvariable + ( 30 ) [compile] dummy ( 31 ) [compile] dummy + ( 32 ) [compile] dummy ( 33 ) [compile] dummy + ( 34 ) [compile] dummy ( 35 ) [compile] dummy \ Print a word which has been classified by execution-class #decomp-classes 1+ case: .execution-class ( ip index -- ip' ) @@ -355,9 +358,12 @@ ( 18 ) .endof ( 19 ) .endcase ( 20 ) .pstring ( 21 ) .is ( 22 ) .dlit ( 23 ) .llit - ( 24 ) .nstring ( 25 ) dummy - ( 26 ) dummy ( 27 ) dummy - ( 28 ) dummy ( 29 ) dummy + ( 24 ) .nstring ( 25 ) .is + ( 26 ) .is ( 27 ) .is + ( 28 ) .is ( 29 ) .is + ( 30 ) dummy ( 31 ) dummy + ( 32 ) dummy ( 32 ) dummy + ( 34 ) dummy ( 35 ) dummy ( default ) .word ; @@ -376,9 +382,12 @@ ( 18 ) skip-branch ( 19 ) skip-word ( 20 ) skip-string ( 21 ) skip-word ( 22 ) skip-dlit ( 23 ) skip-llit - ( 24 ) skip-nstring ( 25 ) dummy - ( 26 ) dummy ( 27 ) dummy - ( 28 ) dummy ( 29 ) dummy + ( 24 ) skip-nstring ( 25 ) skip-word + ( 26 ) skip-word ( 27 ) skip-word + ( 28 ) skip-word ( 29 ) skip-word + ( 30 ) dummy ( 31 ) dummy + ( 32 ) dummy ( 32 ) dummy + ( 34 ) dummy ( 35 ) dummy ( default ) skip-word ;

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[commit] r2111 - dev/olpc/viacamera
by repository service 17 Jan '11

17 Jan '11

Author: wmb Date: Mon Jan 17 22:58:06 2011 New Revision: 2111 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2111 Log: Initial revision of color space converstion code. Added: dev/olpc/viacamera/ycrcbtorgb.fth Added: dev/olpc/viacamera/ycrcbtorgb.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ dev/olpc/viacamera/ycrcbtorgb.fth Mon Jan 17 22:58:06 2011 (r2111) @@ -0,0 +1,141 @@ +\ See license at end of file +purpose: Color space conversion from YCbCr to RGB + +\ R = clip (Y + 1.402 * Cr) +\ G = clip (Y - 0.344 * Cb - 0.714 * Cr) +\ B = clip (Y + 1.772 * Cb) + +\ This is for full-range YCbCr, where the Y anc Cb/Cr values ranges from 0-255. +\ For restricted-range YCbCr (16 <= Y <= 235, 16 <= Cr,Cb <= 240), the Y value +\ would need to be adjusted to Ysc = (Y - 16) * 1.164 (1.164 = 298 / 256 = 149 / 128) +\ and the multipliers change from (1.402, -0.343, -0.711, 1.765) to (1.596, -0.392, -0.813, 2.017) + +code ycrcb444>rgb888 ( y cr cb -- r g b ) + \ y: 8 [sp] + \ u: 4 [sp] = Cr + \ v: 0 [sp] = Cb + + d# 128 # 0 [sp] sub \ convert Cb to signed + d# 128 # 4 [sp] sub \ convert Cr to signed + 8 [sp] bx mov \ Get Y into register + + d# 90 # 4 [sp] ax imul-imm \ Multiply Cr by 1.402 * 64 (actually 1.406) + d# 6 # ax sar \ Scale down by 64 + bx ax add \ Add to Y + 0< if ax ax xor then \ Clip to 0 + d# 255 # ax cmp > if d# 255 # ax mov then \ Clip to 255 + + ax 8 [sp] mov \ Put R in place on stack + + d# -46 # 4 [sp] ax imul-imm \ Multiply Cr by -0.714 * 64 (actually -0.719) + d# 6 # ax sar \ Scale down by 64 + ax cx mov + d# -22 # 0 [sp] ax imul-imm \ Multiply Cr by -0.344 * 64 (actually -0.344) + d# 6 # ax sar \ Scale down by 64 + ax cx add + bx cx add \ Now we have G + 0< if cx cx xor then \ Clip to 0 + d# 255 # cx cmp > if d# 255 # cx mov then \ Clip to 255 + + d# 113 # 0 [sp] ax imul-imm \ Multiply Cr by 1.772 * 64 (actually 1.766) + d# 6 # ax sar \ Scale down by 64 + bx ax add \ Add to Y + 0< if ax ax xor then \ Clip to 0 + d# 255 # ax cmp > if d# 255 # ax mov then \ Clip to 255 + ax 0 [sp] mov \ Put B in place on stack + + cx 4 [sp] mov \ Put G in place on stack +c; + + +\ This version operates on pixel values in memory +\ Src bytes are Cb Y1 Cr Y2 (2 pixels) +\ Dst bytes are R G B A R G B A (2 pixels) + +code ycbcr422>rgba8888 ( src dst count -- ) + 4 [sp] di xchg \ di: dst + 8 [sp] si xchg \ si: src + + ax push ax push \ Space on stack for Cr and Cb values + + begin + \ src: Cb Y1 Cr Y2 dst: R1 G1 B1 A1 R2 G2 B2 A2 + ax ax xor al lods d# 128 # ax sub ax 0 [sp] mov \ Get Cb, make signed, save on stack + ax ax xor al lods ax bx mov \ Get Y1, save in BX + ax ax xor al lods d# 128 # ax sub ax 4 [sp] mov \ Get Cr, make signed, save on stack + + d# 90 # 4 [sp] ax imul-imm \ Multiply Cr by 1.402 * 64 (actually 1.406) + d# 6 # ax sar \ Scale down by 64 + bx ax add \ Add to Y + + 0< if ax ax xor then \ Clip to 0 + d# 255 # ax cmp > if d# 255 # ax mov then \ Clip to 255 + + al stos \ Output R + + d# -46 # 4 [sp] ax imul-imm \ Multiply Cr by -0.714 * 64 (actually -0.719) + d# 6 # ax sar \ Scale down by 64 + ax dx mov + d# -22 # 0 [sp] ax imul-imm \ Multiply Cr by -0.344 * 64 (actually -0.344) + d# 6 # ax sar \ Scale down by 64 + dx ax add + bx ax add \ Now we have G + + 0< if ax ax xor then \ Clip to 0 + d# 255 # ax cmp > if d# 255 # ax mov then \ Clip to 255 + + al stos \ Output G + + d# 113 # 0 [sp] ax imul-imm \ Multiply Cr by 1.772 * 64 (actually 1.766) + d# 6 # ax sar \ Scale down by 64 + bx ax add \ Add to Y + + 0< if ax ax xor then \ Clip to 0 + d# 255 # ax cmp > if d# 255 # ax mov then \ Clip to 255 + + al stos \ Output B + d# 255 # al mov + al stos \ Output A + + ax ax xor al lods ax bx mov \ Get Y2 into BX + + d# 90 # 4 [sp] ax imul-imm \ Multiply Cr by 1.402 * 64 (actually 1.406) + d# 6 # ax sar \ Scale down by 64 + bx ax add \ Add to Y + + 0< if ax ax xor then \ Clip to 0 + d# 255 # ax cmp > if d# 255 # ax mov then \ Clip to 255 + + al stos \ Output R + + d# -46 # 4 [sp] ax imul-imm \ Multiply Cr by -0.714 * 64 (actually -0.719) + d# 6 # ax sar \ Scale down by 64 + ax dx mov + d# -22 # 0 [sp] ax imul-imm \ Multiply Cr by -0.344 * 64 (actually -0.344) + d# 6 # ax sar \ Scale down by 64 + dx ax add + bx ax add \ Now we have G + + 0< if ax ax xor then \ Clip to 0 + d# 255 # ax cmp > if d# 255 # ax mov then \ Clip to 255 + + al stos \ Output G + + d# 113 # 0 [sp] ax imul-imm \ Multiply Cr by 1.772 * 64 (actually 1.766) + d# 6 # ax sar \ Scale down by 64 + bx ax add \ Add to Y + + 0< if ax ax xor then \ Clip to 0 + d# 255 # ax cmp > if d# 255 # ax mov then \ Clip to 255 + + al stos \ Output B + d# 255 # al mov + al stos \ Output A + + 8 [sp] dec + 0= until + + d# 12 [sp] sp lea \ Clean stack + 0 [sp] di xchg \ Restore EDI + 4 [sp] si xchg \ Restore ESI +c;

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[commit] r2110 - cpu/x86
by repository service 17 Jan '11

17 Jan '11

Author: wmb Date: Mon Jan 17 22:44:52 2011 New Revision: 2110 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2110 Log: X86 assembler - added imul-imm and imul2 for assembling alternative forms of the IMUL instruction. Trying to work out the instruction form automatically from the operands is just too hard. Modified: cpu/x86/assem.fth Modified: cpu/x86/assem.fth ============================================================================== --- cpu/x86/assem.fth Mon Jan 17 07:20:26 2011 (r2109) +++ cpu/x86/assem.fth Mon Jan 17 22:44:52 2011 (r2110) @@ -749,6 +749,25 @@ : rdmsr ( -- ) prefix-0f h# 32 asm8, ; : cpuid ( -- ) prefix-0f h# a2 asm8, ; \ Arg in %eax, results in ax,bx,dx,cx +: imul2 ( MR REG -- ) \ REG <- REG * R/M + prefix-0f h# AF asm8, r/m, +; + +: imul-imm ( imm # MR REG -- ) \ REG <- R/M * imm16/32 "500 # bx cx imul-imm" + here >r ( imm # MR r: adr ) + h# 69 asm8, ( imm # MR ) + r/m, ( imm # ) + # <> abort" Expecting # in imul-imm" ( imm ) + dup big? if ( imm r: adr ) + 16bit? if asm16, else asm32, then ( r: adr ) + r> drop ( ) + else ( imm r: adr ) + asm8, ( r: adr ) + \ Change the opcode from 69 to 6b + h# 6b r> asm8! ( ) + then +; + \ Structured Conditionals \ single pass forces fixed size. optimize for small, fast structures: \ always use 8-bit offsets.

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openfirmware January 2011