openfirmware November 2009

openfirmware@openfirmware.info

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r1460 - cpu/x86/pc/olpc/via
by svn＠openfirmware.info 06 Nov '09

06 Nov '09

Author: wmb Date: 2009-11-06 07:34:27 +0000 (Fri, 06 Nov 2009) New Revision: 1460 Modified: cpu/x86/pc/olpc/via/demodram.fth cpu/x86/pc/olpc/via/dramtiming.fth cpu/x86/pc/olpc/via/dumpvia.fth cpu/x86/pc/olpc/via/fw.bth cpu/x86/pc/olpc/via/ioinit.fth cpu/x86/pc/olpc/via/pcinode.fth cpu/x86/pc/olpc/via/romreset.bth cpu/x86/pc/olpc/via/startcominit.fth cpu/x86/pc/olpc/via/startgfxinit.fth cpu/x86/pc/olpc/via/startgtlinit.fth cpu/x86/pc/olpc/via/starthostctl.fth Log: Via - big mess o' tweaks to PCI config register values to make the settings match the Phoenix values as closely as possible. Trying to sort out why the screen tears on graphics accelerator operations in X, so minimizing differences from non-tearing case. Modified: cpu/x86/pc/olpc/via/demodram.fth =================================================================== --- cpu/x86/pc/olpc/via/demodram.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/demodram.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -19,7 +19,8 @@ [then] [ifdef] xo-board \ 0 3 devfunc 90 07 03 mreg end-table d# 20 wait-us \ 200 MHz ATEST - 0 3 devfunc 90 e7 03 mreg end-table d# 20 wait-us \ 200 MHz ATEST +\ 0 3 devfunc 90 e7 03 mreg end-table d# 20 wait-us \ 200 MHz ATEST + 0 3 devfunc 90 ff c3 mreg end-table d# 20 wait-us \ 200 MHz ATEST [then] 0 3 devfunc 6b d0 c0 mreg end-table d# 20 wait-us \ PLL Off 0 3 devfunc 6b 00 10 mreg end-table d# 20 wait-us \ PLL On @@ -207,10 +208,12 @@ \ DQSInputCaptureCtrl 77 bf 9b mreg \ DQS Input Delay - Manual, value from VIA's BIOS 78 3f 01 mreg \ 533: 3 667: 7 800: d DQS Input Capture Range Control A - 79 ff 83 mreg \ 533: 87 667: 89 800: 89 +\ 79 ff 83 mreg \ 533: 87 667: 89 800: 89 + 79 ff 80 mreg \ Reserved, perhaps for the snapshot RAM ? Phoenix value 7a ff 00 mreg \ Reserved 7b ff 10 mreg \ 533: 20 667: 34 800: 34 Read Data Phase Control - 8b ff 10 mreg \ 533: 20 667: 34 800: 34 +\ 8b ff 10 mreg \ 533: 20 667: 34 800: 34 + 8b ff 02 mreg \ Phoenix value [then] \ DCLKPhsCtrl - depends on which clock outputs are used @@ -218,7 +221,7 @@ 99 1e 12 mreg \ MCLKOA[3,2,1,0] outputs [then] [ifdef] xo-board - 99 1e 1e mreg \ MCLKOA[1,0] outputs + 99 1e 06 mreg \ MCLKOA[1,0] outputs [then] end-table @@ -368,11 +371,12 @@ forth #ranks 3 < assembler [if] 55 ff 00 mreg \ Rank map A 2/3 2 & 3 off -[then] -forth #ranks 3 = assembler [if] +[else] + forth #ranks 3 = assembler [if] 55 ff a0 mreg \ Rank map A 2/3 2 on 3 off -[else] + [else] 55 ff ab mreg \ Rank map A 2/3 2 & 3 on + [then] [then] 56 ff 00 mreg \ Rank map B ? @@ -402,6 +406,12 @@ h# 15 port80 + 0 3 devfunc + 52 77 11 mreg \ BA1 is A14, BA0 is A13 + 53 30 10 mreg \ BA2 is A15 + 69 20 20 mreg \ Bank address scramble + end-table + 0 [if] \ Very simple memtest long-offsets on ax ax xor @@ -463,6 +473,7 @@ [then] [ifdef] xo-board 96 0f 01 mreg \ Enable self-refresh for rank 0 + b1 ff aa mreg \ Reserved - Phoenix value [then] end-table Modified: cpu/x86/pc/olpc/via/dramtiming.fth =================================================================== --- cpu/x86/pc/olpc/via/dramtiming.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/dramtiming.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -32,7 +32,8 @@ \ DDR-400 timings for HY5PS1G4831C d# 5.00 to Tck -d# 127.50 constant Trfc +\ d# 127.50 constant Trfc +d# 125.00 constant Trfc \ Fudged to get same setting as Phoenix d# 7.50 constant Trrd \ d# 10.00 constant Trrd d# 3 constant TCL @@ -86,7 +87,8 @@ rank-size #ranks * constant total-size [then] -h# 400.0000 constant /fbmem +\ h# 400.0000 constant /fbmem +h# 1000.0000 constant /fbmem : >fbmem-base ( size/64M -- low high ) d# 26 lshift ( memsize-in-bytes ) /fbmem - ( memsize-less-framebuf-size ) Modified: cpu/x86/pc/olpc/via/dumpvia.fth =================================================================== --- cpu/x86/pc/olpc/via/dumpvia.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/dumpvia.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -12,41 +12,47 @@ : seq@ ( index -- value ) h# 3c4 pc! h# 3c5 pc@ ; : grf@ ( index -- value ) h# 3ce pc! h# 3cf pc@ ; : crt@ ( index -- value ) h# 3d4 pc! h# 3d5 pc@ ; -: seq. ( adr len -- ) bounds ?do i c@ seq@ 3 u.r loop ; +: .byte ( n -- ) push-hex 2 0.r space pop-base ; +: seq. ( adr len -- ) bounds ?do i c@ seq@ .byte loop ; : .regular - ." ATR " h# 15 0 do i attr@ 3 u.r loop cr + ." == VGA Registers - A=Attribute G=Graphics C=CRT S=Sequencer" cr + ." 0 1 2 3 4 5 6 7 8 9 a b c d e f" cr + ." MSC: " h# 3cc pc@ .byte cr + ." A00: " h# 10 0 do i attr@ .byte loop cr + ." A10: " h# 15 h# 10 do i attr@ .byte loop cr h# 20 video-mode! - ." SEQ " 5 0 do i seq@ 3 u.r loop cr - ." GRF " 9 0 do i grf@ 3 u.r loop cr -." 0 1 2 3 4 5 6 7 8 9 a b c d e f" cr - ." C00 " h# 10 0 do i crt@ 3 u.r loop cr - ." C10 " h# 19 h# 10 do i crt@ 3 u.r loop cr + ." G00: " 9 0 do i grf@ .byte loop cr + ." G20: " h# 23 h# 20 do i grf@ .byte loop cr ; -: .sextended - ." S10 " h# 1f h# 10 do i seq@ 3 u.r loop cr - ." S20 " " "(20 21 22 26 2a 2b 2c 2d 2e)" seq. cr - ." S30 " " "(31 35 36 3c 3d 3e 3f)" seq. cr - ." S40 " h# 50 h# 40 do i seq@ 3 u.r loop cr - ." S50 " h# 60 h# 50 do i seq@ 3 u.r loop cr - ." S60 " h# 70 h# 60 do i seq@ 3 u.r loop cr - ." S70 " h# 80 h# 70 do i seq@ 3 u.r loop cr - ." SA8 " h# b0 h# a8 do i seq@ 3 u.r loop cr - ." G20 " h# 23 h# 20 do i grf@ 3 u.r loop cr +: .seq + ." S00: " h# 10 0 do i seq@ .byte loop cr + ." S10: " h# 20 h# 10 do i seq@ .byte loop cr +\ ." S20 " " "(20 21 22 26 2a 2b 2c 2d 2e)" seq. cr +\ ." S30 " " "(31 35 36 3c 3d 3e 3f)" seq. cr + ." S20: " h# 30 h# 20 do i seq@ .byte loop cr + ." S30: " h# 40 h# 30 do i seq@ .byte loop cr + ." S40: " h# 50 h# 40 do i seq@ .byte loop cr + ." S50: " h# 60 h# 50 do i seq@ .byte loop cr + ." S60: " h# 70 h# 60 do i seq@ .byte loop cr + ." S70: " h# 80 h# 70 do i seq@ .byte loop cr + ." SA0: " h# b0 h# a0 do i seq@ .byte loop cr ; -: .cextended - ." C30 " h# 40 h# 30 do i crt@ 3 u.r loop cr - ." C40 " h# 49 h# 40 do i crt@ 3 u.r loop cr - ." C50 " h# 60 h# 50 do i crt@ 3 u.r loop cr - ." C60 " h# 70 h# 60 do i crt@ 3 u.r loop cr - ." C70 " h# 80 h# 70 do i crt@ 3 u.r loop cr - ." C80 " h# 90 h# 80 do i crt@ 3 u.r loop cr - ." C90 " h# a0 h# 90 do i crt@ 3 u.r loop cr - ." CA0 " h# b0 h# a0 do i crt@ 3 u.r loop cr - ." CD0 " h# e0 h# d0 do i crt@ 3 u.r loop cr - ." CE0 " h# f0 h# e0 do i crt@ 3 u.r loop cr - ." CF0 " h# fd h# f0 do i crt@ 3 u.r loop cr +: .crt + ." C00: " h# 10 0 do i crt@ .byte loop cr + ." C10: " h# 20 h# 10 do i crt@ .byte loop cr + ." C30: " h# 40 h# 30 do i crt@ .byte loop cr + ." C40: " h# 50 h# 40 do i crt@ .byte loop cr + ." C50: " h# 60 h# 50 do i crt@ .byte loop cr + ." C60: " h# 70 h# 60 do i crt@ .byte loop cr + ." C70: " h# 80 h# 70 do i crt@ .byte loop cr + ." C80: " h# 90 h# 80 do i crt@ .byte loop cr + ." C90: " h# a0 h# 90 do i crt@ .byte loop cr + ." CA0: " h# b0 h# a0 do i crt@ .byte loop cr + ." CD0: " h# e0 h# d0 do i crt@ .byte loop cr + ." CE0: " h# f0 h# e0 do i crt@ .byte loop cr + ." CF0: " h# fd h# f0 do i crt@ .byte loop cr ; -: .dpy .regular .cextended .sextended ; +: .dpy .regular .crt .seq ; \ b0 8b0 config-b@ -> 1 ( VGA in S.L.) \ b2 8b2 config-b@ -> 40 ( 256 MB memory base 0) @@ -58,6 +64,49 @@ : cw. dup (.2) type ." : " config-base + config-w@ (.4) type cr ; : cb. dup (.2) type ." : " config-base + config-b@ (.2) type cr ; : ch. config-base h# 40 bounds do i config-l@ u. 4 +loop cr ; +: .devfunc ( device function -- ) + ." == Device " swap .x ." Function " .x cr +; +: disabled? ( device function -- true | cfgaddr false ) + 2dup .devfunc ( device function ) + h# 100 * swap h# 800 * + ( base ) + dup config-l@ h# ffffffff = if ." Disabled" cr drop true exit then ( cfgaddr ) + false +; +defer dump-devfunc ( device function -- ) +: 0.r.upc + >r (u.) r> over - 0 max 0 ?do + 30 emit + loop 2dup upper type +; + +: dump-devfunc-via ( device function -- ) + disabled? if exit then ( cfgaddr ) + h# 100 0 do + i 8 bounds do + i 2 0.r.upc ." =" dup i + config-b@ 2 0.r.upc + i h# f and h# f <> if space then + loop + cr + h# 8 +loop + drop +; +: dump-devfunc-lspci ( device function -- ) + disabled? if exit then ( cfgaddr ) + h# 100 0 do + i 2 0.r ." : " + i h# 10 bounds do + dup i + config-b@ 2 0.r + i h# f and h# f <> if space then + loop + cr + h# 10 +loop + drop +; +: via-dump-mode ['] dump-devfunc-via to dump-devfunc ; +: lspci-dump-mode ['] dump-devfunc-lspci to dump-devfunc ; +via-dump-mode + : dump-d0f0 0 to config-base ." == D0F0 Host Control ==" cr @@ -706,7 +755,7 @@ cr ; -: dump-config-regs +: dump-config-regs-old dump-d0f0 dump-d0f1 dump-d0f2 @@ -726,6 +775,21 @@ dump-d20f0 ; +: dump-config-regs ( -- ) + 8 0 do 0 i dump-devfunc cr loop + d# 1 d# 0 dump-devfunc cr + d# 12 d# 0 dump-devfunc cr + d# 15 d# 0 dump-devfunc cr + d# 16 d# 0 dump-devfunc cr + d# 16 d# 1 dump-devfunc cr + d# 16 d# 2 dump-devfunc cr + d# 16 d# 4 dump-devfunc cr + d# 17 d# 0 dump-devfunc cr + d# 17 d# 7 dump-devfunc cr + d# 19 d# 0 dump-devfunc cr + d# 20 d# 0 dump-devfunc cr +; + [ifdef] apic-ih : ap. ( index -- ) dup (.4) type ." : " ( index ) @@ -791,4 +855,5 @@ dump-apic dump-io-apic [then] + .dpy ; Modified: cpu/x86/pc/olpc/via/fw.bth =================================================================== --- cpu/x86/pc/olpc/via/fw.bth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/fw.bth 2009-11-06 07:34:27 UTC (rev 1460) @@ -629,6 +629,11 @@ ; [then] +: pci-fixup ( -- ) + h# 43 h# 8804 config-b! \ Enable parity checking on D17F0 + h# 0800 h# 8f0c config-w! \ Override pcibus.fth latency timer setting for North/South Module +; + : startup ( -- ) standalone? 0= if exit then @@ -654,6 +659,8 @@ " probe-" do-drop-in probe-pci + pci-fixup + show-child install-alarm sound Modified: cpu/x86/pc/olpc/via/ioinit.fth =================================================================== --- cpu/x86/pc/olpc/via/ioinit.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/ioinit.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -10,6 +10,24 @@ 0833152d 062c config-wl 0833152d 072c config-wl +\ Cache line size (low byte) / latency timer (high byte) registers +2008 000c config-ww +0008 010c config-ww +0008 020c config-ww +0008 040c config-ww +0008 050c config-ww +0008 060c config-ww +0008 070c config-ww +2000 080c config-ww +2000 780c config-ww +2008 800c config-ww +2008 810c config-ww +2008 820c config-ww +2008 830c config-ww +2010 840c config-ww +0800 8f0c config-ww +0008 a00c config-ww + 0 4 devfunc \ PM_table a0 80 80 mreg \ Enable dynamic power management (coreboot for vx800 uses f0; 70 bits are reserved on vx855) a1 e0 e0 mreg \ Dynamic power management for DRAM @@ -62,7 +80,19 @@ 90 ff ff mreg \ Gate clocks 91 ff ff mreg \ Gate clocks 92 cc cc mreg \ Dynamic buffer control, power down comparators + 95 ff 01 mreg \ Reserved - Phoenix value + a5 ff 00 mreg \ Reserved - Phoenix value a8 20 20 mreg \ Central traffic controller dynamic clock stop + d1 ff 01 mreg \ BIOS scratch - Phoenix value + d2 ff 02 mreg \ BIOS scratch - Phoenix value + d3 ff 03 mreg \ BIOS scratch - Phoenix value + d4 ff 10 mreg \ BIOS scratch - Phoenix value + d8 ff 10 mreg \ BIOS scratch - Phoenix value + e4 ff 2a mreg \ BIOS scratch - Phoenix value + e8 ff 10 mreg \ BIOS scratch - Phoenix value + e9 ff fa mreg \ BIOS scratch - Phoenix value + eb ff 01 mreg \ BIOS scratch - Phoenix value + f6 ff 01 mreg \ Reserved - Phoenix value end-table \ Bus tuning @@ -72,13 +102,20 @@ 59 0f 02 mreg \ IGFX Promote Timer value 2 5f 0f 06 mreg \ IPI Promote Timer value 6 64 20 00 mreg \ Upstream MSI doesn't flush queued P2C Write Data + 72 ff 09 mreg \ Reserved - Phoenix value 80 0b 08 mreg \ Upstream Request 1T earlier + 81 ff 9a mreg \ Reserved - Phoenix value 83 ff 81 mreg \ P2PW down arb timer timer 8, P2PR down arb timer timer 1 84 7f 28 mreg \ Downstream arbitration Timeout timer for C2P 85 c0 c0 mreg \ Abort P2P cycle to PCI1, CPU to PCI1 cycle blocks next C2P cycle a3 01 01 mreg \ 01 res be like Phx end-table + 0 7 devfunc + e5 ff 40 mreg \ Reserved - Phoenix value + e6 ff 29 mreg \ Reserved - Phoenix value + end-table + 0 [if] d# 11 0 devfunc \ USB device 41 18 18 mreg \ Enable backdoor @@ -91,6 +128,7 @@ [then] d# 12 0 devfunc \ SDIO tuning + 04 10 10 mreg \ Enable Memory Write and Invalidate 44 01 01 mreg \ Enable backdoor 2c ff 2d mreg \ Subsystem ID backdoor 2d ff 15 mreg \ Subsystem ID backdoor @@ -105,6 +143,7 @@ 99 ff f9 mreg \ Two slots [then] [ifdef] xo-board +\ 98 ff 20 mreg \ Set Reserved bit - Phoenix value - No, SD fails to start the clock if this bit is set 99 ff fa mreg \ Three slots [then] end-table @@ -142,6 +181,7 @@ \ USB Tuning d# 16 0 devfunc \ UHCI Ports 0,1 + 04 10 10 mreg \ Enable Memory Write and Invalidate 42 10 10 mreg \ Enable backdoor 2c ff 2d mreg \ Subsystem ID backdoor 2d ff 15 mreg \ Subsystem ID backdoor @@ -154,6 +194,7 @@ end-table d# 16 1 devfunc \ UHCI Ports 2,3 + 04 10 10 mreg \ Enable Memory Write and Invalidate 42 10 10 mreg \ Enable backdoor 2c ff 2d mreg \ Subsystem ID backdoor 2d ff 15 mreg \ Subsystem ID backdoor @@ -167,6 +208,7 @@ [ifndef] xo-board d# 16 2 devfunc \ UHCI Ports 4,5 + 04 10 10 mreg \ Enable Memory Write and Invalidate 42 10 10 mreg \ Enable backdoor 2c ff 2d mreg \ Subsystem ID backdoor 2d ff 15 mreg \ Subsystem ID backdoor @@ -181,6 +223,7 @@ d# 16 4 devfunc \ EHCI + 04 10 10 mreg \ Enable Memory Write and Invalidate 42 10 10 mreg \ Enable backdoor 2c ff 2d mreg \ Subsystem ID backdoor 2d ff 15 mreg \ Subsystem ID backdoor @@ -191,20 +234,22 @@ 42 40 40 mreg \ Enable Check PRESOF of ITDOUT Transaction during Fetching Data from DRAM 43 c0 c0 mreg \ Enable Dynamic Clock Scheme - 66MHz (80) & 33MHz (40) 48 20 00 mreg \ Disable DMA bursts + 4b 60 60 mreg \ EHCI sleep timeout to match Via settings +\ 4b 60 00 mreg \ Via setting of 60 doesn't work with USB LAN device 4c 03 03 mreg \ Squelch detector fine tune - 01 is 112.5 mV 4d 10 10 mreg \ 10 res be like Phx 4e 03 03 mreg \ reserved bit - setting is appropriate for vx800 03 res be like Phx 4f 10 10 mreg \ Enable Clear RUN Bit when EHCI_IDLE 50 80 80 mreg \ Fetch one more QH before de-asserting Doorbell 52 ff 11 mreg \ be like Phx - 53 ff 3f mreg \ be like Phx + 53 ff bf mreg \ Via settings, different from old Phx 55 ff ff mreg \ Disconnect level fine tune - 575 mV for ports 0-3 56 0f 0f mreg \ Disconnect level fine tune - 575 mV for ports 4-5 5a ff cc mreg \ HS termination resistor fine tune - 45 ohm, 48 ohm for ports 0,1 5b ff cc mreg \ HS termination resistor fine tune - 45 ohm, 48 ohm for ports 2,3 5c 0f 00 mreg \ DPLL Track Speed 2, DPLL Lock Speed 2 5d ff cc mreg \ HS termination resistor fine tune - 45 ohm, 48 ohm for ports 4,5 - 64 05 05 mreg \ Bump NULL-SOF valid time to 8 micro frames (04), Inhibit C4 state on USB 1.1 ISO activity (01) + 64 07 03 mreg \ High bit of NULL-SOF valid time (04=00), HS ISO actitivy (02) and USB 1.1 ISO activity (01) inhibit C4 end-table [ifdef] xo-board @@ -217,6 +262,7 @@ [then] d# 17 0 devfunc \ Bus control and power management + 04 40 40 mreg \ Check parity 40 44 44 mreg \ Enable I/O Recovery time (40), Enable ports 4d0/4d1 for edge/level setting (04) [ifdef] xo-board 41 40 40 mreg \ Enable fff0.0000-fff7.ffff ROM on LPC bus @@ -230,7 +276,8 @@ 50 40 40 mreg \ Disable USB device mode [then] [ifdef] xo-board - 50 4c 4c mreg \ Disable USB device mode, unused USB 1.1 ports 4,5, and EIDE device +\ 50 4c 4c mreg \ Disable USB device mode, unused USB 1.1 ports 4,5, and EIDE device + 50 cc cc mreg \ Disable USB device mode, unused USB 1.1 ports 4,5, and EIDE device (set rsvd 80 bit to Phoenix value) 51 9f 88 mreg \ Enable SDIO and internal RTC, disable card reader, int mouse & kbd [then] @@ -315,7 +362,7 @@ b0 08 00 mreg \ The BIOS Porting Note says to clear this bit. Phoenix and coreboot agree. b4 80 00 mreg \ No positive decoding for UART1 ??? - b7 40 40 mreg \ 40 res be like Phx +\ b7 40 40 mreg \ 40 res be like Phx (Phoenix now uses 00) uart-dma-io-base wbsplit swap ( bits15:8 bits7:0 ) b8 fc rot mreg \ UART DMA Control Registers Base low (port is 4080) b9 ff rot mreg \ UART DMA Control Registers Base high @@ -330,7 +377,8 @@ d0 f0 rot mreg \ SMBUS IO Base Address low (port is 0500) d1 ff rot mreg \ SMBUS IO Base Address high d2 0f 01 mreg \ Enable SMBUS and set other characteristics - e2 80 80 mreg \ Inhibit C4 during USB isochronous transaction +\ e2 80 80 mreg \ Inhibit C4 during USB isochronous transaction + e2 ff e9 mreg \ Inhibit C4 during USB isochronous transaction, other bits reserved - Phoenix value [ifdef] demo-board e4 ff a0 mreg \ Enable short C3/C4 (80), select various multi-function pins [then] @@ -350,6 +398,7 @@ end-table d# 17 7 devfunc \ South-North Module Interface Control + 4e ff 80 mreg \ Reserved - Phoenix value 50 df 08 mreg \ SM priorities - HDAC high priority, others low 51 80 80 mreg \ Enable subtractive decode for P2P cycle 54 7b 02 mreg \ CCA REQ timing - synchronize USB REQ but not others @@ -372,17 +421,27 @@ 80 07 07 mreg \ PCI1 and HDAC upstream read does not pass write, APCI blocks upstream write \ 82 3e 20 mreg \ Monitor CCA and SDIO2 82 3f 21 mreg \ Monitor CCA and SDIO2 - 01 res be like Phx + 88 ff 02 mreg \ Reserved - Phoenix value \ e0 e0 80 mreg \ Dynamic CCA clock e0 f3 93 mreg \ Dynamic CCA clock - 13 res be like Phx + e1 ff 08 mreg \ Reserved - Phoenix value \ e2 1e 00 mreg \ Use dynamic clocks for Downstream Interface, PCI1, Downstream HDAC, Downstream SM Internal PCI device e2 1f 00 mreg \ Use dynamic clocks for Downstream Interface, PCI1, Downstream HDAC, Downstream SM Internal PCI device 01 res be like Phx e3 ff 5e mreg \ PCI1 dynamic clock, PCI clock on when GRANT# asserted, Enable P2CR data timeout at 7*8 PCI clocks \ e6 1f 1f mreg \ Split APIC decoding, Snoop FEEx.xxxx, Enable top SMM, High SMM, Compat SMM (20 bit is reserved) - e6 1f 19 mreg \ Split APIC decoding, Snoop FEEx.xxxx, Enable top SMM, High SMM, Compat SMM (20 bit is reserved) + e6 3f 39 mreg \ Split APIC decoding, Snoop FEEx.xxxx, Enable top SMM, High SMM, Compat SMM (20 bit is reserved) \ fc 40 40 mreg \ Enable CCA Read Clock When MTXCTL state machine is not idle fc 48 48 mreg \ Enable CCA Read Clock When MTXCTL state machine is not idle - 08 res be like Phx end-table + d# 19 0 devfunc \ P2P Bridge + 04 ff 07 mreg \ Mem, IO, Bus Master Enable + 05 ff 01 mreg \ SERR# enable + 19 ff 01 mreg \ Secondary bus number + 1a ff 01 mreg \ Subordinate bus number + 3e ff 04 mreg \ ISA Enable + end-table + d# 20 0 devfunc 41 01 01 mreg \ Dynamic clock for HDAC 40 01 01 mreg \ Enable backdoor Modified: cpu/x86/pc/olpc/via/pcinode.fth =================================================================== --- cpu/x86/pc/olpc/via/pcinode.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/pcinode.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -1,6 +1,8 @@ \ See license at end of file purpose: PCI bus package +d# 33,333,333 " clock-frequency" integer-property + : preassigned-pci-slot? ( my-space -- flag ) h# f.f800 and dup h# 800 = if drop true exit then @@ -115,6 +117,7 @@ \ Wouldn't it be nice if you could get the argument to pirq@ from \ the interrupt pin register (offset 3d)? But that doesn't work, \ because some devices say pin A but use PIRQB. + h# 0800 of d# 10 set-level-trigger true exit endof \ Display h# 5800 of 1 pirq@ set-level-trigger true exit endof \ USB device - PIRQB h# 6000 of 0 pirq@ set-level-trigger true exit endof \ SDIO - PIRQA h# 6800 of 0 pirq@ set-level-trigger true exit endof \ SDC - PIRQA Modified: cpu/x86/pc/olpc/via/romreset.bth =================================================================== --- cpu/x86/pc/olpc/via/romreset.bth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/romreset.bth 2009-11-06 07:34:27 UTC (rev 1460) @@ -116,16 +116,21 @@ \ This is a device ID backdoor to fake out the ID so Ubuntu will install \ 8879 config-rb h# 40 # al or al dx out \ I don't know what this is, but coreboot does it - fload ${BP}/cpu/x86/pc/olpc/via/starthostctl.fth - acpi-io-base 1 + 8888 config-ww \ Set ACPI base address acpi-io-base wbsplit 0292 config-wb 0293 config-wb \ ACPI base address for C-states, big-endian [ifdef] debug-startup cominit #) call [then] + char + report - char + report + fload ${BP}/cpu/x86/pc/olpc/via/starthostctl.fth + +[ifdef] debug-startup +\ cominit #) call +[then] + +\ char + report long-offsets on acpi-io-base 4 + port-rw \ Get APCI Status register @@ -144,8 +149,10 @@ \ This must be done in both the power-up and resume-from-S3 cases, \ since the registers in D17F7 lose state during S3. - 0385 config-rb ax bx mov 8fe5 config-setup bx ax mov al dx out \ Copy Low Top from reg 85 to SB Low Top e5 - 0385 config-rb ax bx mov 8f60 config-setup bx ax mov al dx out \ Copy Low Top from reg 85 to SB Bank 7 end 60 + 80 8fe5 config-wb \ Phoenix value + 80 8f60 config-wb \ Phoenix value +\ 0385 config-rb ax bx mov 8fe5 config-setup bx ax mov al dx out \ Copy Low Top from reg 85 to SB Low Top e5 +\ 0385 config-rb ax bx mov 8f60 config-setup bx ax mov al dx out \ Copy Low Top from reg 85 to SB Bank 7 end 60 \ d# 17 7 devfunc \ e6 ff 07 mreg \ Enable Top, High, and Compatible SMM @@ -251,7 +258,7 @@ char o report h# 1e port80 -\ fload ${BP}/cpu/x86/pc/olpc/via/startgtlinit.fth + fload ${BP}/cpu/x86/pc/olpc/via/startgtlinit.fth \ Enable the keyboard controller Modified: cpu/x86/pc/olpc/via/startcominit.fth =================================================================== --- cpu/x86/pc/olpc/via/startcominit.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/startcominit.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -34,7 +34,8 @@ d# 17 0 devfunc 40 44 44 mreg \ Enable I/O Recovery time (40), Enable ports 4d0/4d1 for edge/level setting (04) 43 0f 0b mreg \ Enable PCI delayed transactions (08), Write transaction timer (02), Read transaction timer (01) - 4c c0 40 mreg \ Set I/O recovery time to 2 bus clocks +\ 4c c0 40 mreg \ Set I/O recovery time to 2 bus clocks + 4c c0 00 mreg \ Set I/O recovery time to 1 bus clock 59 ff 1c mreg \ Keyboard (ports 60,64) and ports 62,66 on LPC bus (EC) 5c ff 68 mreg \ High byte (68) of PCS0 5d ff 00 mreg \ High byte (00) of PCS0 Modified: cpu/x86/pc/olpc/via/startgfxinit.fth =================================================================== --- cpu/x86/pc/olpc/via/startgfxinit.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/startgfxinit.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -33,7 +33,8 @@ end-table 1 0 devfunc - b0 07 03 mreg \ VGA memory selection (coreboot uses 03, Phoenix 01. I think 03 is correct) +\ b0 07 03 mreg \ VGA memory selection (coreboot uses 03, Phoenix 01. I think 03 is correct) + b0 07 01 mreg \ VGA memory selection (coreboot uses 03, Phoenix 01. I think 03 is correct) end-table 01 3c3 port-wb \ Graphics chip IO port access on @@ -44,8 +45,13 @@ 68 3c4 port-wb ( size ) 3c5 port-wb \ Size of System Local Frame Buffer - Value depends on frame buffer size \ 00:512MB 80:256MB c0:128MB e0:64MB f0:32MB f8:16MB fc:8MB fe:4MB ff:2MB - \ These 2 are scratch registers that communicate with the VGA BIOS - 3d 3d4 port-wb 74 3d5 port-wb \ Value depends on DIMM frequency - used by VGA BIOS + \ These are scratch registers that communicate from the VGA BIOS to the OS driver + 3b 3d4 port-wb 02 3d5 port-wb \ TV standard + 3c 3d4 port-wb 08 3d5 port-wb \ Don't know what this is + 3d 3d4 port-wb 64 3d5 port-wb \ Value depends on DIMM frequency - 6 in high nibble is DDR-400 + 3e 3d4 port-wb 20 3d5 port-wb \ Active device + 3f 3d4 port-wb 0b 3d5 port-wb \ Panel size + 39 3c4 port-wb /fbmem d# 22 rshift 3c5 port-wb \ BIOS Reserved Register 0 - FBsize_MiB/4 - VGA BIOS 5a 3c4 port-wb 01 3c5 port-wb \ Point to secondary registers Modified: cpu/x86/pc/olpc/via/startgtlinit.fth =================================================================== --- cpu/x86/pc/olpc/via/startgtlinit.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/startgtlinit.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -1,5 +1,9 @@ \ After-the-fact tweaks to ROMSIP values 0 2 devfunc + c0 ff 75 mreg + c5 ff 20 mreg + c8 ff 04 mreg +0 [if] 70 ff 55 mreg 71 ff aa mreg 72 ff 66 mreg @@ -56,4 +60,5 @@ c9 00 00 mreg ca b7 10 mreg cb b7 04 mreg +[then] end-table Modified: cpu/x86/pc/olpc/via/starthostctl.fth =================================================================== --- cpu/x86/pc/olpc/via/starthostctl.fth 2009-11-05 00:55:52 UTC (rev 1459) +++ cpu/x86/pc/olpc/via/starthostctl.fth 2009-11-06 07:34:27 UTC (rev 1460) @@ -1,7 +1,7 @@ \ enable_mainboard_devices() \ 41 8f4f config-wb \ Enable P2P Bridge Header for External PCI Bus (coreboot value) -\ 43 8f4f config-wb \ As above, plus support extended PCIe config space - 1 8f4f config-wb \ Disable P2P bridge + 43 8f4f config-wb \ As above, plus support extended PCIe config space +\ 1 8f4f config-wb \ Disable P2P bridge \ 4f6 config-rb \ Get Northbridge revision ... don't need it because the \ init table contains no revision-specific entries @@ -11,7 +11,8 @@ \ Enable extended config space for PCIe 0 5 devfunc \ NB_APIC 61 ff 0e mreg \ Set Exxxxxxx as PCIe MMIO config range - 60 f4 13 mreg \ Support extended cfg address of PCIe (preserve 28 bits) (coreboot used vx800 bit resv in vx855) +\ 60 f4 13 mreg \ Support extended cfg address of PCIe (preserve 28 bits) (coreboot used vx800 bit resv in vx855) + 60 fc 13 mreg \ Support extended cfg address of PCIe (preserve 28 bits) (coreboot used vx800 bit resv in vx855), Phoenix value end-table 0 2 devfunc \ HOST CPU CTL @@ -23,7 +24,7 @@ 53 ff 44 mreg \ Arbitration: Host/Master Occupancy timer = 4*4 HCLK 54 1e 1c mreg \ Misc Ctrl: Enable 8QW burst Mem Access - 55 06 04 mreg \ Miscellaneous Control 2 + 55 06 04 mreg \ Miscellaneous Control 2 - Several T faster read cycle 56 f7 63 mreg \ Write Policy 1 57 01 01 mreg \ Enable fast TRDY by detecting HREQa[5]# de-assertion 5d ff a2 mreg \ Write Policy @@ -55,6 +56,7 @@ 51 80 80 mreg \ Last step - enable DRDY timing [then] [ifdef] xo-board +.( HELLO) cr 60 ff 2a mreg \ DRDY Timing Control 1 for Read Line 61 ff 00 mreg \ DRDY Timing Control 2 for Read Line 62 ff 00 mreg \ Reserved, probably channel B

1 0

r1459 - dev/usb2/hcd/ehci
by svn＠openfirmware.info 05 Nov '09

05 Nov '09

Author: wmb Date: 2009-11-05 00:55:52 +0000 (Thu, 05 Nov 2009) New Revision: 1459 Modified: dev/usb2/hcd/ehci/bulk.fth Log: OLPC trac 9611 - EHCI USB 2.0 driver - When a pipe has to be unstalled, the execution of control-set from inside a bulk-out transaction killed the "my-qh" value, leading to erratic behavior such as page faults. Modified: dev/usb2/hcd/ehci/bulk.fth =================================================================== --- dev/usb2/hcd/ehci/bulk.fth 2009-11-04 11:02:54 UTC (rev 1458) +++ dev/usb2/hcd/ehci/bulk.fth 2009-11-05 00:55:52 UTC (rev 1459) @@ -20,6 +20,9 @@ 0 instance value bulk-out-qh \ For begin-bulk-out-ring ... 0 instance value bulk-out-qtd \ For begin-bulk-out-ring ... +0 instance value my-bulk-qh \ Cannot use my-qh because unstall-pipe kills it +0 instance value my-bulk-qtd + : bulk-in-data@ ( -- n ) bulk-in-pipe target di-in-data@ di-data>td-data ; : bulk-out-data@ ( -- n ) bulk-out-pipe target di-out-data@ di-data>td-data ; : bulk-in-data! ( n -- ) td-data>di-data bulk-in-pipe target di-in-data! ; @@ -443,43 +446,43 @@ debug? if ." bulk-in" cr then dup to bulk-in-pipe process-bulk-args - ?alloc-bulk-qhqtds to my-qtd to my-qh - bulk-in-timeout my-qh >qh-timeout l! + ?alloc-bulk-qhqtds to my-bulk-qtd to my-bulk-qh + bulk-in-timeout my-bulk-qh >qh-timeout l! \ IN qTDs - TD_PID_IN my-qtd fill-bulk-io-qtds + TD_PID_IN my-bulk-qtd fill-bulk-io-qtds \ Start bulk in transaction - my-qh pt-bulk fill-qh - my-qh insert-qh + my-bulk-qh pt-bulk fill-qh + my-bulk-qh insert-qh \ Process results - my-qh done? if + my-bulk-qh done? if ( ) 0 ( actual ) \ System error, timeout - else - my-qh error? if + else ( ) + my-bulk-qh error? if ( ) 0 ( actual ) \ USB error - else - my-qtd dup my-#qtds get-actual ( qtd actual ) + else ( ) + my-bulk-qtd dup my-#qtds get-actual ( qtd actual ) over >qtd-buf l@ rot >qtd-pbuf l@ 2 pick dma-sync ( actual ) - then - then + then ( actual ) + then ( actual ) usb-error ( actual usberr ) - my-qtd map-out-bptrs - my-qh dup fixup-bulk-in-data - remove-qh + my-bulk-qtd map-out-bptrs ( actual usberr ) + my-bulk-qh dup fixup-bulk-in-data ( actual usberr ) + remove-qh ( actual usberr ) ; 0 instance value bulk-out-busy? : done-bulk-out ( -- error? ) \ Process results - my-qh done? 0= if my-qh error? drop then + my-bulk-qh done? 0= if my-bulk-qh error? drop then usb-error ( usberr ) - my-qtd map-out-bptrs ( usberr ) - my-qh fixup-bulk-out-data ( usberr ) - my-qh remove-qh ( usberr ) + my-bulk-qtd map-out-bptrs ( usberr ) + my-bulk-qh fixup-bulk-out-data ( usberr ) + my-bulk-qh remove-qh ( usberr ) false to bulk-out-busy? ( usberr ) ; : start-bulk-out ( buf len pipe -- usberr ) @@ -490,16 +493,16 @@ debug? if ." bulk-out" cr then dup to bulk-out-pipe ( buf len pipe ) process-bulk-args ( ) - ?alloc-bulk-qhqtds to my-qtd to my-qh ( ) - bulk-out-timeout my-qh >qh-timeout l! ( ) - my-qh >hcqh-overlay >hcqtd-token dup le-l@ TD_STAT_PING or swap le-l! + ?alloc-bulk-qhqtds to my-bulk-qtd to my-bulk-qh ( ) + bulk-out-timeout my-bulk-qh >qh-timeout l! ( ) + my-bulk-qh >hcqh-overlay >hcqtd-token dup le-l@ TD_STAT_PING or swap le-l! \ OUT qTDs - TD_PID_OUT my-qtd fill-bulk-io-qtds ( ) + TD_PID_OUT my-bulk-qtd fill-bulk-io-qtds ( ) \ Start bulk out transaction - my-qh pt-bulk fill-qh ( ) - my-qh insert-qh ( ) + my-bulk-qh pt-bulk fill-qh ( ) + my-bulk-qh insert-qh ( ) true to bulk-out-busy? ( ) 0 ( usberr ) ;

1 0

r1458 - cpu/x86/pc/olpc/via dev/mmc/sdhci dev/olpc/dcon
by svn＠openfirmware.info 04 Nov '09

04 Nov '09

Author: wmb Date: 2009-11-04 12:02:54 +0100 (Wed, 04 Nov 2009) New Revision: 1458 Modified: cpu/x86/pc/olpc/via/versions.fth dev/mmc/sdhci/sdhcixo.bth dev/olpc/dcon/viadcon.fth Log: OLPC trac 9489 - implement SD port reassignments and DCONINT GPIO change for B3 build. Modified: cpu/x86/pc/olpc/via/versions.fth =================================================================== --- cpu/x86/pc/olpc/via/versions.fth 2009-11-03 22:12:32 UTC (rev 1457) +++ cpu/x86/pc/olpc/via/versions.fth 2009-11-04 11:02:54 UTC (rev 1458) @@ -2,7 +2,7 @@ \ The overall firmware revision macro: FW_MAJOR A -macro: FW_MINOR 15 +macro: FW_MINOR 15b \ The EC microcode macro: EC_VERSION 1_9_14 Modified: dev/mmc/sdhci/sdhcixo.bth =================================================================== --- dev/mmc/sdhci/sdhcixo.bth 2009-11-03 22:12:32 UTC (rev 1457) +++ dev/mmc/sdhci/sdhcixo.bth 2009-11-04 11:02:54 UTC (rev 1458) @@ -13,7 +13,10 @@ init : populate-children ( -- ) - " atest?" evaluate if + " board-revision" evaluate ( boardrev ) + + dup h# d10 < if \ A1 and A2 + drop new-device 2 encode-int " reg" property " sdmmc" " $load-driver" eval drop @@ -23,24 +26,49 @@ 1 encode-int " reg" property " mv8686" " $load-driver" eval drop finish-device - else + exit + then + + dup h# d28 >= if \ B3 and greater + drop + new-device 1 encode-int " reg" property " sdmmc" " $load-driver" eval drop - " internal" " slot-name" string-property + " external" " slot-name" string-property finish-device new-device 2 encode-int " reg" property - " sdmmc" " $load-driver" eval drop - " external" " slot-name" string-property + " mv8686" " $load-driver" eval drop finish-device new-device 3 encode-int " reg" property - " mv8686" " $load-driver" eval drop + " sdmmc" " $load-driver" eval drop + " internal" " slot-name" string-property finish-device then + + \ B1,B2 + drop + + new-device + 1 encode-int " reg" property + " sdmmc" " $load-driver" eval drop + " internal" " slot-name" string-property + finish-device + + new-device + 2 encode-int " reg" property + " sdmmc" " $load-driver" eval drop + " external" " slot-name" string-property + finish-device + + new-device + 3 encode-int " reg" property + " mv8686" " $load-driver" eval drop + finish-device ; populate-children Modified: dev/olpc/dcon/viadcon.fth =================================================================== --- dev/olpc/dcon/viadcon.fth 2009-11-03 22:12:32 UTC (rev 1457) +++ dev/olpc/dcon/viadcon.fth 2009-11-04 11:02:54 UTC (rev 1458) @@ -28,10 +28,12 @@ \ h# 4000 constant DM_DEBUG \ h# 8000 constant DM_SELFTEST +: b3+? ( -- flag ) board-revision h# d28 >= ; + \ Enable SMBALRT# IRQ as DCON IRQ -: dcon-enable-irq ( -- ) 8 8 smb-reg! ; +: dcon-enable-irq ( -- ) b3+? if exit then 8 8 smb-reg! ; \ Disable SMBALRT# IRQ as DCON IRQ; leaving it enabled causes spurious S3 wakeups -: dcon-disable-irq ( -- ) 0 8 smb-reg! ; +: dcon-disable-irq ( -- ) b3+? if exit then 0 8 smb-reg! ; : dcon-load ( -- ) atest? if @@ -49,8 +51,8 @@ ; : dcon-blnk? ( -- flag ) h# 4a acpi-b@ 4 and 0<> ; : dcon-stat@ ( -- n ) h# 4b acpi-b@ 3 and ; -: dcon-irq? ( -- flag ) 1 smb-reg@ h# 20 and 0<> ; -: dcon-clr-irq ( -- ) h# 20 1 smb-reg! ; +: dcon-irq? ( -- flag ) b3+? if 4a acpi-b@ h# 40 else 1 smb-reg@ h# 20 then and 0<> ; +: dcon-clr-irq ( -- ) b3+? if exit then h# 20 1 smb-reg! ; \ DCONSTAT values: 0 SCANINT 1 SCANINT_DCON 2 DISPLAYLOAD 3 MISSED @@ -72,15 +74,16 @@ : wait-dcon-mode ( -- ) dcon-enable-irq - d# 100 ms-factor * tsc@ drop + ( end-time ) + 8 acpi-l@ d# 357,955 + ( end-time ) \ 100 ms timeout begin ( end-time ) dcon-irq? if dcon-disable-irq dcon-stat@ dcon-clr-irq 2 = if \ DCONSTAT=10 drop exit then + dcon-enable-irq then - dup tsc@ drop - 0< ( end-time reached? ) + dup 8 acpi-l@ - 0< ( end-time reached? ) until ( end-time ) drop dcon-disable-irq @@ -195,46 +198,6 @@ 1 set-source \ Unfreeze image ; -0 [if] -dconstat dconblnk or dconirq or constant in-gpios -dconload constant out-gpios - -: dcon-gpio-init ( -- ) - out-gpios in-gpios wljoin OUT_EN gpio! - in-gpios out-gpios wljoin IN_EN gpio! - - dconirq >set INV_EN gpio! - - dconirq dconblnk or ( events ) - -\ Linux doesn't want me to turn these on -\ dup >set EVNT_EN gpio! -\ dup >set IN_FLTR_EN gpio! \ Enable counter for GPIO7 (DCONIRQ) -\ dup >clr EVNTCNT_EN gpio! -\ d# 12 gpio-base h# f7 + rb! \ GPIO_FE7_SEL -\ dup >clr h# 44 gpio! \ NEGEDGE_EN - -\ 0 gpio-base h# d8 + rw! \ GPIO_FLTR7_AMNT - - h# e0 gpio@ h# 0fff.ffff and h# 2000.0000 or h# e0 gpio! \ p512 Map X - h# e4 gpio@ h# fff0.ffff and h# 0000.0000 or h# e4 gpio! \ p511 Map Y - -[ifdef] dcon-interrupts - h# 5140.0023 rdmsr ( lo hi ) drop ( lo ) - h# ff0f.fffff and h# 0050.0000 or 0 wrmsrl \ p 381 unrestricted Z - 0 h# 4d0 pc! \ IRQs 0-7 edge sensitive -[then] - - ( events ) - dup >set IN_EN gpio! - >set h# 4c gpio! \ GPIOL_NEGEDGE_STS - clear detected edges - - dcon-load - - \ ['] dcon-interrupt 5 request_irq -; -[then] - 0 value dcon-found? d# 440 8 / constant dcon-flag

1 0

r1457 - cpu/x86/pc/olpc/via
by svn＠openfirmware.info 03 Nov '09

03 Nov '09

Author: wmb Date: 2009-11-03 23:12:32 +0100 (Tue, 03 Nov 2009) New Revision: 1457 Modified: cpu/x86/pc/olpc/via/dsdt.dsl Log: OLPC Via - DSDT source formatting from Paul Fox: Remove all trailing whitespace. Modified: cpu/x86/pc/olpc/via/dsdt.dsl =================================================================== --- cpu/x86/pc/olpc/via/dsdt.dsl 2009-11-03 22:10:14 UTC (rev 1456) +++ cpu/x86/pc/olpc/via/dsdt.dsl 2009-11-03 22:12:32 UTC (rev 1457) @@ -8,10 +8,10 @@ // distribute, sublicense, and/or sell copies of the Software, and to // permit persons to whom the Software is furnished to do so, subject to // the following conditions: -// +// // The above copyright notice and this permission notice shall be // included in all copies or substantial portions of the Software. -// +// // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND @@ -40,8 +40,8 @@ Field (UART, ByteAcc, NoLock, Preserve) { - UDAT, 8, - UAR1, 8, + UDAT, 8, + UAR1, 8, UAR2, 8, UAR3, 8, UAR4, 8, @@ -69,7 +69,7 @@ Add (Local0, 0x57, Local0) // 'a' - 10 } UPUT (Local0) - + And (Arg0, 0xF, Local0) If (LLess (Local0, 10)) { Add (Local0, 0x30, Local0) // '0' @@ -145,7 +145,7 @@ GS13,1, // HDAC wakeup GS14,1, // USB wakeup GS15,1, // north module SERR# -} +} OperationRegion(GPIO, SystemIO, 0x0448, 0x4) Field(GPIO, ByteAcc, NoLock, Preserve) { @@ -154,7 +154,7 @@ ,1, GPI9,1, // ebook ,22, -} +} // PMIO_RX22/3 OperationRegion(\GPSE, SystemIO, 0x0422, 0x2) // Genernal Purpose SCI Enable @@ -174,7 +174,7 @@ HDA, 1, // HDA Enable USBE, 1, // USB Resume , 1, // NB SERR Detect -} +} // PMIO_RX28/9 OperationRegion(\Glos, SystemIO, 0x0428, 0x2) // Global Status @@ -187,7 +187,7 @@ SIRS, 1, // serirq status , 4, } - + OperationRegion(\WIRQ, SystemIO, 0x042a, 0x1) // IRQ Resume Reg Field(\WIRQ, ByteAcc, NoLock, Preserve) { IRQR, 8, @@ -209,7 +209,7 @@ OperationRegion(\Stus, SystemIO, 0x0430, 0x1) // Global Status Field(\Stus, ByteAcc, NoLock, Preserve) { PADS, 8, -} +} OperationRegion(\Prie, SystemIO, 0x0434, 0x1) Field(\Prie, ByteAcc, NoLock, Preserve) { @@ -227,17 +227,17 @@ UPUT (0x31) // 1 Notify(\_SB.PCI0.EC, 0x80) // GPWAKE, from the EC } - + Method(_L02) { UPUT (0x33) // 3 Notify(\_SB.PCI0.VT86.PS2K, 0x02) //Internal Keyboard PME Status } - + Method(_L04) { UPUT (0x34) // 4 Notify(\_SB.SLPB, 0x80) } - + Method(_L05) { UPUT (0x35) // 5 Notify(\_SB.PCI0,0x2) @@ -287,7 +287,7 @@ Notify(\_SB.PCI0.USB2, 0x00) Notify(\_SB.PCI0.USB3, 0x00) Notify(\_SB.PCI0.EHCI, 0x00) - + Store(One, SCIZ) If (LEqual (Arg0, 1)) //S1 @@ -353,7 +353,7 @@ IF (LEqual(Arg0, 0x03)) { // S3 Store(0x0,\_SB.PCI0.MEMC.FSEG) // Disable F Segment Read/Write - } + } IF (LEqual(Arg0, 0x04)) { //S4 } @@ -369,15 +369,15 @@ // If(LNotEqual(Sizeof(Arg0), Sizeof(Arg1))) { // Return(1) // } -// +// // Add(Sizeof(Arg0), 1, Local0) -// +// // Name(BUF0, Buffer(Local0) {}) // Name(BUF1, Buffer(Local0) {}) -// +// // Store(Arg0, BUF0) // Store(Arg1, BUF1) -// +// // While(Local0) { // Decrement(Local0) // If(LNotEqual(Derefof(Index(BUF0, Local0)), Derefof(Index(BUF1, Local0)))) { @@ -405,29 +405,29 @@ // Notify() calls to SLPB -- not sure what that will do. Name(_PRW, Package(2){0x04,5}) //Internal Keyboard Controller PME Status; S5 } - + Device(PCI0) { Name(_HID,EISAID ("PNP0A08")) // Indicates PCI Express host bridge hierarchy Name(_CID,EISAID ("PNP0A03")) // For legacy OS that doesn't understand the new HID - + Name(_ADR,0x00000000) // Device (HI WORD)=0, Func (LO WORD)=0 - + Name (_BBN,0) - + Method(_INI, 0) { UPUT (0x4a) // J } - + Name (_S3D, 3) - + Method(_STA, 0) { Return(0x0F) // present, enabled, functioning } - + Name(_PRW, Package(2){0x5,0x4}) // PME# - + Method(_CRS,0) { Name(BUF0,ResourceTemplate() { WORDBusNumber( // Bus 0 @@ -441,7 +441,7 @@ 0x0000, 0x0100 ) - + IO( // IO Resource for PCI Bus Decode16, 0x0CF8, @@ -449,7 +449,7 @@ 1, 8 ) - + WORDIO( // IO from 0x0000 - 0x0cf7 ResourceProducer, MinFixed, @@ -462,7 +462,7 @@ 0x0000, 0x0CF8 ) - + WORDIO( // IO from 0x0d00 - 0xffff ResourceProducer, MinFixed, @@ -475,7 +475,7 @@ 0x0000, 0xF300 ) - + DWORDMemory( ResourceProducer, PosDecode, @@ -489,7 +489,7 @@ 0x00000000, 0x00020000 ) - + DWORDMemory( ResourceProducer, PosDecode, @@ -505,12 +505,12 @@ ) // XXX I don't know what this is DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, - 0xFED40000, - 0xFED44FFF, - 0x00000000, - 0x00005000, - ) + 0x00000000, + 0xFED40000, + 0xFED44FFF, + 0x00000000, + 0x00005000, + ) DWORDMemory( // Consumed-and-produced resource(all of memory space) ResourceProducer, // bit 0 of general flags is 0 PosDecode, // positive Decode @@ -528,7 +528,7 @@ MEM3 // Name declaration for this descriptor ) }) // end of BUF0 - + CreateDWordField(BUF0,MEM3._MIN, PMRN) CreateDWordField(BUF0,MEM3._MAX, PMRM) CreateDWordField(BUF0,MEM3._LEN, PMRL) @@ -537,17 +537,17 @@ Store(\_SB.PCI0.MEMC.LTMA, Local0) ShiftLeft(Local0, 16, PMRN) Subtract (PMRM, PMRN, PMRL) - + Return(BUF0) } // end of CRS - + Device(MEMC) { Name(_ADR, 0x00000003) - + Method(_STA, 0) { Return(0x0F) // present, enabled, functioning } - + OperationRegion(MCPS,PCI_Config,0x00,0x100) Field(MCPS,ByteAcc,NoLock,Preserve) { @@ -567,25 +567,25 @@ Offset(0xA1), , 4, - FBSZ, 3, // Frame Buffer Size + FBSZ, 3, // Frame Buffer Size ENIG, 1, // Enable Internal Graphic } } - + // USBD Controller Device (USBD) { Name(_ADR, 0x000B0000) - + OperationRegion(RUDC,PCI_Config,0x00,0x100) Field(RUDC,ByteAcc,NoLock,Preserve){ - Offset(0x00), - VID, 16, - Offset(0x04), + Offset(0x00), + VID, 16, + Offset(0x04), CMDR, 3, } - - Method(_STA, 0) + + Method(_STA, 0) { If(LNotEqual(\_SB.PCI0.USBD.VID, 0x1106)) { Return(0x00) @@ -598,21 +598,21 @@ } } }//Device(USBD) - + // SDIO Controller Device (SDIO) { Name(_ADR, 0x000C0000) - + OperationRegion(RSDC,PCI_Config,0x00,0x100) Field(RSDC,ByteAcc,NoLock,Preserve){ - Offset(0x00), - VID, 16, - Offset(0x04), + Offset(0x00), + VID, 16, + Offset(0x04), CMDR, 3, } - - Method(_STA, 0) + + Method(_STA, 0) { If(LNotEqual(\_SB.PCI0.SDIO.VID, 0x1106)) { Return(0x00) @@ -625,21 +625,21 @@ } } }//Device(SDIO) - + // SD $ MS Controller Device (SDMS) { Name(_ADR, 0x000D0000) - + OperationRegion(RSDM,PCI_Config,0x00,0x100) Field(RSDM,ByteAcc,NoLock,Preserve){ - Offset(0x00), - VID, 16, - Offset(0x04), + Offset(0x00), + VID, 16, + Offset(0x04), CMDR, 3, } - - Method(_STA, 0) + + Method(_STA, 0) { If(LNotEqual(\_SB.PCI0.SDMS.VID, 0x1106)) { Return(0x00) @@ -652,21 +652,21 @@ } } }//Device(SDMS) - + // CE-ATA $ NF Controller(Card Boot) Device(CENF) { Name(_ADR, 0x000E0000) - + OperationRegion(RENF,PCI_Config,0x00,0x100) Field(RENF,ByteAcc,NoLock,Preserve){ - Offset(0x00), - VID, 16, - Offset(0x04), + Offset(0x00), + VID, 16, + Offset(0x04), CMDR, 3, } - - Method(_STA, 0) + + Method(_STA, 0) { If(LNotEqual(\_SB.PCI0.CENF.VID, 0x1106)) { Return(0x00) @@ -679,12 +679,12 @@ } } } - + Device(IDEC) { - + Name(_ADR, 0x000F0000) //D15F0: a Pata device - + Method(_STA,0,NotSerialized) //Status of the Pata Device { If(LNot(LEqual(\_SB.PCI0.IDEC.VID,0x1106))) @@ -711,19 +711,19 @@ CMDR,3, Offset(0x40), , 1, - EPCH, 1, // Enable Primary channel. + EPCH, 1, // Enable Primary channel. Offset(0x4A), PSPT, 8, // IDE Timings, Primary Slave - PMPT, 8, // IDE Timings, Primary Master + PMPT, 8, // IDE Timings, Primary Master Offset(0x52), PSUT, 4, // Primary Slave UDMA Timing PSCT, 1, // Primary Drive Slave Cabal Type PSUE, 3, // Primary Slave UDMA Enable PMUT, 4, // Primary Master UDMA Timing PMCT, 1, // Primary Drive Master Cabal Type - PMUE, 3, // Primary Master UDMA Enable + PMUE, 3, // Primary Master UDMA Enable } - + Name(REGF,0x01) //accessible OpRegion default Method(_REG,2,NotSerialized) // is PCI Config space accessible as OpRegion? { @@ -740,42 +740,42 @@ Package(){0x06,0x05,0x04,0x04,0x03,0x03,0x02,0x02,0x01,0x01,0x01,0x01,0x01,0x01,0x00} }) */ - Name(TIM0, Package() + Name(TIM0, Package() { // Primary / Secondary channels timings Package(){120, 180, 240, 383, 600}, // Timings in ns - Mode 4,3,2,1,0 defined from ATA spec. Package(){0x20, 0x22, 0x33, 0x47, 0x5D }, // PIO Timing - Mode 4,3,2,1,0 Package(){4, 3, 2, 1, 0}, // PIO mode (TIM0,0) Package(){2, 1, 0, 0}, // Multi-word DMA mode Package(){120, 80, 60, 45, 30, 20, 15}, // Min UDMA Timings in ns - Package(){6,5,4,4,3,3,2,2,1,1,1,1,1,1,0}, // UDMA mode - Package(){0x0E, 8, 6, 4, 2, 1, 0}, // UDMA timing - }) - + Package(){6,5,4,4,3,3,2,2,1,1,1,1,1,1,0}, // UDMA mode + Package(){0x0E, 8, 6, 4, 2, 1, 0}, // UDMA timing + }) + Name(TMD0,Buffer(0x14){}) CreateDwordField(TMD0,0x00,PIO0) CreateDwordField(TMD0,0x04,DMA0) CreateDwordField(TMD0,0x08,PIO1) CreateDwordField(TMD0,0x0C,DMA1) CreateDwordField(TMD0,0x10,CHNF) - + Name(GMPT, 0) // Master PIO Timings Name(GMUE, 0) // Master UDMA enable Name(GMUT, 0) // Master UDMA Timings Name(GSPT, 0) // Slave PIO Timings Name(GSUE, 0) // Slave UDMA enable Name(GSUT, 0) // Slave UDMA Timings - + Device(CHN0) //Primary Channel: Pata device { Name(_ADR,0x00) - + Method(_STA,0,NotSerialized) { - If(LNotEqual(\_SB.PCI0.IDEC.EPCH, 0x1)) + If(LNotEqual(\_SB.PCI0.IDEC.EPCH, 0x1)) { Return(0x00) //channel disable - } - Else + } + Else { Return(0x0F) //channel enable } @@ -785,7 +785,7 @@ Return(GTM(PMPT,PMUE,PMUT,PSPT,PSUE,PSUT)) } Method(_STM, 3) // Set Timing PIO/DMA Mode - { + { Store(Arg0, TMD0) // Copy Arg0 into TMD0 buffer Store(PMPT, GMPT) // Master PIO Timings Store(PMUE, GMUE) // Master UDMA enable @@ -801,7 +801,7 @@ Store(GSUE, PSUE) // Slave UDMA enable Store(GSUT, PSUT) // Slave UDMA Timings } // end Method _STM - + Device(DRV0) //Master Device { Name(_ADR,0x00) //0 indicates master drive @@ -819,7 +819,7 @@ } } } - + Method(GTM,6,Serialized) { Store(Ones,PIO0) //default value: all bits set to 1 @@ -839,11 +839,11 @@ { Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x00)),Local6)),Local7) Store(Local7,DMA0) - Store(Local7,PIO0) + Store(Local7,PIO0) } Store(Match(DeRefOf(Index(TIM0,0x01)),MEQ,Arg3,MTR,0x00,0x00),Local6) If(LLess(Local6,Ones)) - { + { Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x00)),Local6)),Local7) Store(Local7,DMA1) Store(Local7,PIO1) @@ -862,18 +862,18 @@ } Return(TMD0) //return timing mode } - + Method(STM, 0, Serialized) { - + If(REGF){} // PCI space not accessible Else { Return(TMD0) } - - Store(0x00, GMUE) // Master UDMA Disable - Store(0x00, GSUE) // Slave UDMA Disable - Store(0x07, GMUT) // Master UDMA Mode 0 - Store(0x07, GSUT) // Slave UDMA Mode 0 - + + Store(0x00, GMUE) // Master UDMA Disable + Store(0x00, GSUE) // Slave UDMA Disable + Store(0x07, GMUT) // Master UDMA Mode 0 + Store(0x07, GSUT) // Slave UDMA Mode 0 + If(And(CHNF, 0x1)) { Store(Match(DeRefOf(Index(TIM0, 4)), MLE, DMA0, MTR,0,0), Local0) // Get DMA mode @@ -883,20 +883,20 @@ Else // non - UDMA mode. Possible Multi word DMA { If(Or(LEqual(PIO0,Ones), LEqual(PIO0,0))) - { + { If(And(LLess(DMA0,Ones), LGreater(DMA0,0))) { Store(DMA0, PIO0) // Make PIO0=DMA0 - } + } } } - + If(And(CHNF, 0x4)) { Store(Match(DeRefOf(Index(TIM0, 4)), MLE, DMA1, MTR,0,0), Local0) Store(DeRefOf(Index(DeReFof(Index(TIM0, 6)), Local0)), GSUT) // Timing bit mask 66Mhz Or(GSUE, 0x07, GSUE) // Enable UltraDMA for Device 0 - } + } Else // non - UDMA mode. Possible Multi word DMA { If(Or(LEqual(PIO1, Ones), LEqual(PIO1,0))) @@ -907,17 +907,17 @@ } } } - + And(Match(DeRefOf(Index(TIM0, 0)), MGE, PIO0, MTR,0,0), 0x3, Local0) Store(DeRefOf(Index(DeReFof(Index(TIM0, 1)), Local0)), Local1) Store(Local1, GMPT) - + And(Match(DeRefOf(Index(TIM0, 0)), MGE, PIO1, MTR,0,0), 0x3, Local0) Store(DeRefOf(Index(DeReFof(Index(TIM0, 1)), Local0)), Local1) Store(Local1, GSPT) Return(TMD0) } // end Method STM - + Method(GTF , 4 , Serialized) { Store(Buffer(7){0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF}, Local1) @@ -927,39 +927,39 @@ CreateByteField(Local1, 5, PCHA) // master or slave CreateByteField(Local2, 5, UCHA) // master or slave And(Arg0,0x03,Local3) - - If(Lequal(And(Local3,0x01),0x01)) + + If(Lequal(And(Local3,0x01),0x01)) { Store(0xB0,PCHA) // drive 1 Store(0xB0,UCHA) // drive 1 } - + If(Arg1) { - Store(DeRefOf(Index(DeReFof(Index(TIM0, 5)), Arg2)), UMOD) //Programming DMA Mode - Or( UMOD, 0x40, UMOD) + Store(DeRefOf(Index(DeReFof(Index(TIM0, 5)), Arg2)), UMOD) //Programming DMA Mode + Or( UMOD, 0x40, UMOD) } - Else + Else { // non-UltraDMA Store(Match(DeRefOf(Index(TIM0, 1)), MEQ, Arg3, MTR,0,0), Local0) Or(0x20, DeRefOf(Index(DeReFof(Index(TIM0, 3)), Local0)), UMOD) } - + Store(Match(DeRefOf(Index(TIM0, 1)), MEQ, Arg3, MTR,0,0), Local0) Or(0x08, DeRefOf(Index(DeReFof(Index(TIM0, 2)), Local0)), Mode) Concatenate(Local1, Local2, Local6) Return(Local6) - + } // end of GTF } Device(USB1) { Name(_ADR,0x00100000) //Address+function. - + Name(_PRW, Package(2){0x0E,3}) - + Name(_S3D, 3) - + OperationRegion(U2F0,PCI_Config,0x00,0xC2) Field(U2F0,ByteAcc,NoLock,Preserve){ Offset(0x00), @@ -971,7 +971,7 @@ Offset(0x84), ECDX, 2 //USB1 PM capability status register } - + Method(_STA,0) { //Status of the USB1 Device If(LEqual(\_SB.PCI0.USB1.CMDR, 0x00)) { Return(0x0D) @@ -980,14 +980,14 @@ } } } - + Device(USB2) { Name(_ADR,0x00100001) //Address+function. - + Name(_PRW, Package(2){0x0E,3}) - + Name(_S3D, 3) - + OperationRegion(U2F1,PCI_Config,0x00,0xC2) Field(U2F1,ByteAcc,NoLock,Preserve){ Offset(0x00), @@ -999,7 +999,7 @@ Offset(0x84), ECDX, 2 //USB2 PM capability status register } - + Method(_STA,0) { //Status of the USB2 Device If(LEqual(\_SB.PCI0.USB2.CMDR, 0x00)) { Return(0x0D) @@ -1008,14 +1008,14 @@ } } } - + Device(USB3) { Name(_ADR,0x00100002) //Address+function. - + Name(_PRW, Package(2){0x0E,3}) - + Name(_S3D, 3) - + OperationRegion(U2F2,PCI_Config,0x00,0xC2) Field(U2F2,ByteAcc,NoLock,Preserve){ Offset(0x00), @@ -1027,7 +1027,7 @@ Offset(0x84), ECDX, 2 //USB3 PM capability status register } - + Method(_STA,0) { //Status of the USB3 Device If(LEqual(\_SB.PCI0.USB3.CMDR, 0x00)) { Return(0x0D) @@ -1036,14 +1036,14 @@ } } } - + Device(EHCI) { Name(_ADR,0x00100004) //Address+function. - + Name(_PRW, Package(2){0x0E,3}) - + Name(_S3D, 3) - + OperationRegion(U2F4,PCI_Config,0x00,0xC2) Field(U2F4,ByteAcc,NoLock,Preserve){ Offset(0x00), @@ -1055,16 +1055,16 @@ Offset(0x84), ECDX, 2 //EHCI1 PM capability status register } - + Method(_STA,0) { //Status of the EHCI1 Device If(LEqual(\_SB.PCI0.EHCI.CMDR, 0x00)) { Return(0x0D) } Else { Return(0x0F) - } + } } } - + Device (PEXX) { Name (_HID, EISAID ("PNP0C01")) @@ -1076,51 +1076,51 @@ } ) } - + Device(VT86) { Name(_ADR,0x00110000) //Address+function. - + OperationRegion(VTSB, PCI_Config, 0x00, 0x100) Field(\_SB.PCI0.VT86.VTSB,ByteAcc,NoLock,Preserve) { Offset(0x2), DEID, 16, // Device ID - + Offset(0x2C), ID2C,8, // RX2C ID2D,8, // RX2D ID2E,8, // RX2E ID2F,8, // RX2F - + Offset(0x44), PIRE, 4, PIRF, 4, - PIRG, 4, + PIRG, 4, PIRH, 4, // PIRQH# Routing - + Offset(0x46), POLE, 1, // INTE polarity POLF, 1, // INTF polarity - POLG, 1, // INTG polarity + POLG, 1, // INTG polarity POLH, 1, // INTH polarity ENR8, 1, // enable INTE~H routing by Rx44~Rx45. , 1, ECOM, 1, - + Offset(0x4E), , 3, EP74, 1, // Enable 74/75 Access CMOS , 4, - + Offset(0x50), , 1, ESB3, 1, // RX5001 EHCI1 - ESB2, 1, // RX5002 USB3 - EIDE, 1, // RX5003 EIDE - EUSB, 1, // RX5004 USB1 + ESB2, 1, // RX5002 USB3 + EIDE, 1, // RX5003 EIDE + EUSB, 1, // RX5004 USB1 ESB1, 1, // RX5005 USB2 USBD, 1, // RX5006 USB Device Mode controller - + Offset(0x51), EKBC, 1, // RX5100 Internal Keyboard controller KBCC, 1, // RX5101 Internal KBC Configuration @@ -1128,7 +1128,7 @@ ERTC, 1, // RX5103 Internal RTC SDIO, 1, // RX5104 enable SDIO controller , 2, - + Offset(0x55), , 4, PIRA, 4, // PCI IRQA @@ -1136,75 +1136,75 @@ PIRC, 4, // PCI IRQC , 4, PIRD, 4, // PCI IRQD - + Offset(0x58), , 6, ESIA, 1, // Enable Source Bridge IO APIC , 1, - + Offset(0x81), // Enable ACPI I/O , 7, ENIO, 1, - - Offset(0x88), + + Offset(0x88), , 7, IOBA, 9, // Power Management I/O Base - + Offset(0x94), , 5, - PLLD, 1, // RX9405 Internal PLL Reset During Suspend 0:Enable,1:Disable - - Offset(0xB0), + PLLD, 1, // RX9405 Internal PLL Reset During Suspend 0:Enable,1:Disable + + Offset(0xB0), , 4, EU1E, 1, // Embedded COM1 EU2E, 1, // Embedded COM2 , 2, - - Offset(0xB2), + + Offset(0xB2), UIQ1, 4, // UART1 IRQ - UIQ2, 4, // UART2 IRQ - - Offset(0xB4), - U1BA, 7, // UART1 I/O base address. + UIQ2, 4, // UART2 IRQ + + Offset(0xB4), + U1BA, 7, // UART1 I/O base address. , 1, - U2BA, 7, // UART2 I/O base address. + U2BA, 7, // UART2 I/O base address. , 1, - - Offset(0xB7), + + Offset(0xB7), , 3, UDFE, 1, // UART DMA Funtion Enable - + Offset(0xB8), , 2, DIBA, 14, // UART DMA I/O Base Address - + Offset(0xBC), - SPIB, 24, - + SPIB, 24, + Offset(0xD0), , 4, SMBA, 12, // SMBus I/O Base (16-byte I/O space) - + Offset(0xD2), - ENSM, 1, // Enable SMBus IO + ENSM, 1, // Enable SMBus IO , 7, - + Offset(0xF6), REBD, 8, //Internal Revision ID } - + Device(APCM) // APIC MMIO { Name(_HID, EISAID("PNP0C02")) // Hardware Device ID, Motherboard Resources Name(_UID, 0x1100) - + Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xFEE00000, 0x00001000) // Local APIC Memory32Fixed(ReadWrite, 0xFEC00000, 0x00001000) // IO APIC }) } - + Device(PS2M) //PS2 Mouse { Name(_HID,EISAID("PNP0F13")) @@ -1212,14 +1212,14 @@ Name(_CRS, ResourceTemplate () { IRQNoFlags () {12} }) Name(_PRW, Package() {0x09, 0x04}) } - + Device(PS2K) // PS2 Keyboard - { + { Name(_HID,EISAID("PNP0303")) Name(_CID,EISAID("PNP030B")) // Microsoft reserved PNP ID - + Name(_STA,0x0) // not present: not used on XO - + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x0060, 0x0060, 0x01, 0x01, ) @@ -1227,12 +1227,12 @@ IRQNoFlags () {1} }) Name(_PRW, Package() {0x02, 0x04}) - } - + } + Device(DMAC) { - Name(_HID, EISAID("PNP0200")) - + Name(_HID, EISAID("PNP0200")) + Name(_CRS,ResourceTemplate() { IO(Decode16, 0x00, 0x00, 0, 0x10) // Master DMA Controller IO(Decode16, 0x81, 0x81, 0, 0x03) // DMA Page Registers @@ -1243,11 +1243,11 @@ DMA(Compatibility,NotBusMaster,Transfer8) {4} // Cascade channel }) } - + Device(RTC) { Name(_HID,EISAID("PNP0B00")) - + Name(_CRS,ResourceTemplate() { IO(Decode16, 0x70, 0x70, 0x00, 0x02) @@ -1255,7 +1255,7 @@ IRQNoFlags() {8} }) } - + Device(PIC) { Name(_HID,EISAID("PNP0000")) @@ -1264,7 +1264,7 @@ IO(Decode16,0xA0,0xA0,0x00,0x02) }) } - + Device(FPU) { Name(_HID,EISAID("PNP0C04")) @@ -1273,18 +1273,18 @@ IRQNoFlags(){13} }) } - + Device(TMR) { Name(_HID,EISAID("PNP0100")) - + Name(_CRS, ResourceTemplate() { IO(Decode16,0x40,0x40,0x00,0x04) IRQNoFlags() {0} }) } - + Device(SPKR) // System Speaker { Name(_HID,EISAID("PNP0800")) @@ -1292,50 +1292,50 @@ IO(Decode16,0x61,0x61,0x01,0x01) }) } - + Name (ICRS, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) // The flags is the value of Byte 3 of IRQ Description Definition { } // The value decides the value of Byte 1 and byte 2 of IRQ Description Definition }) - + Name(PRSA, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) {3, 4, 5, 6, 7, 10, 11, 12, 14, 15} }) - + Device(LNKA) { Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link Name(_UID, 1) Method(_STA, 0) { - If(LEqual(\_SB.PCI0.VT86.PIRA, 0x00)) + If(LEqual(\_SB.PCI0.VT86.PIRA, 0x00)) { Return(0x09) // disabled } Else { Return(0x0B) // enabled, but no UI } } - - Method(_PRS) + + Method(_PRS) { Return(PRSA) } - - Method(_DIS) + + Method(_DIS) { Store(0x0, \_SB.PCI0.VT86.PIRA) } - - Method(_CRS) + + Method(_CRS) { CreateWordField (ICRS, 1, IRA0) Store (1, Local1) ShiftLeft (Local1, \_SB.PCI0.VT86.PIRA, IRA0) Return (ICRS) } - + Method(_SRS, 1) { CreateWordField (Arg0, 1, IRA) // Byte 1 and Byte 2 in the IRQ Descriptor Definition FindSetRightBit (IRA, Local0) @@ -1343,38 +1343,38 @@ Store (Local0, \_SB.PCI0.VT86.PIRA) } } - + Device(LNKB) { Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link Name(_UID, 2) Method(_STA, 0) { - If(LEqual(\_SB.PCI0.VT86.PIRB, 0x00)) + If(LEqual(\_SB.PCI0.VT86.PIRB, 0x00)) { Return(0x09) // disabled } Else { Return(0x0B) // enabled, but no UI } } - - Method(_PRS) + + Method(_PRS) { Return(PRSA) } - - Method(_DIS) + + Method(_DIS) { Store(0x0, \_SB.PCI0.VT86.PIRB) } - - Method(_CRS) + + Method(_CRS) { CreateWordField (ICRS, 1, IRA0) Store (1, Local1) ShiftLeft (Local1, \_SB.PCI0.VT86.PIRB, IRA0) Return (ICRS) } - + Method(_SRS, 1) { CreateWordField (Arg0, 1, IRA) // Byte 1 and Byte 2 in the IRQ Descriptor Definition FindSetRightBit (IRA, Local0) @@ -1382,39 +1382,39 @@ Store (Local0, \_SB.PCI0.VT86.PIRB) } } - - + + Device(LNKC) { Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link Name(_UID, 3) Method(_STA, 0) { - If(LEqual(\_SB.PCI0.VT86.PIRC, 0x00)) + If(LEqual(\_SB.PCI0.VT86.PIRC, 0x00)) { Return(0x09) // disabled } Else { Return(0x0B) // enabled, but no UI } } - - Method(_PRS) + + Method(_PRS) { Return(PRSA) } - - Method(_DIS) + + Method(_DIS) { Store(0x0, \_SB.PCI0.VT86.PIRC) } - - Method(_CRS) + + Method(_CRS) { CreateWordField (ICRS, 1, IRA0) Store (1, Local1) ShiftLeft (Local1, \_SB.PCI0.VT86.PIRC, IRA0) Return (ICRS) } - + Method(_SRS, 1) { CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition FindSetRightBit (IRA, Local0) @@ -1422,38 +1422,38 @@ Store (Local0, \_SB.PCI0.VT86.PIRC) } } - + Device(LNKD) { Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link Name(_UID, 4) Method(_STA, 0) { - If(LEqual(\_SB.PCI0.VT86.PIRD, 0x00)) + If(LEqual(\_SB.PCI0.VT86.PIRD, 0x00)) { Return(0x09) // disabled } Else { Return(0x0B) // enabled, but no UI } } - - Method(_PRS) + + Method(_PRS) { Return(PRSA) } - - Method(_DIS) + + Method(_DIS) { Store(0x0, \_SB.PCI0.VT86.PIRD) } - - Method(_CRS) + + Method(_CRS) { CreateWordField (ICRS, 1, IRA0) Store (1, Local1) ShiftLeft (Local1, \_SB.PCI0.VT86.PIRD, IRA0) Return (ICRS) } - + Method(_SRS, 1) { CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition FindSetRightBit (IRA, Local0) @@ -1461,176 +1461,176 @@ Store (Local0, \_SB.PCI0.VT86.PIRD) } } - + Device(LNKE) { Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link Name(_UID, 5) Method(_STA, 0) { - If(LEqual(\_SB.PCI0.VT86.PIRE, 0x00)) + If(LEqual(\_SB.PCI0.VT86.PIRE, 0x00)) { Return(0x09) // disabled } Else { Return(0x0B) // enabled, but no UI } } - - Method(_PRS) + + Method(_PRS) { Return(PRSA) } - - Method(_DIS) + + Method(_DIS) { Store(0x0, \_SB.PCI0.VT86.PIRE) } - - Method(_CRS) + + Method(_CRS) { CreateWordField (ICRS, 1, IRA0) Store (1, Local1) ShiftLeft (Local1, \_SB.PCI0.VT86.PIRE, IRA0) Return (ICRS) } - + Method(_SRS, 1) { CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition FindSetRightBit (IRA, Local0) Decrement (Local0) Store (Local0, \_SB.PCI0.VT86.PIRE) Store(One,ENR8) - Store(Zero,POLE) + Store(Zero,POLE) } } - + Device(LNKF) { Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link Name(_UID, 6) Method(_STA, 0) { - If(LEqual(\_SB.PCI0.VT86.PIRF, 0x00)) + If(LEqual(\_SB.PCI0.VT86.PIRF, 0x00)) { Return(0x09) // disabled } Else { Return(0x0B) // enabled, but no UI } } - - Method(_PRS) + + Method(_PRS) { Return(PRSA) } - - Method(_DIS) + + Method(_DIS) { Store(0x0, \_SB.PCI0.VT86.PIRF) } - - Method(_CRS) + + Method(_CRS) { CreateWordField (ICRS, 1, IRA0) Store (1, Local1) ShiftLeft (Local1, \_SB.PCI0.VT86.PIRF, IRA0) Return (ICRS) } - + Method(_SRS, 1) { CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition FindSetRightBit (IRA, Local0) Decrement (Local0) Store (Local0, \_SB.PCI0.VT86.PIRF) Store(One,ENR8) - Store(Zero,POLF) + Store(Zero,POLF) } } - + Device(LNK0) { Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link Name(_UID, 7) Method(_STA, 0) { - If(LEqual(\_SB.PCI0.VT86.PIRG, 0x00)) + If(LEqual(\_SB.PCI0.VT86.PIRG, 0x00)) { Return(0x09) // disabled } Else { Return(0x0B) // enabled, but no UI } } - - Method(_PRS) + + Method(_PRS) { Return(PRSA) } - - Method(_DIS) + + Method(_DIS) { Store(0x0, \_SB.PCI0.VT86.PIRG) } - - Method(_CRS) + + Method(_CRS) { CreateWordField (ICRS, 1, IRA0) Store (1, Local1) ShiftLeft (Local1, \_SB.PCI0.VT86.PIRG, IRA0) Return (ICRS) } - + Method(_SRS, 1) { CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition FindSetRightBit (IRA, Local0) Decrement (Local0) Store (Local0, \_SB.PCI0.VT86.PIRG) Store(One,ENR8) - Store(Zero,POLG) + Store(Zero,POLG) } } - + Device(LNK1) { Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link Name(_UID, 8) Method(_STA, 0) { - If(LEqual(\_SB.PCI0.VT86.PIRH, 0x00)) + If(LEqual(\_SB.PCI0.VT86.PIRH, 0x00)) { Return(0x09) // disabled } Else { Return(0x0B) // enabled, but no UI } } - - Method(_PRS) + + Method(_PRS) { Return(PRSA) } - - Method(_DIS) + + Method(_DIS) { Store(0x0, \_SB.PCI0.VT86.PIRH) } - - Method(_CRS) + + Method(_CRS) { CreateWordField (ICRS, 1, IRA0) Store (1, Local1) ShiftLeft (Local1, \_SB.PCI0.VT86.PIRH, IRA0) Return (ICRS) } - + Method(_SRS, 1) { CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition FindSetRightBit (IRA, Local0) Decrement (Local0) Store (Local0, \_SB.PCI0.VT86.PIRH) Store(One,ENR8) - Store(Zero,POLH) + Store(Zero,POLH) } } - + Mutex (MUEC, 0x00) OperationRegion (ECCP, SystemIO, 0x068, 0x05) - + // NB -- the EC routines all return 0 for failure - + Field (ECCP, ByteAcc, NoLock, Preserve) { ECDA, 8, // 0x68 @@ -1639,7 +1639,7 @@ , 8, ECCM, 8, // 0x6c } - + // force clear OBF by reading/discarding 0x68 Method (OBFZ, 0, Serialized) { @@ -1651,7 +1651,7 @@ } Return (LNotEqual (Local0, Zero)) } - + // wait for IBF == 0 Method (IBFZ, 0, Serialized) { @@ -1662,7 +1662,7 @@ } Return (LNotEqual (Local0, Zero)) } - + // wait for IBF == 1 Method (IBFN, 0, Serialized) { @@ -1673,7 +1673,7 @@ } Return (LNotEqual (Local0, Zero)) } - + // wait for OBF == 1 Method (OBFN, 0, Serialized) { @@ -1686,14 +1686,14 @@ } Return (LNotEqual (Local0, Zero)) } - + // EC read byte helper Method (ECRB, 0, NotSerialized) { if (OBFN ()) { Return(ECDA) } Return (Ones) } - + // EC command helper Method (ECWC, 1, NotSerialized) { @@ -1712,12 +1712,12 @@ } Return(Zero) } - + // EC command (zero args) Method (ECW0, 2, NotSerialized) { If (Acquire (MUEC, 0xFFFF)) { Return (One) } - + if (ECWC (Arg0)) { Release(MUEC) Return(One) @@ -1726,12 +1726,12 @@ Release(MUEC) Return (Zero) } - + // EC command - 1 arg Method (ECW1, 2, NotSerialized) { If (Acquire (MUEC, 0xFFFF)) { Return (One) } - + if (ECWC (Arg0)) { if (IBFZ ()) { UPUT (0x2b) // + @@ -1745,12 +1745,12 @@ Release(MUEC) Return (Zero) } - + // EC command - 2 args Method (ECW2, 3, NotSerialized) { If (Acquire (MUEC, 0xFFFF)) { Return (One) } - + if (ECWC (Arg0)) { if (IBFZ ()) { UPUT (0x2b) // + @@ -1769,14 +1769,14 @@ Release(MUEC) Return (Zero) } - + // EC command - no arg, 1 return byte Method (ECR1, 1, NotSerialized) { - + If (Acquire (MUEC, 0xFFFF)) { Return (One) } // UPUT (0x4c) // L - + If (ECWC (Arg0)) { // UPUT (0x31) Store (10, Local0) // Ten retries @@ -1797,14 +1797,14 @@ Release(MUEC) Return (Ones) } - + // EC command - one arg, one return byte Method (ECWR, 2, NotSerialized) { Store (10, Local0) // Ten retries - + If (Acquire (MUEC, 0xFFFF)) { Return (One) } - + If (ECWC (Arg0)) { if (IBFZ ()) { UPUT (0x2b) // + @@ -1833,7 +1833,7 @@ Device (AC) { /* AC adapter */ Name (_HID, "ACPI0003") Name (_PCL, Package (0x01) { _SB }) // Power consumer list - points to main system bus - + Method (_PSR, 0, NotSerialized) { If (LNot (Acquire (ACMX, 5000))) @@ -1843,7 +1843,7 @@ Store (ECR1 (0x15), Local0) // CMD_READ_BATTERY_STATUS Release (ACMX) } - + // If (And (Local0, One)) If (And (Local0, 0x10)) { @@ -1852,10 +1852,10 @@ Return (Zero) } } - + Name (_STA, 0x0F) } - + Name (BIFP, Package (0x0D) // Battery info (static) p 342 { One, // Power units - 1 : mAh / mA @@ -1880,7 +1880,7 @@ 2910, // remaining capacity 23306 // voltage in mV }) - + Device (BATT) { Name (_HID, EisaId ("PNP0C0A")) Name (_UID, One) @@ -1891,7 +1891,7 @@ Method (_STA, 0, NotSerialized) // Battery Status { - + If (LNot (Acquire (ACMX, 5000))) { UPUT (0x73) // s @@ -1899,7 +1899,7 @@ Store (ECR1 (0x15), Local0) // CMD_READ_BATTERY_STATUS Release (ACMX) } - + If (And (Local0, One)) // ECRD(0xfaa4) & 0x01 => Battery inserted { Return (0x1F) @@ -1971,13 +1971,13 @@ } } UPUT (0x49) // I - + Release (ACMX) } - + Return (BIFP) } - + Method (_BST, 0, NotSerialized) { If (LNot (Acquire (ACMX, 5000))) @@ -1989,11 +1989,11 @@ { Store (0x02, Local1) // charging } - ElseIf (And (Local0, 0x40)) // + ElseIf (And (Local0, 0x40)) // { Store (One, Local1) // discharging } - + Sleep (15) // Store (ECRD (0xF910), Local0) Store (ECR1 (0x16), Local0) // CMD_READ_SOC @@ -2001,10 +2001,10 @@ { Or (Local1, 4, Local1) // critical } - + Store (Local1, Index (BSTP, Zero)) Sleep (15) - + // Switch (ECRD (0xFB5F)) Switch (ECR1 (0x2c)) // CMD_READ_BATTERY_TYPE { @@ -2024,21 +2024,21 @@ Multiply (Local0, 28, Local2) } } - + Store (Local2, Index (BSTP, 2)) Release (ACMX) } - + Return (BSTP) } } - + Device(RMSC) { // all "PNP0C02" devices- pieces that don't fit anywhere else Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices Name (_UID, 0x13) - + Name(CRS,ResourceTemplate(){ - + IO(Decode16,0x10,0x10,0x00,0x10) IO(Decode16,0x22,0x22,0x00,0x1E) IO(Decode16,0x44,0x44,0x00,0x1C) @@ -2056,7 +2056,7 @@ IO(Decode16,0xA2,0xA2,0x00,0x1E) IO(Decode16,0xE0,0xE0,0x00,0x10) IO(Decode16,0x3E0,0x3E0,0x00,0x8) - + // Reserve 4D0 and 4D1 for IRQ edge/level control port IO(Decode16, 0x4D0,0x4D0,0x00,0x2) // ACPI IO base address allocation @@ -2064,9 +2064,9 @@ // SMBus I/O space if applicable IO(Decode16, 0, 0, 0, 0, IO1) // SPI Memory Map IO Base - Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, MEM0) + Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, MEM0) }) - + Method(_CRS, 0) { If(LEqual(\_SB.PCI0.VT86.ENIO, 0x01)) // If we should privide the DSDT, ACPI IO must be enabled. @@ -2080,7 +2080,7 @@ Store(Local0, MAX0) Store(0x80, LEN0) } - + If(LEqual(\_SB.PCI0.VT86.ENSM, 0x01)) { CreateWordField(CRS, ^IO1._MIN, MIN1) @@ -2092,7 +2092,7 @@ Store(Local0, MAX1) Store(0x10, LEN1) // Length: 16 Byte } - + If(LNotEqual(\_SB.PCI0.VT86.SPIB, 0x00)) { CreateDWordField(CRS, ^MEM0._BAS, BAS2) @@ -2102,47 +2102,47 @@ Store(Local0, BAS2) Store(0x100, LEN2) } - + Return(CRS) } } - + } // End of (VT86) - - Name(PICM, Package(){ + + Name(PICM, Package(){ // VIA VGA Device(Integrated Graphics Device) Package(){0x0001ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // VGA, INTA - + //PCI Slot 1 Package(){0x0008ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTA Package(){0x0008ffff, 1, \_SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTB Package(){0x0008ffff, 2, \_SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTC Package(){0x0008ffff, 3, \_SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTD - + //PCI Slot 2 Package(){0x0009ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTA Package(){0x0009ffff, 1, \_SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTB Package(){0x0009ffff, 2, \_SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTC Package(){0x0009ffff, 3, \_SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTD - + //PCI Slot 3 Package(){0x000Affff, 0, \_SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTA Package(){0x000Affff, 1, \_SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTB Package(){0x000Affff, 2, \_SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTC Package(){0x000Affff, 3, \_SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTD - + // USB Device Controller Package(){0x000Bffff, 0, \_SB.PCI0.VT86.LNKA, 0}, - + // SDIO Controller Package(){0x000cffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // SD $ MS Controller Package(){0x000dffff, 0, \_SB.PCI0.VT86.LNKB, 0}, // CE-ATA $ NF Controller(Card Boot) Package(){0x000effff, 0, \_SB.PCI0.VT86.LNKC, 0}, - // VIA VX800 IDE + // VIA VX800 IDE Package(){0x000fffff, 0, \_SB.PCI0.VT86.LNKB, 0}, - + // VIA UHCI USB1 Device Package(){0x0010ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // VIA UHCI USB2 Device @@ -2151,45 +2151,45 @@ Package(){0x0010ffff, 2, \_SB.PCI0.VT86.LNKC, 0}, // VIA EHCI USB 2.0 Device Package(){0x0010ffff, 3, \_SB.PCI0.VT86.LNKD, 0}, - - // SB HDAC(Azalia) Audio + + // SB HDAC(Azalia) Audio Package(){0x0014ffff, 0, \_SB.PCI0.VT86.LNKA, 0}, // HD Audio, INTA }) - + Name(APIC, Package(){ // VIA VGA Device(Integrated Graphics Device) Package(){0x0001ffff, 0, 0, 0x10}, - + //PCI Slot 1 Package(){0x0008ffff, 0, 0, 0x10}, Package(){0x0008ffff, 1, 0, 0x10}, Package(){0x0008ffff, 2, 0, 0x10}, Package(){0x0008ffff, 3, 0, 0x10}, - + //PCI Slot 2 Package(){0x0009ffff, 0, 0, 0x10}, Package(){0x0009ffff, 1, 0, 0x10}, Package(){0x0009ffff, 2, 0, 0x10}, Package(){0x0009ffff, 3, 0, 0x10}, - + //PCI Slot 3 Package(){0x000Affff, 0, 0, 0x10}, Package(){0x000Affff, 1, 0, 0x10}, Package(){0x000Affff, 2, 0, 0x10}, Package(){0x000Affff, 3, 0, 0x10}, - + // USB Device Controller Package(){0x000Bffff, 0, 0, 0x13}, // USBD, INTA - + // SDIO Controller Package(){0x000cffff, 0, 0, 0x16}, // SDIO, INTA // SD $ MS Controller Package(){0x000dffff, 0, 0, 0x17}, // Card Reader, INTA // CE-ATA $ NF Controller(Card Boot) Package(){0x000effff, 0, 0, 0x14}, // Card Boot(NAND Flash), INTA - // VIA VX800 IDE + // VIA VX800 IDE Package(){0x000fffff, 0, 0, 0x15}, //IDE, INTA - + // VIA UHCI USB1 Device Package(){0x0010ffff, 0, 0, 0x14}, // VIA UHCI USB2 Device @@ -2198,44 +2198,44 @@ Package(){0x0010ffff, 2, 0, 0x15}, // VIA EHCI USB 2.0 Device Package(){0x0010ffff, 3, 0, 0x17}, - + // SB HDAC(Azalia) Audio Package(){0x0014ffff, 0, 0, 0x11}, //HD Audio , INTA - + }) // end of APIX - + Method(_PRT, 0, NotSerialized) { If(LNot(PICF)) { //PIC - Return(PICM) + Return(PICM) } Else { //APIC - Return(APIC) + Return(APIC) } } Device(P2PB) { - Name (_ADR, 0x00130000) - + Name (_ADR, 0x00130000) + OperationRegion(RP2P,PCI_Config,0x00,0x100) Field(RP2P,ByteAcc,NoLock,Preserve){ - Offset(0x00), - VID, 16, - Offset(0x04), + Offset(0x00), + VID, 16, + Offset(0x04), CMDR, 3, Offset(0x19), BUS1, 8, } - - Method(_BBN,0) + + Method(_BBN,0) { Return(BUS1) } - - Method(_STA, 0) + + Method(_STA, 0) { If(LNotEqual(\_SB.PCI0.P2PB.VID, 0x1106)) { Return(0x00) @@ -2247,61 +2247,61 @@ } } } - + Name(PIC4, Package(){ Package(){0x0003ffff, 0,\_SB.PCI0.VT86.LNKA , 0}, Package(){0x0003ffff, 1,\_SB.PCI0.VT86.LNKA , 0}, Package(){0x0003ffff, 2,\_SB.PCI0.VT86.LNKA , 0}, Package(){0x0003ffff, 3,\_SB.PCI0.VT86.LNKA , 0}, - + Package(){0x0004ffff, 0,\_SB.PCI0.VT86.LNKA , 0}, Package(){0x0004ffff, 1,\_SB.PCI0.VT86.LNKA , 0}, Package(){0x0004ffff, 2,\_SB.PCI0.VT86.LNKA , 0}, Package(){0x0004ffff, 3,\_SB.PCI0.VT86.LNKA , 0}, - + Package(){0x0005ffff, 0,\_SB.PCI0.VT86.LNKA , 0}, Package(){0x0005ffff, 1,\_SB.PCI0.VT86.LNKA , 0}, Package(){0x0005ffff, 2,\_SB.PCI0.VT86.LNKA , 0}, - Package(){0x0005ffff, 3,\_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0005ffff, 3,\_SB.PCI0.VT86.LNKA , 0}, }) - + Name(API4, Package(){ Package(){0x0003ffff, 0, 0, 0x10}, Package(){0x0003ffff, 1, 0, 0x10}, Package(){0x0003ffff, 2, 0, 0x10}, Package(){0x0003ffff, 3, 0, 0x10}, - + Package(){0x0004ffff, 0, 0, 0x10}, Package(){0x0004ffff, 1, 0, 0x10}, Package(){0x0004ffff, 2, 0, 0x10}, Package(){0x0004ffff, 3, 0, 0x10}, - + Package(){0x0005ffff, 0, 0, 0x10}, Package(){0x0005ffff, 1, 0, 0x10}, Package(){0x0005ffff, 2, 0, 0x10}, Package(){0x0005ffff, 3, 0, 0x10}, }) - + Method(_PRT, 0x0, NotSerialized) { If(LNot(PICF)) - { - Return(PIC4) + { + Return(PIC4) } Else { Return(API4) } } - + Method(_PRW, 0x00, NotSerialized) { Return(Package(){0x05,4}) //PME# - } + } Device(P4D3) { Name(_ADR, 0x00030000) } } // Device(P2PB) - + Device (EC) { Name (_PRW, Package (0x02) { 0x01, 0x04 }) // Event 01, wakes from S4 @@ -2330,7 +2330,7 @@ UPUT (0x45) // E } If (LNotEqual(GPI9, TPOL)) { - Store (GPI9, TPOL) // (re)init edge detect + Store (GPI9, TPOL) // (re)init edge detect } Return(GPI9) } @@ -2354,7 +2354,7 @@ } If (LNotEqual(GPI7, LPOL)) { - Store (GPI7, LPOL) // (re)init edge detect + Store (GPI7, LPOL) // (re)init edge detect } Return(GPI7) @@ -2365,16 +2365,16 @@ Device(HDAC) { Name(_ADR, 0x00140000) - + OperationRegion(RHDA,PCI_Config,0x00,0x100) Field(RHDA,ByteAcc,NoLock,Preserve){ - Offset(0x00), - VID, 16, - Offset(0x04), + Offset(0x00), + VID, 16, + Offset(0x04), CMDR, 3, } - - Method(_STA, 0) + + Method(_STA, 0) { If(LNotEqual(\_SB.PCI0.HDAC.VID, 0x1106)) { Return(0x00) @@ -2386,22 +2386,22 @@ } } } - + Method(_PRW) { Return (Package(){0xD, 4}) } }//Device(HDAC) - + } // Device(PCI0) - + //----------------------------------------------------------------------- // System board extension Device node for ACPI BIOS //----------------------------------------------------------------------- /* - + Procedure: RMEM - + Description: System board extension Device node for ACPI BIOS Place the device under \_SB scope, As per Msft the MEM Device is used to reserve Resources that are decoded out of PCI Bus @@ -2418,13 +2418,13 @@ by the device; Win2000 never use such ROM regions for its devices. Therefore there can be different approach used for different OSes in reservation unclaimed memory in "SYSM" Device node. is forwarded to PCI Bus - + Input: Nothing - + Output: _CRS buffer - + **************************************************************************/ - + Device(RMEM) { Name(_HID, EISAID("PNP0C01")) // Hardware Device ID, System Board Name(_UID, 1) @@ -2439,7 +2439,7 @@ // Base Address 1M - Top of system present memory Memory32Fixed(ReadWrite,0x100000,0x00000, RAM3) //Writeable }) - + Method (_CRS, 0) { CreateDWordField(CRS, ^RAM1._BAS, BAS1) @@ -2447,7 +2447,7 @@ CreateDWordField(CRS, ^RAM2._BAS, BAS2) CreateDWordField(CRS, ^RAM2._LEN, LEN2) CreateDWordField(CRS, ^RAM3._LEN, LEN3) - + //RAM3 Store(\_SB.PCI0.MEMC.LTMA, Local0) ShiftLeft(Local0, 0x10, Local2) @@ -2467,10 +2467,10 @@ Subtract(Local2, Local5, Local2) // Subtract Top SM RAM Size } Subtract(Local2, 0x100000, LEN3) - + Return(CRS) } } - + }//Scope(\_SB) }

1 0

r1456 - cpu/x86/pc/olpc/via
by svn＠openfirmware.info 03 Nov '09

03 Nov '09

Author: wmb Date: 2009-11-03 23:10:14 +0100 (Tue, 03 Nov 2009) New Revision: 1456 Modified: cpu/x86/pc/olpc/via/dsdt.dsl Log: OLPC Via - DSDT fix from Paul Fox: Change lid wakeup behavior so we only wake on lid open. (Later this behavior will be selectable.) Modified: cpu/x86/pc/olpc/via/dsdt.dsl =================================================================== --- cpu/x86/pc/olpc/via/dsdt.dsl 2009-11-03 01:11:15 UTC (rev 1455) +++ cpu/x86/pc/olpc/via/dsdt.dsl 2009-11-03 22:10:14 UTC (rev 1456) @@ -35,6 +35,9 @@ // set to 1 to enable debug output Name (UDBG, 0) +// set to 1 to enable LID wakeups on both open/close +Name (LIDX, 0) + Field (UART, ByteAcc, NoLock, Preserve) { UDAT, 8, @@ -147,9 +150,9 @@ OperationRegion(GPIO, SystemIO, 0x0448, 0x4) Field(GPIO, ByteAcc, NoLock, Preserve) { ,7, - GPI7,1, + GPI7,1, // lid ,1, - GPI9,1, + GPI9,1, // ebook ,22, } @@ -254,7 +257,7 @@ Method(_L0B) { // LID event UPUT (0x66) // f - Not(LPOL, LPOL) // Flip the lid polarity bit + Store (GPI7, LPOL) // set edge detect from current lid state Notify(\_SB.PCI0.LID, 0x80) } @@ -316,6 +319,10 @@ Or (Arg0, 0xB0, Local0) Store (Local0, DBG1) //80 Port: B1, B2, B3.... + + // always want to hear both lid events when awake + Store (GPI7, LPOL) // watch either edge + Return (0) } @@ -327,6 +334,9 @@ Or (Arg0, 0xF0, Local0) Store (Local0, DBG1) //80 Port: F1, F2, F3.... + // if (LIDX == 0), wake on rising edge only, else watch either + Store (And(LIDX, GPI7), LPOL) + IF (LEqual(Arg0, 0x01)) // S1 { While(PRII) @@ -2314,13 +2324,15 @@ } Method(EBK) { - If (TPOL) { - // non-zero means waiting for fall, so switch is open + If (GPI9) { // non-zero --> switch is open UPUT (0x65) // e } Else { UPUT (0x45) // E } - Return(TPOL) + If (LNotEqual(GPI9, TPOL)) { + Store (GPI9, TPOL) // (re)init edge detect + } + Return(GPI9) } } // Device(EBK) @@ -2335,13 +2347,17 @@ Method(_LID) { - If (LPOL) { - // non-zero means waiting for fall, so switch is open + If (GPI7) { // non-zero --> switch (and lid) is open UPUT (0x6c) // l } Else { UPUT (0x4c) // L } - Return(LPOL) + + If (LNotEqual(GPI7, LPOL)) { + Store (GPI7, LPOL) // (re)init edge detect + } + + Return(GPI7) } } // Device(LID)

1 0

r1455 - cpu/x86/pc/olpc cpu/x86/pc/olpc/via dev/hdaudio ofw/core
by svn＠openfirmware.info 03 Nov '09

03 Nov '09

Author: wmb Date: 2009-11-03 02:11:15 +0100 (Tue, 03 Nov 2009) New Revision: 1455 Modified: cpu/x86/pc/olpc/sound.fth cpu/x86/pc/olpc/via/fw.bth dev/hdaudio/core.fth ofw/core/ofwcore.fth Log: OLPC trac 9589 - Fixed several cases where the startup sound would be left playing instead of automatically turning off after one play of the sound. At the same time, I prevented the frame key from interrupting the early startup, which could lead to the display not working right. The startup sound now stops abruptly when you go to the ok prompt. That is intentional. Modified: cpu/x86/pc/olpc/sound.fth =================================================================== --- cpu/x86/pc/olpc/sound.fth 2009-11-03 01:07:21 UTC (rev 1454) +++ cpu/x86/pc/olpc/sound.fth 2009-11-03 01:11:15 UTC (rev 1455) @@ -40,6 +40,9 @@ : sound-end ( -- ) " wait-sound" ['] $call-audio catch if 2drop then ; +: stop-sound ( -- ) + " stop-sound" ['] $call-audio catch if 2drop then +; \ LICENSE_BEGIN \ Copyright (c) 2006 FirmWorks Modified: cpu/x86/pc/olpc/via/fw.bth =================================================================== --- cpu/x86/pc/olpc/via/fw.bth 2009-11-03 01:07:21 UTC (rev 1454) +++ cpu/x86/pc/olpc/via/fw.bth 2009-11-03 01:11:15 UTC (rev 1455) @@ -550,7 +550,6 @@ cursor-off true to text-on? - " //null" open-dev to null-ih \ For text-off state ?gui-banner @@ -639,6 +638,7 @@ ?factory-mode ?factory-boot-sequence + disable-user-aborts console-start board-revision 0= if @@ -687,6 +687,8 @@ blue-letters ." Type 'help' for more information." black-letters cr cr + enable-user-aborts + stop-sound quit ; Modified: dev/hdaudio/core.fth =================================================================== --- dev/hdaudio/core.fth 2009-11-03 01:07:21 UTC (rev 1454) +++ dev/hdaudio/core.fth 2009-11-03 01:11:15 UTC (rev 1455) @@ -450,7 +450,6 @@ ; : write-done ( -- ) - wait-stream-done stop-stream free-bdl release-sound-buffer @@ -460,12 +459,21 @@ 4 to sd# audio-out install-playback-alarm true to playing? ; +false value stop-lock +: stop-sound ( -- ) + true to stop-lock + playing? if write-done false to playing? then + false to stop-lock +; + \ Alarm handle to stop the stream when the content has been played. : playback-completed-alarm ( -- ) - sd# ( sd# ) - 4 to sd# ( sd# ) - stream-done? if write-done false to playing? then ( sd# ) - to sd# ( ) + stop-lock if exit then + playing? if + sd# 4 to sd# ( sd# ) + stream-done? if write-done false to playing? then ( sd# ) + to sd# ( ) + then ; ' playback-completed-alarm is playback-alarm Modified: ofw/core/ofwcore.fth =================================================================== --- ofw/core/ofwcore.fth 2009-11-03 01:07:21 UTC (rev 1454) +++ ofw/core/ofwcore.fth 2009-11-03 01:11:15 UTC (rev 1455) @@ -173,9 +173,12 @@ \ From reenter.fth headerless nuser aborted? aborted? off +1 value allow-user-aborts? \ Must be 0/1 instead of false/true because of the incrementing in the low-level handler +: enable-user-aborts ( -- ) 1 to allow-user-aborts? ; +: disable-user-aborts ( -- ) 0 to allow-user-aborts? ; headers -: user-abort ( -- ) 1 aborted? ! ; +: user-abort ( -- ) allow-user-aborts? aborted? ! ; headerless \ System and version identification

1 0

r1454 - in cpu/x86: . pc/olpc/via
by svn＠openfirmware.info 03 Nov '09

03 Nov '09

Author: wmb Date: 2009-11-03 02:07:21 +0100 (Tue, 03 Nov 2009) New Revision: 1454 Added: cpu/x86/acpiio.fth Modified: cpu/x86/acpitimer.fth cpu/x86/pc/olpc/via/config.fth cpu/x86/pc/olpc/via/devices.fth cpu/x86/pc/olpc/via/fw.bth cpu/x86/pc/olpc/via/probemem.fth cpu/x86/tsc.fth Log: OLPC trac 9574 - Fixed memory size reporting problem for 32-bit memory interface. Also switched the timing test words "t( .. )t" to use the ACPI timer instead of the timestamp counter, because the latter's frequency changes with thermal throttling. Added: cpu/x86/acpiio.fth =================================================================== --- cpu/x86/acpiio.fth (rev 0) +++ cpu/x86/acpiio.fth 2009-11-03 01:07:21 UTC (rev 1454) @@ -0,0 +1,34 @@ +\ See license at end of file +purpose: Access ACPI registers + +: acpi-b@ ( reg# -- b ) acpi-io-base + pc@ ; +: acpi-b! ( b reg# -- ) acpi-io-base + pc! ; +: acpi-w@ ( reg# -- w ) acpi-io-base + pw@ ; +: acpi-w! ( w reg# -- ) acpi-io-base + pw! ; +: acpi-l@ ( reg# -- l ) acpi-io-base + pl@ ; +: acpi-l! ( l reg# -- ) acpi-io-base + pl! ; + + +\ LICENSE_BEGIN +\ Copyright (c) 2009 FirmWorks +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END Modified: cpu/x86/acpitimer.fth =================================================================== --- cpu/x86/acpitimer.fth 2009-11-02 07:05:33 UTC (rev 1453) +++ cpu/x86/acpitimer.fth 2009-11-03 01:07:21 UTC (rev 1454) @@ -1,16 +1,10 @@ \ See license at end of file purpose: Timing functions using the ACPI timer -: acpi-b@ ( reg# -- b ) acpi-io-base + pc@ ; -: acpi-b! ( b reg# -- ) acpi-io-base + pc! ; -: acpi-w@ ( reg# -- w ) acpi-io-base + pw@ ; -: acpi-w! ( w reg# -- ) acpi-io-base + pw! ; -: acpi-l@ ( reg# -- l ) acpi-io-base + pl@ ; -: acpi-l! ( l reg# -- ) acpi-io-base + pl! ; - \ The ACPI timer counts at 3.579545 MHz. \ 3.579545 * 1024 is 3665 : acpi-timer@ ( -- counts ) 8 acpi-l@ ; + : acpi-us ( us -- ) d# 3664 * d# 10 rshift acpi-timer@ + ( end ) begin dup acpi-timer@ - 0< until ( end ) @@ -22,26 +16,44 @@ drop ; -[ifdef] tsc@ : acpi-calibrate-tsc ( -- ) tsc@ d# 100 acpi-ms tsc@ ( d.start d.end ) 2swap d- ( d.delta ) 2dup d# 100 um/mod nip to ms-factor ( d.delta ms ) d# 100,000 um/mod nip to us-factor ( ) ; -[else] + +[ifdef] use-acpi-timing : us ( us -- ) acpi-us ; ' acpi-ms to ms + \ Timing tools variable timestamp1 : t( ( -- ) acpi-timer@ timestamp1 ! ; +: ))t1 ( -- ticks ) acpi-timer@ timestamp1 @ - ; : )t ( -- ) - acpi-timer@ timestamp1 @ - d# 1000 d# 3580 */ ( microseconds ) + ))t1 d# 1000 d# 3580 */ ( microseconds ) push-decimal <# u# u# u# [char] , hold u# u#s u#> type ." uS " pop-base ; - +: ))t-sec ( -- sec ) ))t1 d# 3,580,000 / ; +: )t-sec ( -- ) + ))t-sec ( seconds ) + push-decimal + <# u# u#s u#> type ." S " + pop-base +; +: .hms ( seconds -- ) + d# 60 /mod d# 60 /mod ( sec min hrs ) + push-decimal + <# u# u#s u#> type ." :" <# u# u# u#> type ." :" <# u# u# u#> type + pop-base +; +: )t-hms + ))t-sec d# 3,580,000 / ( seconds ) + .hms +; [then] \ LICENSE_BEGIN Modified: cpu/x86/pc/olpc/via/config.fth =================================================================== --- cpu/x86/pc/olpc/via/config.fth 2009-11-02 07:05:33 UTC (rev 1453) +++ cpu/x86/pc/olpc/via/config.fth 2009-11-03 01:07:21 UTC (rev 1454) @@ -28,6 +28,7 @@ \ create use-timestamp-counter \ Use CPU's timestamp counter for timing ... \ ... this is worthwhile if your CPU has one. +create use-acpi-timing create resident-packages \ create use-watch-all Modified: cpu/x86/pc/olpc/via/devices.fth =================================================================== --- cpu/x86/pc/olpc/via/devices.fth 2009-11-02 07:05:33 UTC (rev 1453) +++ cpu/x86/pc/olpc/via/devices.fth 2009-11-03 01:07:21 UTC (rev 1454) @@ -12,8 +12,7 @@ fload ${BP}/dev/pciprobe.fth \ Generic PCI probing -\ Use the CPU chip's Time Stamp Counter for timing; it does just what we want -fload ${BP}/cpu/x86/tsc.fth +fload ${BP}/cpu/x86/tsc.fth \ Timestamp counter access words \ Calibrate the Time Stamp Counter using the ACPI timer fload ${BP}/cpu/x86/acpitimer.fth Modified: cpu/x86/pc/olpc/via/fw.bth =================================================================== --- cpu/x86/pc/olpc/via/fw.bth 2009-11-02 07:05:33 UTC (rev 1453) +++ cpu/x86/pc/olpc/via/fw.bth 2009-11-03 01:07:21 UTC (rev 1454) @@ -109,6 +109,8 @@ ; [then] +fload ${BP}/cpu/x86/acpiio.fth \ ACPI register access + fload ${BP}/cpu/x86/pc/olpc/via/probemem.fth \ Memory probing [ifdef] virtual-mode Modified: cpu/x86/pc/olpc/via/probemem.fth =================================================================== --- cpu/x86/pc/olpc/via/probemem.fth 2009-11-02 07:05:33 UTC (rev 1453) +++ cpu/x86/pc/olpc/via/probemem.fth 2009-11-03 01:07:21 UTC (rev 1454) @@ -6,6 +6,7 @@ : total-ram ( -- ramsize ) total-ram-cached ?dup if exit then h# 385 config-b@ d# 24 lshift + h# 48 acpi-l@ h# 1000.0000 and if 2/ then \ Account for possible 32-bit width dup to total-ram-cached ; Modified: cpu/x86/tsc.fth =================================================================== --- cpu/x86/tsc.fth 2009-11-02 07:05:33 UTC (rev 1453) +++ cpu/x86/tsc.fth 2009-11-03 01:07:21 UTC (rev 1454) @@ -38,6 +38,7 @@ : (ms) ( #ms -- ) 0 ?do 1ms loop ; ' (ms) to ms +[ifdef] use-tsc-timing \ These are precise but inaccurate, as the TSC varies with clock throttling \ Timing tools 2variable timestamp : t( ( -- ) tsc@ timestamp 2! ; @@ -64,6 +65,7 @@ ))t us-factor d# 1,000,000 * um/mod nip ( seconds ) .hms ; +[then] \ LICENSE_BEGIN \ Copyright (c) 2006 FirmWorks

1 0

r1453 - dev/olpc/viacamera
by svn＠openfirmware.info 02 Nov '09

02 Nov '09

Author: wmb Date: 2009-11-02 08:05:33 +0100 (Mon, 02 Nov 2009) New Revision: 1453 Modified: dev/olpc/viacamera/loadpkg.fth Log: OLPC trac 9576 - fixed regression in "test /camera". Modified: dev/olpc/viacamera/loadpkg.fth =================================================================== --- dev/olpc/viacamera/loadpkg.fth 2009-10-30 20:41:00 UTC (rev 1452) +++ dev/olpc/viacamera/loadpkg.fth 2009-11-02 07:05:33 UTC (rev 1453) @@ -4,7 +4,7 @@ : alloc-capture-buffer ( len -- vadr padr ) drop ( ) - " graphmem" $call-parent ( vadr ) + graphmem ( vadr ) dup >physical ( vadr padr ) ;

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