[coreboot] APIC and lspci
Hilbert_Tu at pegatroncorp.com
Tue Sep 4 04:06:27 CEST 2018
I think there is no MSI mode in my system.
In my case, device 00:14.0 is SATA controller and as you said, there is likely a 1 to 1 mapping, so I expect it should maps to one of IRQ16-23 for IOxAPIC. But from lspci, it is IRQ28 and I want to know if this is changed in Coreboot or in kernel and where to modify it. Another is my MAC (02:00.0) which connects to Denverton through PCI-e, the lspci's output is "pin A routed to IRQ 0". Why IRQ0 is being used? Anything I forgot to configure? I'll check the BWG, but I have to admit I am too "fresh" to understand it :p. If you know something, please advise. Thanks.
From: Nico Huber [mailto:nico.h at gmx.de]
Sent: Tuesday, September 04, 2018 1:46 AM
To: Hilbert Tu(杜睿哲_Pegatron); coreboot at coreboot.org
Subject: Re: [coreboot] APIC and lspci
On 03.09.2018 12:36, Hilbert Tu(杜睿哲_Pegatron) wrote:
> I have a customized Intel Denverton-NS platform similar like Harcuvar
> CRB. In dmesg, I can see following:
> [ 10.973387] ACPI: PCI Interrupt Link [LNKA] (IRQs 6 7 10 *11 12 14 15)
> [ 10.981587] ACPI: PCI Interrupt Link [LNKB] (IRQs 6 7 *10 11 12 14 15)
> [ 10.989776] ACPI: PCI Interrupt Link [LNKC] (IRQs *6 7 10 11 12 14 15)
> [ 10.997961] ACPI: PCI Interrupt Link [LNKD] (IRQs 6 *7 10 11 12 14 15)
> [ 11.006147] ACPI: PCI Interrupt Link [LNKE] (IRQs 6 7 10 11 *12 14 15)
> [ 11.014332] ACPI: PCI Interrupt Link [LNKF] (IRQs 6 7 10 11 12 *14 15)
> [ 11.022518] ACPI: PCI Interrupt Link [LNKG] (IRQs 6 7 10 11 12 14 *15)
> [ 11.030697] ACPI: PCI Interrupt Link [LNKH] (IRQs 6 7 10 11 12 14 *15)
> And by “lspci -s 00:14.0 -vv”, there is a message “Interrupt: pin A
> routed to IRQ 28”. Actually I know in the devicetree.cb, the device 14’s
> interrupt is configured by IR08 which routes INTA to PIRQE and LNKE is
> using IRQ12. This is the legacy interrupt mode as kernel message dumped.
> But in ACPI mode, why does lspci report IRQ28 and how to reconfigure it
> in Coreboot? Please help to clarify. Thanks.
there is actually a third case, MSI interrupts. It's hard to tell if
that is used without seeing the lspci output. MSIs are configured by
the OS, not coreboot.
In APIC mode, there is likely a 1:1 mapping of the PIRQ LNK* to APIC
IRQs; e.g. LNKA -> 16, LNKB -> 17, ..., LNKH -> 23 (this usually can't
be changed, but I don't know for sure if that is the case for Denver-
ton). It should be documented in the BIOS Writer's Guide for your SoC.
This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited.
More information about the coreboot