[coreboot] APIC and lspci

Nico Huber nico.h at gmx.de
Mon Sep 3 19:45:54 CEST 2018


Hi Hilbert,

On 03.09.2018 12:36, Hilbert Tu(杜睿哲_Pegatron) wrote:
> I have a customized Intel Denverton-NS platform similar like Harcuvar
> CRB. In dmesg, I can see following:
> [   10.973387] ACPI: PCI Interrupt Link [LNKA] (IRQs 6 7 10 *11 12 14 15)
> [   10.981587] ACPI: PCI Interrupt Link [LNKB] (IRQs 6 7 *10 11 12 14 15)
> [   10.989776] ACPI: PCI Interrupt Link [LNKC] (IRQs *6 7 10 11 12 14 15)
> [   10.997961] ACPI: PCI Interrupt Link [LNKD] (IRQs 6 *7 10 11 12 14 15)
> [   11.006147] ACPI: PCI Interrupt Link [LNKE] (IRQs 6 7 10 11 *12 14 15)
> [   11.014332] ACPI: PCI Interrupt Link [LNKF] (IRQs 6 7 10 11 12 *14 15)
> [   11.022518] ACPI: PCI Interrupt Link [LNKG] (IRQs 6 7 10 11 12 14 *15)
> [   11.030697] ACPI: PCI Interrupt Link [LNKH] (IRQs 6 7 10 11 12 14 *15)
> And by “lspci -s 00:14.0 -vv”, there is a message “Interrupt: pin A
> routed to IRQ 28”. Actually I know in the devicetree.cb, the device 14’s
> interrupt is configured by IR08 which routes INTA to PIRQE and LNKE is
> using IRQ12. This is the legacy interrupt mode as kernel message dumped.
> But in ACPI mode, why does lspci report IRQ28 and how to reconfigure it
> in Coreboot? Please help to clarify. Thanks.

there is actually a third case, MSI interrupts. It's hard to tell if
that is used without seeing the lspci output. MSIs are configured by
the OS, not coreboot.

In APIC mode, there is likely a 1:1 mapping of the PIRQ LNK* to APIC
IRQs; e.g. LNKA -> 16, LNKB -> 17, ..., LNKH -> 23 (this usually can't
be changed, but I don't know for sure if that is the case for Denver-
ton). It should be documented in the BIOS Writer's Guide for your SoC.

Nico



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