[coreboot] Intel Leaf Hill Coreboot Trouble
Zoran Stojsavljevic
zoran.stojsavljevic at gmail.com
Wed Sep 27 21:10:39 CEST 2017
Since I really want to help, and I do not have any time left for Coreboot
(since I am fully/200% devoted to Fedora/RHEL/kernel.org and YOCTO), three
kludge thinking from me (APL-I supposed to be my
get_to_the_rich_pals_vehicle in Y2015, but mortally crashed somewhere in
the process - For Good)!:
[1] I did assemble APL-I Coreboot based upon www.intel.com/fsp (please,
choose APL-I FSP release) APL-I FSP blobs. I did at the very end very clean
compilation, but there are two catches 22 to what I did (significant
credits/courtesy to Martin Roth, Martin really pulled me up and survived me
in this weird FSP 2.0 crazy business of INTEL's)... ;-)
[A] The Coreboot release I played with is: [user at localhost coreboot]$
git describe ==>> 4.5-1029-g97535558f1 (NOT 4.6);
[B] Never tested it on real HW, I do NOT have APL-I HW, Leaf Hill,
Deaf Hill or you name it... But I did attach my .config/CONFIG!
[2] As my .config (attached CONFIG) suggests, please, try with some other
payload (SeaBIOS as for example, which I used);
[3] You need to compare my .config with yours (I have neither any time,
neither any desire to do this).
Good Luck, very much/totally INTEL 2.0 FSP (doomed to the bones) dependent
enthusiast (I can still advise out of desperation, if you investigate and
continue posting results here).
P.S. Martin (Roth), once again, thank you for unselfish help (I do
remember)! :-)
Zoran
_______
On Wed, Sep 27, 2017 at 2:01 PM, Cameron Craig <Cameron.Craig at exterity.com>
wrote:
> Hi All,
>
>
>
> I’m currently trying to get coreboot working on an Intel Leaf Hill
> development board, we are using U-Boot as a payload.
>
>
>
> I have managed to create a bootable image using an out of date copy of
> coreboot and U-Boot, provided by Intel under NDA.
>
> The stitching process used to generate the image is a little ugly: a set
> of Windows tools are provided (or pointed at) by Intel to stitch the
> various blobs together to create an 8MB image.
>
> We would like to move away from this process. Using the cbfs tool it looks
> like we are getting a legacy image composed entirely of a single CBFS.
>
>
>
> However, as far as I understand, the latest coreboot release (v4.6) should
> be capable of producing a 16MB working image without the use of external
> tools.
>
> This is of course dependent on the provision of the correct binary blobs
> such as the FSP, flash descriptor and IFWI.
>
> I have attached the descriptor of the IFWI image being used.
>
>
>
> This is the process I have followed in order to generate a coreboot image:
>
> 1. Clone coreboot (v4.6)
>
> 2. Obtain Apollo Lake FSP from Intel (https://github.com/IntelFSP/
> FSP)
>
> 3. Split FSP into its constituent parts (https://raw.
> githubusercontent.com/tianocore/edk2/master/IntelFsp2Pkg/Tools/
> SplitFspBin.py)
>
> 4. Extract Flash Descriptor from an existing Leaf Hill UEFI image
> (./ifdtool --extract leaf_hill_ref_board_uefi.bin)
>
> 5. Obtain IFWI image from Intel (Apollo Lake Technical Library)
>
> 6. make menuconfig (config file is attached)
>
> a. Mainboard
>
> i. Mainboard
> vendor (Intel)
>
> ii. Mainboard
> model (Leafhill)
>
> iii. [*]
> Use IFWI Stitching
>
> iv. (IFWI)
> section in .fmd file to place IFWI blob
>
> v. (IFWI_SPI.bin)
> Path to image coming from FIT Tool
>
> vi. (descriptor.bin)
> path to descriptor.bin
>
> vii. (Fsp_M.fd)
> path to FSP-M.Fv blob
>
> viii. (Fsp_S.fd)
> path to FSP-S.Fv
>
> b. Payload
>
> i. Add
> a payload (U-Boot (Experimental))
>
> ii. U-Boot
> version (v2016.1)
>
> iii. (coreboot-x86_defconfig)
> U-Boot config file
>
> c. The rest are at Leaf Hill defaults.
>
> 7. make
>
> 8. Flash image to Leaf Hill SPI flash
>
>
>
> As far as I can tell, this process should produce a working image.
>
> However it does not. My most recent attempt has managed to blink the
> PWR_OK LED, suggesting the PMIC/PMC is working, but no serial messages.
>
> Other than that, I currently have no working theories as to what the root
> cause is L
>
>
>
> Is there anything obviously wrong with this process?
>
> Are there any bugs that I should be aware of relating to coreboot on an
> Apollo Lake platform?
>
> I haven’t found a lot of documentation online to describe the exact
> configuration and blob usage, are there any relevant sources of
> documentation you could point me towards?
>
>
>
> Any help to answer the above, or any other advice would be greatly
> appreciated.
>
>
>
> Cheers,
>
> Cameron
>
>
>
> Cameron Craig | Graduate Software Engineer | Exterity Limited
> tel: +44 1383 828 250 <+44%201383%20828250> | fax:
> e: Cameron.Craig at exterity.com | w: www.exterity.com
>
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