<div dir="ltr">Since I really want to help, and I do not have any time left for Coreboot (since I am fully/200% devoted to Fedora/RHEL/<a href="http://kernel.org">kernel.org</a> and YOCTO), three kludge thinking from me (APL-I supposed to be my get_to_the_rich_pals_vehicle in Y2015, but mortally crashed somewhere in the process - For Good)!:<div><br></div><div>[1] I did assemble APL-I Coreboot based upon <a href="http://www.intel.com/fsp">www.intel.com/fsp</a> (please, choose APL-I FSP release) APL-I FSP blobs. I did at the very end very clean compilation, but there are two catches 22 to what I did (significant credits/courtesy to Martin Roth, Martin really pulled me up and survived me in this weird FSP 2.0 crazy business of INTEL's)... ;-)</div><div> [A] The Coreboot release I played with is: [user@localhost coreboot]$ git describe ==>> 4.5-1029-g97535558f1 (NOT 4.6);</div><div> [B] Never tested it on real HW, I do NOT have APL-I HW, Leaf Hill, Deaf Hill or you name it... But I did attach my .config/CONFIG!</div><div>[2] As my .config (attached CONFIG) suggests, please, try with some other payload (SeaBIOS as for example, which I used);</div><div>[3] You need to compare my .config with yours (I have neither any time, neither any desire to do this).<br></div><div><br></div><div>Good Luck, very much/totally INTEL 2.0 FSP (doomed to the bones) dependent enthusiast (I can still advise out of desperation, if you investigate and continue posting results here).</div><div><br></div><div>P.S. Martin (Roth), once again, thank you for unselfish help (I do remember)! :-)</div><div><br></div><div>Zoran</div><div>_______</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Sep 27, 2017 at 2:01 PM, Cameron Craig <span dir="ltr"><<a href="mailto:Cameron.Craig@exterity.com" target="_blank">Cameron.Craig@exterity.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div lang="EN-GB" link="blue" vlink="purple">
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<p class="MsoNormal">Hi All,<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">I’m currently trying to get coreboot working on an Intel Leaf Hill development board, we are using U-Boot as a payload.<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">I have managed to create a bootable image using an out of date copy of coreboot and U-Boot, provided by Intel under NDA.<u></u><u></u></p>
<p class="MsoNormal">The stitching process used to generate the image is a little ugly: a set of Windows tools are provided (or pointed at) by Intel to stitch the various blobs together to create an 8MB image.<u></u><u></u></p>
<p class="MsoNormal">We would like to move away from this process. Using the cbfs tool it looks like we are getting a legacy image composed entirely of a single CBFS.<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">However, as far as I understand, the latest coreboot release (v4.6) should be capable of producing a 16MB working image without the use of external tools.<u></u><u></u></p>
<p class="MsoNormal">This is of course dependent on the provision of the correct binary blobs such as the FSP, flash descriptor and IFWI.<u></u><u></u></p>
<p class="MsoNormal">I have attached the descriptor of the IFWI image being used.<u></u><u></u></p>
<p class="MsoNormal"> <u></u><u></u></p>
<p class="MsoNormal">This is the process I have followed in order to generate a coreboot image:<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph"><u></u><span>1.<span style="font:7.0pt "Times New Roman"">
</span></span><u></u>Clone coreboot (v4.6)<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph"><u></u><span>2.<span style="font:7.0pt "Times New Roman"">
</span></span><u></u>Obtain Apollo Lake FSP from Intel (<a href="https://github.com/IntelFSP/FSP" target="_blank">https://github.com/IntelFSP/<wbr>FSP</a>)<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph"><u></u><span>3.<span style="font:7.0pt "Times New Roman"">
</span></span><u></u>Split FSP into its constituent parts (<a href="https://raw.githubusercontent.com/tianocore/edk2/master/IntelFsp2Pkg/Tools/SplitFspBin.py" target="_blank">https://raw.<wbr>githubusercontent.com/<wbr>tianocore/edk2/master/<wbr>IntelFsp2Pkg/Tools/<wbr>SplitFspBin.py</a>)<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph"><u></u><span>4.<span style="font:7.0pt "Times New Roman"">
</span></span><u></u>Extract Flash Descriptor from an existing Leaf Hill UEFI image (./ifdtool --extract leaf_hill_ref_board_uefi.bin)<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph"><u></u><span>5.<span style="font:7.0pt "Times New Roman"">
</span></span><u></u>Obtain IFWI image from Intel (Apollo Lake Technical Library)<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph"><u></u><span>6.<span style="font:7.0pt "Times New Roman"">
</span></span><u></u>make menuconfig (config file is attached)<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:72.0pt">
<u></u><span>a.<span style="font:7.0pt "Times New Roman"">
</span></span><u></u>Mainboard<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:108.0pt">
<u></u><span><span style="font:7.0pt "Times New Roman""> <wbr> <wbr>
</span>i.<span style="font:7.0pt "Times New Roman""> </span></span><u></u>Mainboard vendor (Intel)<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:108.0pt">
<u></u><span><span style="font:7.0pt "Times New Roman""> <wbr>
</span>ii.<span style="font:7.0pt "Times New Roman""> </span></span><u></u>Mainboard model (Leafhill)<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:108.0pt">
<u></u><span><span style="font:7.0pt "Times New Roman""> <wbr>
</span>iii.<span style="font:7.0pt "Times New Roman""> </span></span><u></u>[*] Use IFWI Stitching<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:108.0pt">
<u></u><span><span style="font:7.0pt "Times New Roman""> <wbr>
</span>iv.<span style="font:7.0pt "Times New Roman""> </span></span><u></u>(IFWI) section in .fmd file to place IFWI blob<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:108.0pt">
<u></u><span><span style="font:7.0pt "Times New Roman""> <wbr>
</span>v.<span style="font:7.0pt "Times New Roman""> </span></span><u></u>(IFWI_SPI.bin) Path to image coming from FIT Tool<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:108.0pt">
<u></u><span><span style="font:7.0pt "Times New Roman""> <wbr>
</span>vi.<span style="font:7.0pt "Times New Roman""> </span></span><u></u>(descriptor.bin) path to descriptor.bin<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:108.0pt">
<u></u><span><span style="font:7.0pt "Times New Roman""> <wbr>
</span>vii.<span style="font:7.0pt "Times New Roman""> </span></span><u></u>(Fsp_M.fd) path to FSP-M.Fv blob<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:108.0pt">
<u></u><span><span style="font:7.0pt "Times New Roman""> <wbr>
</span>viii.<span style="font:7.0pt "Times New Roman""> </span></span><u></u>(Fsp_S.fd) path to FSP-S.Fv<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:72.0pt">
<u></u><span>b.<span style="font:7.0pt "Times New Roman"">
</span></span><u></u>Payload<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:108.0pt">
<u></u><span><span style="font:7.0pt "Times New Roman""> <wbr> <wbr>
</span>i.<span style="font:7.0pt "Times New Roman""> </span></span><u></u>Add a payload (U-Boot (Experimental))<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:108.0pt">
<u></u><span><span style="font:7.0pt "Times New Roman""> <wbr>
</span>ii.<span style="font:7.0pt "Times New Roman""> </span></span><u></u>U-Boot version (v2016.1)<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:108.0pt">
<u></u><span><span style="font:7.0pt "Times New Roman""> <wbr>
</span>iii.<span style="font:7.0pt "Times New Roman""> </span></span><u></u>(coreboot-x86_defconfig) U-Boot config file<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph" style="margin-left:72.0pt">
<u></u><span>c.<span style="font:7.0pt "Times New Roman"">
</span></span><u></u>The rest are at Leaf Hill defaults.<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph"><u></u><span>7.<span style="font:7.0pt "Times New Roman"">
</span></span><u></u>make<u></u><u></u></p>
<p class="m_-214314034319128437MsoListParagraph"><u></u><span>8.<span style="font:7.0pt "Times New Roman"">
</span></span><u></u>Flash image to Leaf Hill SPI flash<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">As far as I can tell, this process should produce a working image.<u></u><u></u></p>
<p class="MsoNormal">However it does not. My most recent attempt has managed to blink the PWR_OK LED, suggesting the PMIC/PMC is working, but no serial messages.<u></u><u></u></p>
<p class="MsoNormal">Other than that, I currently have no working theories as to what the root cause is
<span style="font-family:Wingdings">L</span><u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">Is there anything obviously wrong with this process?<u></u><u></u></p>
<p class="MsoNormal">Are there any bugs that I should be aware of relating to coreboot on an Apollo Lake platform?<u></u><u></u></p>
<p class="MsoNormal">I haven’t found a lot of documentation online to describe the exact configuration and blob usage, are there any relevant sources of documentation you could point me towards?<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">Any help to answer the above, or any other advice would be greatly appreciated.<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">Cheers,<u></u><u></u></p>
<p class="MsoNormal">Cameron<u></u><u></u></p>
</div>
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