[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: [WIP] Make FSP optional Completely
Rizwan Qureshi (Code Review)
gerrit at coreboot.org
Wed Sep 19 12:50:09 CEST 2018
Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/28674
Change subject: soc/intel/cannonlake: [WIP] Make FSP optional Completely
......................................................................
soc/intel/cannonlake: [WIP] Make FSP optional Completely
Change-Id: I557b8001a2f59220a9da096100b601c9bd8764ee
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
M src/lib/coreboot_table.c
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/cpu.c
A src/soc/intel/cannonlake/fsp_igd_bar.c
A src/soc/intel/cannonlake/fsp_rst_handle.c
M src/soc/intel/cannonlake/graphics.c
M src/soc/intel/cannonlake/include/soc/ramstage.h
M src/soc/intel/cannonlake/include/soc/romstage.h
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/include/soc/vr_config.h
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/reset.c
M src/soc/intel/cannonlake/romstage/Makefile.inc
A src/soc/intel/cannonlake/romstage/dimminfo.c
A src/soc/intel/cannonlake/romstage/dimminfo.h
A src/soc/intel/cannonlake/romstage/meminit.c
A src/soc/intel/cannonlake/romstage/meminit.h
M src/soc/intel/cannonlake/romstage/romstage.c
A src/soc/intel/cannonlake/siliconinit.c
A src/soc/intel/cannonlake/siliconinit.h
M src/soc/intel/cannonlake/vr_config.c
A src/soc/intel/common/basecode/include/intelbasecode/memmap.h
24 files changed, 325 insertions(+), 110 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28674/1
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 62b3aaa..c83ff76 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -603,3 +603,8 @@
cbmem_list();
return (void *)cbtable_start;
}
+
+int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
+{
+ die ("platform does not implement fill_lb_framebuffer");
+}
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 5a74b6f..9152ee7 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -30,7 +30,7 @@
select BOOT_DEVICE_SUPPORTS_WRITES
select C_ENVIRONMENT_BOOTBLOCK
select CACHE_MRC_SETTINGS
- select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
+# select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select COMMON_FADT
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select GENERIC_GPIO_LIB
@@ -46,7 +46,7 @@
select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
- select PLATFORM_USES_FSP2_0
+# select PLATFORM_USES_FSP2_0
select POSTCAR_CONSOLE
select POSTCAR_STAGE
select REG_SCRIPT
@@ -74,8 +74,9 @@
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_2017_BINDING
- select DISPLAY_FSP_VERSION_INFO
- select FSP_PARAM_OVERRIDE
+# select DISPLAY_FSP_VERSION_INFO
+# select FSP_PARAM_OVERRIDE
+ select SOC_INTEL_COMMON_BASECODE
config UART_DEBUG
bool "Enable UART debug port."
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 761fe81..c453dc0 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -23,6 +23,7 @@
bootblock-$(CONFIG_UART_DEBUG) += uart.c
romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_rst_handle.c
romstage-y += gpio.c
romstage-y += gspi.c
romstage-y += i2c.c
@@ -37,6 +38,7 @@
ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += finalize.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_rst_handle.c
ramstage-$(CONFIG_FSP_PARAM_OVERRIDE) += fsp_params.c
ramstage-y += gpio.c
ramstage-y += graphics.c
@@ -55,8 +57,9 @@
ramstage-y += spi.c
ramstage-y += systemagent.c
ramstage-$(CONFIG_UART_DEBUG) += uart.c
-ramstage-y += vr_config.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += vr_config.c
ramstage-y += sd.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += siliconinit.c
smm-y += gpio.c
smm-y += p2sb.c
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 0c0a05d..4c2f5e5 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -18,8 +18,6 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <fsp/api.h>
-#include <fsp/util.h>
#include <intelblocks/acpi.h>
#include <intelblocks/chip.h>
#include <intelblocks/xdci.h>
@@ -28,6 +26,7 @@
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <string.h>
+#include "siliconinit.h"
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
const char *soc_acpi_name(const struct device *dev)
@@ -98,10 +97,10 @@
void soc_init_pre_device(void *chip_info)
{
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ silicon_init(romstage_handoff_is_resume());
/* Display FIRMWARE_VERSION_INFO_HOB */
- fsp_display_fvi_version_hob();
+ display_fvi_version_hob();
}
static void pci_domain_set_resources(struct device *dev)
@@ -140,3 +139,13 @@
.enable_dev = &soc_enable,
.init = &soc_init_pre_device,
};
+
+__weak void display_fvi_version_hob(void)
+{
+ die("No FSP to run display_fvi_version_hob");
+}
+
+__weak void silicon_init(bool s3wake)
+{
+ die("No FSP to run silicon_init");
+}
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index ba87045..a59530c 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -28,10 +28,11 @@
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/smm.h>
+#include "siliconinit.h"
static void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ soc_fsps_load(romstage_handoff_is_resume());
}
static void configure_isst(void)
@@ -239,3 +240,8 @@
if (mp_init_with_smm(cpu_bus, &mp_ops))
printk(BIOS_ERR, "MP initialization failure.\n");
}
+
+__weak void soc_fsps_load(bool s3wake)
+{
+ die ("No FSP to run fsps_load");
+}
diff --git a/src/soc/intel/cannonlake/fsp_igd_bar.c b/src/soc/intel/cannonlake/fsp_igd_bar.c
new file mode 100644
index 0000000..ae81189
--- /dev/null
+++ b/src/soc/intel/cannonlake/fsp_igd_bar.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016-2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <fsp/util.h>
+#include <intelblocks/graphics.h>
+
+uintptr_t fsp_soc_get_igd_bar(void)
+{
+ return graphics_get_memory_base();
+}
diff --git a/src/soc/intel/cannonlake/fsp_rst_handle.c b/src/soc/intel/cannonlake/fsp_rst_handle.c
new file mode 100644
index 0000000..8069a1e
--- /dev/null
+++ b/src/soc/intel/cannonlake/fsp_rst_handle.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <fsp/util.h>
+#include <reset.h>
+
+void chipset_handle_reset(uint32_t status)
+{
+ switch (status) {
+ case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
+ printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
+ do_global_reset();
+ break;
+ default:
+ printk(BIOS_ERR, "unhandled reset type %x\n", status);
+ die("unknown reset type");
+ break;
+ }
+}
diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c
index 58f87f7..bae9dd5 100644
--- a/src/soc/intel/cannonlake/graphics.c
+++ b/src/soc/intel/cannonlake/graphics.c
@@ -16,18 +16,12 @@
#include <arch/acpigen.h>
#include <console/console.h>
-#include <fsp/util.h>
#include <device/device.h>
#include <device/pci.h>
#include <drivers/intel/gma/i915_reg.h>
#include <drivers/intel/gma/opregion.h>
#include <intelblocks/graphics.h>
-uintptr_t fsp_soc_get_igd_bar(void)
-{
- return graphics_get_memory_base();
-}
-
void graphics_soc_init(struct device *dev)
{
uint32_t ddi_buf_ctl;
diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h
index 4a96185..e3953d2 100644
--- a/src/soc/intel/cannonlake/include/soc/ramstage.h
+++ b/src/soc/intel/cannonlake/include/soc/ramstage.h
@@ -19,10 +19,13 @@
#include <chip.h>
#include <device/device.h>
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0)
#include <fsp/api.h>
#include <fsp/util.h>
void mainboard_silicon_init_params(FSP_S_CONFIG *params);
+#endif
+
void soc_init_pre_device(void *chip_info);
#endif
diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h
index 6faf110..a846e26 100644
--- a/src/soc/intel/cannonlake/include/soc/romstage.h
+++ b/src/soc/intel/cannonlake/include/soc/romstage.h
@@ -19,9 +19,13 @@
#include <arch/cpu.h>
#include <chip.h>
+
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0)
#include <fsp/api.h>
void mainboard_memory_init_params(FSPM_UPD *mupd);
+#endif
+
void systemagent_early_init(void);
/* Board type */
diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h
index 9121ac3..69766c8 100644
--- a/src/soc/intel/cannonlake/include/soc/smm.h
+++ b/src/soc/intel/cannonlake/include/soc/smm.h
@@ -19,7 +19,7 @@
#include <stdint.h>
#include <cpu/x86/msr.h>
-#include <fsp/memmap.h>
+#include <intelbasecode/memmap.h>
#include <soc/gpio.h>
struct ied_header {
diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h
index 385767d..b993782 100644
--- a/src/soc/intel/cannonlake/include/soc/vr_config.h
+++ b/src/soc/intel/cannonlake/include/soc/vr_config.h
@@ -18,8 +18,6 @@
#ifndef _SOC_VR_CONFIG_H_
#define _SOC_VR_CONFIG_H_
-#include <fsp/api.h>
-
struct vr_config {
/* The below settings will take effect when this is set to 1
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 64e07be..aa037f0 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -21,7 +21,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <fsp/util.h>
+#include <intelbasecode/memmap.h>
#include <intelblocks/ebda.h>
#include <intelblocks/systemagent.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c
index 140fbff..bc3d82b 100644
--- a/src/soc/intel/cannonlake/reset.c
+++ b/src/soc/intel/cannonlake/reset.c
@@ -17,7 +17,6 @@
#include <console/console.h>
#include <intelblocks/cse.h>
#include <intelblocks/pmclib.h>
-#include <fsp/util.h>
#include <reset.h>
#include <string.h>
#include <timer.h>
@@ -88,17 +87,3 @@
pmc_global_reset_enable(1);
hard_reset();
}
-
-void chipset_handle_reset(uint32_t status)
-{
- switch (status) {
- case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
- printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
- do_global_reset();
- break;
- default:
- printk(BIOS_ERR, "unhandled reset type %x\n", status);
- die("unknown reset type");
- break;
- }
-}
diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc
index ab3e8e2..195e7aa 100644
--- a/src/soc/intel/cannonlake/romstage/Makefile.inc
+++ b/src/soc/intel/cannonlake/romstage/Makefile.inc
@@ -17,3 +17,4 @@
romstage-y += romstage.c
romstage-$(CONFIG_FSP_PARAM_OVERRIDE) += fsp_params.c
romstage-y += systemagent.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += meminit.c
diff --git a/src/soc/intel/cannonlake/romstage/dimminfo.c b/src/soc/intel/cannonlake/romstage/dimminfo.c
new file mode 100644
index 0000000..2110540
--- /dev/null
+++ b/src/soc/intel/cannonlake/romstage/dimminfo.c
@@ -0,0 +1,90 @@
+
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "dimminfo.h"
+#include <fsp/util.h>
+
+#define FSP_SMBIOS_MEMORY_INFO_GUID \
+{ \
+ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
+ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \
+}
+
+/* Save the DIMM information for SMBIOS table 17 */
+void save_dimm_info(void)
+{
+ int channel, dimm, dimm_max, index;
+ size_t hob_size;
+ const CONTROLLER_INFO *ctrlr_info;
+ const CHANNEL_INFO *channel_info;
+ const DIMM_INFO *src_dimm;
+ struct dimm_info *dest_dimm;
+ struct memory_info *mem_info;
+ const MEMORY_INFO_DATA_HOB *memory_info_hob;
+ const uint8_t smbios_memory_info_guid[16] =
+ FSP_SMBIOS_MEMORY_INFO_GUID;
+
+ /* Locate the memory info HOB, presence validated by raminit */
+ memory_info_hob = fsp_find_extension_hob_by_guid(
+ smbios_memory_info_guid,
+ &hob_size);
+ if (memory_info_hob == NULL || hob_size == 0) {
+ printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
+ return;
+ }
+
+ /*
+ * Allocate CBMEM area for DIMM information used to populate SMBIOS
+ * table 17
+ */
+ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+ if (mem_info == NULL) {
+ printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
+ return;
+ }
+ memset(mem_info, 0, sizeof(*mem_info));
+
+ /* Describe the first N DIMMs in the system */
+ index = 0;
+ dimm_max = ARRAY_SIZE(mem_info->dimm);
+ ctrlr_info = &memory_info_hob->Controller[0];
+ for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {
+ channel_info = &ctrlr_info->ChannelInfo[channel];
+ if (channel_info->Status != CHANNEL_PRESENT)
+ continue;
+ for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {
+ src_dimm = &channel_info->DimmInfo[dimm];
+ dest_dimm = &mem_info->dimm[index];
+
+ if (src_dimm->Status != DIMM_PRESENT)
+ continue;
+
+ /* Populate the DIMM information */
+ dimm_info_fill(dest_dimm,
+ src_dimm->DimmCapacity,
+ memory_info_hob->MemoryType,
+ memory_info_hob->ConfiguredMemoryClockSpeed,
+ channel_info->ChannelId,
+ src_dimm->DimmId,
+ (const char *)src_dimm->ModulePartNum,
+ sizeof(src_dimm->ModulePartNum),
+ memory_info_hob->DataWidth);
+ index++;
+ }
+ }
+ mem_info->dimm_cnt = index;
+ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
+}
diff --git a/src/soc/intel/cannonlake/romstage/dimminfo.h b/src/soc/intel/cannonlake/romstage/dimminfo.h
new file mode 100644
index 0000000..237b331
--- /dev/null
+++ b/src/soc/intel/cannonlake/romstage/dimminfo.h
@@ -0,0 +1 @@
+void save_dimm_info(void);
diff --git a/src/soc/intel/cannonlake/romstage/meminit.c b/src/soc/intel/cannonlake/romstage/meminit.c
new file mode 100644
index 0000000..b956482
--- /dev/null
+++ b/src/soc/intel/cannonlake/romstage/meminit.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <arch/early_variables.h>
+#include <assert.h>
+#include <chip.h>
+#include <cpu/x86/mtrr.h>
+#include <cbmem.h>
+#include <compiler.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <intelblocks/cse.h>
+#include <intelblocks/pmclib.h>
+#include <memory_info.h>
+#include <soc/intel/common/smbios.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
+#include <string.h>
+#include <timestamp.h>
+#include "meminit.h"
+
+void memory_init(bool s3wake)
+{
+ fsp_memory_init(s3wake);
+}
diff --git a/src/soc/intel/cannonlake/romstage/meminit.h b/src/soc/intel/cannonlake/romstage/meminit.h
new file mode 100644
index 0000000..233948b
--- /dev/null
+++ b/src/soc/intel/cannonlake/romstage/meminit.h
@@ -0,0 +1,15 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+void memory_init(bool s3wake);
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 113798d..071c6cc 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -21,7 +21,6 @@
#include <cbmem.h>
#include <compiler.h>
#include <console/console.h>
-#include <fsp/util.h>
#include <intelblocks/cse.h>
#include <intelblocks/pmclib.h>
#include <memory_info.h>
@@ -32,81 +31,11 @@
#include <soc/romstage.h>
#include <string.h>
#include <timestamp.h>
+#include "meminit.h"
+#include "dimminfo.h"
static struct chipset_power_state power_state CAR_GLOBAL;
-#define FSP_SMBIOS_MEMORY_INFO_GUID \
-{ \
- 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
- 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \
-}
-
-/* Save the DIMM information for SMBIOS table 17 */
-static void save_dimm_info(void)
-{
- int channel, dimm, dimm_max, index;
- size_t hob_size;
- const CONTROLLER_INFO *ctrlr_info;
- const CHANNEL_INFO *channel_info;
- const DIMM_INFO *src_dimm;
- struct dimm_info *dest_dimm;
- struct memory_info *mem_info;
- const MEMORY_INFO_DATA_HOB *memory_info_hob;
- const uint8_t smbios_memory_info_guid[16] =
- FSP_SMBIOS_MEMORY_INFO_GUID;
-
- /* Locate the memory info HOB, presence validated by raminit */
- memory_info_hob = fsp_find_extension_hob_by_guid(
- smbios_memory_info_guid,
- &hob_size);
- if (memory_info_hob == NULL || hob_size == 0) {
- printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
- return;
- }
-
- /*
- * Allocate CBMEM area for DIMM information used to populate SMBIOS
- * table 17
- */
- mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
- if (mem_info == NULL) {
- printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
- return;
- }
- memset(mem_info, 0, sizeof(*mem_info));
-
- /* Describe the first N DIMMs in the system */
- index = 0;
- dimm_max = ARRAY_SIZE(mem_info->dimm);
- ctrlr_info = &memory_info_hob->Controller[0];
- for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {
- channel_info = &ctrlr_info->ChannelInfo[channel];
- if (channel_info->Status != CHANNEL_PRESENT)
- continue;
- for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {
- src_dimm = &channel_info->DimmInfo[dimm];
- dest_dimm = &mem_info->dimm[index];
-
- if (src_dimm->Status != DIMM_PRESENT)
- continue;
-
- /* Populate the DIMM information */
- dimm_info_fill(dest_dimm,
- src_dimm->DimmCapacity,
- memory_info_hob->MemoryType,
- memory_info_hob->ConfiguredMemoryClockSpeed,
- channel_info->ChannelId,
- src_dimm->DimmId,
- (const char *)src_dimm->ModulePartNum,
- sizeof(src_dimm->ModulePartNum),
- memory_info_hob->DataWidth);
- index++;
- }
- }
- mem_info->dimm_cnt = index;
- printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
-}
-
asmlinkage void car_stage_entry(void)
{
bool s3wake;
@@ -123,7 +52,7 @@
timestamp_add_now(TS_START_ROMSTAGE);
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
- fsp_memory_init(s3wake);
+ memory_init(s3wake);
pmc_set_disb();
if (!s3wake)
save_dimm_info();
@@ -146,3 +75,13 @@
run_postcar_phase(&pcf);
}
+
+__weak void save_dimm_info()
+{
+ printk(BIOS_ERR, "%s weak function called\n", __func__);
+}
+
+__weak void memory_init(bool s3wake)
+{
+ die("No FSP to run memory_init");
+}
diff --git a/src/soc/intel/cannonlake/siliconinit.c b/src/soc/intel/cannonlake/siliconinit.c
new file mode 100644
index 0000000..892c2ff
--- /dev/null
+++ b/src/soc/intel/cannonlake/siliconinit.c
@@ -0,0 +1,18 @@
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include "siliconinit.h"
+
+void silicon_init(bool s3wake)
+{
+ fsp_silicon_init(s3wake);
+}
+
+void display_fvi_version_hob(void)
+{
+ fsp_display_fvi_version_hob();
+}
+
+void soc_fsps_load(bool s3wake)
+{
+ fsps_load(s3wake);
+}
diff --git a/src/soc/intel/cannonlake/siliconinit.h b/src/soc/intel/cannonlake/siliconinit.h
new file mode 100644
index 0000000..dad9026
--- /dev/null
+++ b/src/soc/intel/cannonlake/siliconinit.h
@@ -0,0 +1,3 @@
+void silicon_init(bool s3wake);
+void display_fvi_version_hob(void);
+void soc_fsps_load(bool s3wake);
diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c
index fff68c7..5aa36d5 100644
--- a/src/soc/intel/cannonlake/vr_config.c
+++ b/src/soc/intel/cannonlake/vr_config.c
@@ -14,7 +14,6 @@
*
*/
-#include <fsp/api.h>
#include <soc/ramstage.h>
#include <soc/vr_config.h>
diff --git a/src/soc/intel/common/basecode/include/intelbasecode/memmap.h b/src/soc/intel/common/basecode/include/intelbasecode/memmap.h
new file mode 100644
index 0000000..965bce6
--- /dev/null
+++ b/src/soc/intel/common/basecode/include/intelbasecode/memmap.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _COMMON_MEMMAP_H_
+#define _COMMON_MEMMAP_H_
+
+#include <types.h>
+
+/*
+ * mmap_region_granularity must to return a size which is a positive non-zero
+ * integer multiple of the SMM size when SMM is in use. When not using SMM,
+ * this value should be set to 8 MiB.
+ */
+size_t mmap_region_granularity(void);
+
+/* Fills in the arguments for the entire SMM region covered by chipset
+ * protections. e.g. TSEG. */
+void smm_region(void **start, size_t *size);
+
+enum {
+ /* SMM handler area. */
+ SMM_SUBREGION_HANDLER,
+ /* SMM cache region. */
+ SMM_SUBREGION_CACHE,
+ /* Chipset specific area. */
+ SMM_SUBREGION_CHIPSET,
+ /* Total sub regions supported. */
+ SMM_SUBREGION_NUM,
+};
+
+/* Fills in the start and size for the requested SMM subregion. Returns
+ * 0 on susccess, < 0 on failure. */
+int smm_subregion(int sub, void **start, size_t *size);
+
+#endif /* _COMMON_MEMMAP_H_ */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I557b8001a2f59220a9da096100b601c9bd8764ee
Gerrit-Change-Number: 28674
Gerrit-PatchSet: 1
Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi at intel.com>
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