<p>Rizwan Qureshi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28674">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: [WIP] Make FSP optional Completely<br><br>Change-Id: I557b8001a2f59220a9da096100b601c9bd8764ee<br>Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com><br>---<br>M src/lib/coreboot_table.c<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/chip.c<br>M src/soc/intel/cannonlake/cpu.c<br>A src/soc/intel/cannonlake/fsp_igd_bar.c<br>A src/soc/intel/cannonlake/fsp_rst_handle.c<br>M src/soc/intel/cannonlake/graphics.c<br>M src/soc/intel/cannonlake/include/soc/ramstage.h<br>M src/soc/intel/cannonlake/include/soc/romstage.h<br>M src/soc/intel/cannonlake/include/soc/smm.h<br>M src/soc/intel/cannonlake/include/soc/vr_config.h<br>M src/soc/intel/cannonlake/memmap.c<br>M src/soc/intel/cannonlake/reset.c<br>M src/soc/intel/cannonlake/romstage/Makefile.inc<br>A src/soc/intel/cannonlake/romstage/dimminfo.c<br>A src/soc/intel/cannonlake/romstage/dimminfo.h<br>A src/soc/intel/cannonlake/romstage/meminit.c<br>A src/soc/intel/cannonlake/romstage/meminit.h<br>M src/soc/intel/cannonlake/romstage/romstage.c<br>A src/soc/intel/cannonlake/siliconinit.c<br>A src/soc/intel/cannonlake/siliconinit.h<br>M src/soc/intel/cannonlake/vr_config.c<br>A src/soc/intel/common/basecode/include/intelbasecode/memmap.h<br>24 files changed, 325 insertions(+), 110 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28674/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c</span><br><span>index 62b3aaa..c83ff76 100644</span><br><span>--- a/src/lib/coreboot_table.c</span><br><span>+++ b/src/lib/coreboot_table.c</span><br><span>@@ -603,3 +603,8 @@</span><br><span> cbmem_list();</span><br><span> return (void *)cbtable_start;</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ die ("platform does not implement fill_lb_framebuffer");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index 5a74b6f..9152ee7 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -30,7 +30,7 @@</span><br><span> select BOOT_DEVICE_SUPPORTS_WRITES</span><br><span> select C_ENVIRONMENT_BOOTBLOCK</span><br><span> select CACHE_MRC_SETTINGS</span><br><span style="color: hsl(0, 100%, 40%);">- select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM</span><br><span style="color: hsl(120, 100%, 40%);">+# select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM</span><br><span> select COMMON_FADT</span><br><span> select CPU_INTEL_FIRMWARE_INTERFACE_TABLE</span><br><span> select GENERIC_GPIO_LIB</span><br><span>@@ -46,7 +46,7 @@</span><br><span> select MRC_SETTINGS_PROTECT</span><br><span> select PARALLEL_MP</span><br><span> select PARALLEL_MP_AP_WORK</span><br><span style="color: hsl(0, 100%, 40%);">- select PLATFORM_USES_FSP2_0</span><br><span style="color: hsl(120, 100%, 40%);">+# select PLATFORM_USES_FSP2_0</span><br><span> select POSTCAR_CONSOLE</span><br><span> select POSTCAR_STAGE</span><br><span> select REG_SCRIPT</span><br><span>@@ -74,8 +74,9 @@</span><br><span> select TSC_MONOTONIC_TIMER</span><br><span> select UDELAY_TSC</span><br><span> select UDK_2017_BINDING</span><br><span style="color: hsl(0, 100%, 40%);">- select DISPLAY_FSP_VERSION_INFO</span><br><span style="color: hsl(0, 100%, 40%);">- select FSP_PARAM_OVERRIDE</span><br><span style="color: hsl(120, 100%, 40%);">+# select DISPLAY_FSP_VERSION_INFO</span><br><span style="color: hsl(120, 100%, 40%);">+# select FSP_PARAM_OVERRIDE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BASECODE</span><br><span> </span><br><span> config UART_DEBUG</span><br><span> bool "Enable UART debug port."</span><br><span>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>index 761fe81..c453dc0 100644</span><br><span>--- a/src/soc/intel/cannonlake/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>@@ -23,6 +23,7 @@</span><br><span> bootblock-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span> romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_rst_handle.c</span><br><span> romstage-y += gpio.c</span><br><span> romstage-y += gspi.c</span><br><span> romstage-y += i2c.c</span><br><span>@@ -37,6 +38,7 @@</span><br><span> ramstage-y += chip.c</span><br><span> ramstage-y += cpu.c</span><br><span> ramstage-y += finalize.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_rst_handle.c</span><br><span> ramstage-$(CONFIG_FSP_PARAM_OVERRIDE) += fsp_params.c</span><br><span> ramstage-y += gpio.c</span><br><span> ramstage-y += graphics.c</span><br><span>@@ -55,8 +57,9 @@</span><br><span> ramstage-y += spi.c</span><br><span> ramstage-y += systemagent.c</span><br><span> ramstage-$(CONFIG_UART_DEBUG) += uart.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += vr_config.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += vr_config.c</span><br><span> ramstage-y += sd.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += siliconinit.c</span><br><span> </span><br><span> smm-y += gpio.c</span><br><span> smm-y += p2sb.c</span><br><span>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c</span><br><span>index 0c0a05d..4c2f5e5 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip.c</span><br><span>@@ -18,8 +18,6 @@</span><br><span> #include <console/console.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <fsp/api.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <fsp/util.h></span><br><span> #include <intelblocks/acpi.h></span><br><span> #include <intelblocks/chip.h></span><br><span> #include <intelblocks/xdci.h></span><br><span>@@ -28,6 +26,7 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/ramstage.h></span><br><span> #include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "siliconinit.h"</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span> const char *soc_acpi_name(const struct device *dev)</span><br><span>@@ -98,10 +97,10 @@</span><br><span> void soc_init_pre_device(void *chip_info)</span><br><span> {</span><br><span> /* Perform silicon specific init. */</span><br><span style="color: hsl(0, 100%, 40%);">- fsp_silicon_init(romstage_handoff_is_resume());</span><br><span style="color: hsl(120, 100%, 40%);">+ silicon_init(romstage_handoff_is_resume());</span><br><span> </span><br><span> /* Display FIRMWARE_VERSION_INFO_HOB */</span><br><span style="color: hsl(0, 100%, 40%);">- fsp_display_fvi_version_hob();</span><br><span style="color: hsl(120, 100%, 40%);">+ display_fvi_version_hob();</span><br><span> }</span><br><span> </span><br><span> static void pci_domain_set_resources(struct device *dev)</span><br><span>@@ -140,3 +139,13 @@</span><br><span> .enable_dev = &soc_enable,</span><br><span> .init = &soc_init_pre_device,</span><br><span> };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__weak void display_fvi_version_hob(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ die("No FSP to run display_fvi_version_hob");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__weak void silicon_init(bool s3wake)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ die("No FSP to run silicon_init");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c</span><br><span>index ba87045..a59530c 100644</span><br><span>--- a/src/soc/intel/cannonlake/cpu.c</span><br><span>+++ b/src/soc/intel/cannonlake/cpu.c</span><br><span>@@ -28,10 +28,11 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pm.h></span><br><span> #include <soc/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "siliconinit.h"</span><br><span> </span><br><span> static void soc_fsp_load(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- fsps_load(romstage_handoff_is_resume());</span><br><span style="color: hsl(120, 100%, 40%);">+ soc_fsps_load(romstage_handoff_is_resume());</span><br><span> }</span><br><span> </span><br><span> static void configure_isst(void)</span><br><span>@@ -239,3 +240,8 @@</span><br><span> if (mp_init_with_smm(cpu_bus, &mp_ops))</span><br><span> printk(BIOS_ERR, "MP initialization failure.\n");</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__weak void soc_fsps_load(bool s3wake)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ die ("No FSP to run fsps_load");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/fsp_igd_bar.c b/src/soc/intel/cannonlake/fsp_igd_bar.c</span><br><span>new file mode 100644</span><br><span>index 0000000..ae81189</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/fsp_igd_bar.c</span><br><span>@@ -0,0 +1,23 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016-2017 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/graphics.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t fsp_soc_get_igd_bar(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return graphics_get_memory_base();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/fsp_rst_handle.c b/src/soc/intel/cannonlake/fsp_rst_handle.c</span><br><span>new file mode 100644</span><br><span>index 0000000..8069a1e</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/fsp_rst_handle.c</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <reset.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void chipset_handle_reset(uint32_t status)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (status) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "GLOBAL RESET!!\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ do_global_reset();</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "unhandled reset type %x\n", status);</span><br><span style="color: hsl(120, 100%, 40%);">+ die("unknown reset type");</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c</span><br><span>index 58f87f7..bae9dd5 100644</span><br><span>--- a/src/soc/intel/cannonlake/graphics.c</span><br><span>+++ b/src/soc/intel/cannonlake/graphics.c</span><br><span>@@ -16,18 +16,12 @@</span><br><span> </span><br><span> #include <arch/acpigen.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <fsp/util.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <drivers/intel/gma/i915_reg.h></span><br><span> #include <drivers/intel/gma/opregion.h></span><br><span> #include <intelblocks/graphics.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-uintptr_t fsp_soc_get_igd_bar(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return graphics_get_memory_base();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void graphics_soc_init(struct device *dev)</span><br><span> {</span><br><span> uint32_t ddi_buf_ctl;</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h</span><br><span>index 4a96185..e3953d2 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/ramstage.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/ramstage.h</span><br><span>@@ -19,10 +19,13 @@</span><br><span> </span><br><span> #include <chip.h></span><br><span> #include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0)</span><br><span> #include <fsp/api.h></span><br><span> #include <fsp/util.h></span><br><span> </span><br><span> void mainboard_silicon_init_params(FSP_S_CONFIG *params);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void soc_init_pre_device(void *chip_info);</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h</span><br><span>index 6faf110..a846e26 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/romstage.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/romstage.h</span><br><span>@@ -19,9 +19,13 @@</span><br><span> </span><br><span> #include <arch/cpu.h></span><br><span> #include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0)</span><br><span> #include <fsp/api.h></span><br><span> </span><br><span> void mainboard_memory_init_params(FSPM_UPD *mupd);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void systemagent_early_init(void);</span><br><span> </span><br><span> /* Board type */</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h</span><br><span>index 9121ac3..69766c8 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/smm.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/smm.h</span><br><span>@@ -19,7 +19,7 @@</span><br><span> </span><br><span> #include <stdint.h></span><br><span> #include <cpu/x86/msr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <fsp/memmap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/memmap.h></span><br><span> #include <soc/gpio.h></span><br><span> </span><br><span> struct ied_header {</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h</span><br><span>index 385767d..b993782 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/vr_config.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/vr_config.h</span><br><span>@@ -18,8 +18,6 @@</span><br><span> #ifndef _SOC_VR_CONFIG_H_</span><br><span> #define _SOC_VR_CONFIG_H_</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <fsp/api.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> struct vr_config {</span><br><span> </span><br><span> /* The below settings will take effect when this is set to 1</span><br><span>diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c</span><br><span>index 64e07be..aa037f0 100644</span><br><span>--- a/src/soc/intel/cannonlake/memmap.c</span><br><span>+++ b/src/soc/intel/cannonlake/memmap.c</span><br><span>@@ -21,7 +21,7 @@</span><br><span> #include <console/console.h></span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/memmap.h></span><br><span> #include <intelblocks/ebda.h></span><br><span> #include <intelblocks/systemagent.h></span><br><span> #include <soc/pci_devs.h></span><br><span>diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c</span><br><span>index 140fbff..bc3d82b 100644</span><br><span>--- a/src/soc/intel/cannonlake/reset.c</span><br><span>+++ b/src/soc/intel/cannonlake/reset.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #include <console/console.h></span><br><span> #include <intelblocks/cse.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <fsp/util.h></span><br><span> #include <reset.h></span><br><span> #include <string.h></span><br><span> #include <timer.h></span><br><span>@@ -88,17 +87,3 @@</span><br><span> pmc_global_reset_enable(1);</span><br><span> hard_reset();</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-void chipset_handle_reset(uint32_t status)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- switch (status) {</span><br><span style="color: hsl(0, 100%, 40%);">- case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "GLOBAL RESET!!\n");</span><br><span style="color: hsl(0, 100%, 40%);">- do_global_reset();</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- default:</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "unhandled reset type %x\n", status);</span><br><span style="color: hsl(0, 100%, 40%);">- die("unknown reset type");</span><br><span style="color: hsl(0, 100%, 40%);">- break;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc</span><br><span>index ab3e8e2..195e7aa 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/Makefile.inc</span><br><span>@@ -17,3 +17,4 @@</span><br><span> romstage-y += romstage.c</span><br><span> romstage-$(CONFIG_FSP_PARAM_OVERRIDE) += fsp_params.c</span><br><span> romstage-y += systemagent.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += meminit.c</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/dimminfo.c b/src/soc/intel/cannonlake/romstage/dimminfo.c</span><br><span>new file mode 100644</span><br><span>index 0000000..2110540</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/dimminfo.c</span><br><span>@@ -0,0 +1,90 @@</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include "dimminfo.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define FSP_SMBIOS_MEMORY_INFO_GUID \</span><br><span style="color: hsl(120, 100%, 40%);">+{ \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Save the DIMM information for SMBIOS table 17 */</span><br><span style="color: hsl(120, 100%, 40%);">+void save_dimm_info(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int channel, dimm, dimm_max, index;</span><br><span style="color: hsl(120, 100%, 40%);">+ size_t hob_size;</span><br><span style="color: hsl(120, 100%, 40%);">+ const CONTROLLER_INFO *ctrlr_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ const CHANNEL_INFO *channel_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ const DIMM_INFO *src_dimm;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct dimm_info *dest_dimm;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct memory_info *mem_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ const MEMORY_INFO_DATA_HOB *memory_info_hob;</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint8_t smbios_memory_info_guid[16] =</span><br><span style="color: hsl(120, 100%, 40%);">+ FSP_SMBIOS_MEMORY_INFO_GUID;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Locate the memory info HOB, presence validated by raminit */</span><br><span style="color: hsl(120, 100%, 40%);">+ memory_info_hob = fsp_find_extension_hob_by_guid(</span><br><span style="color: hsl(120, 100%, 40%);">+ smbios_memory_info_guid,</span><br><span style="color: hsl(120, 100%, 40%);">+ &hob_size);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (memory_info_hob == NULL || hob_size == 0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Allocate CBMEM area for DIMM information used to populate SMBIOS</span><br><span style="color: hsl(120, 100%, 40%);">+ * table 17</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (mem_info == NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ memset(mem_info, 0, sizeof(*mem_info));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Describe the first N DIMMs in the system */</span><br><span style="color: hsl(120, 100%, 40%);">+ index = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ dimm_max = ARRAY_SIZE(mem_info->dimm);</span><br><span style="color: hsl(120, 100%, 40%);">+ ctrlr_info = &memory_info_hob->Controller[0];</span><br><span style="color: hsl(120, 100%, 40%);">+ for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ channel_info = &ctrlr_info->ChannelInfo[channel];</span><br><span style="color: hsl(120, 100%, 40%);">+ if (channel_info->Status != CHANNEL_PRESENT)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+ for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ src_dimm = &channel_info->DimmInfo[dimm];</span><br><span style="color: hsl(120, 100%, 40%);">+ dest_dimm = &mem_info->dimm[index];</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (src_dimm->Status != DIMM_PRESENT)</span><br><span style="color: hsl(120, 100%, 40%);">+ continue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Populate the DIMM information */</span><br><span style="color: hsl(120, 100%, 40%);">+ dimm_info_fill(dest_dimm,</span><br><span style="color: hsl(120, 100%, 40%);">+ src_dimm->DimmCapacity,</span><br><span style="color: hsl(120, 100%, 40%);">+ memory_info_hob->MemoryType,</span><br><span style="color: hsl(120, 100%, 40%);">+ memory_info_hob->ConfiguredMemoryClockSpeed,</span><br><span style="color: hsl(120, 100%, 40%);">+ channel_info->ChannelId,</span><br><span style="color: hsl(120, 100%, 40%);">+ src_dimm->DimmId,</span><br><span style="color: hsl(120, 100%, 40%);">+ (const char *)src_dimm->ModulePartNum,</span><br><span style="color: hsl(120, 100%, 40%);">+ sizeof(src_dimm->ModulePartNum),</span><br><span style="color: hsl(120, 100%, 40%);">+ memory_info_hob->DataWidth);</span><br><span style="color: hsl(120, 100%, 40%);">+ index++;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ mem_info->dimm_cnt = index;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/dimminfo.h b/src/soc/intel/cannonlake/romstage/dimminfo.h</span><br><span>new file mode 100644</span><br><span>index 0000000..237b331</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/dimminfo.h</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+void save_dimm_info(void);</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/meminit.c b/src/soc/intel/cannonlake/romstage/meminit.c</span><br><span>new file mode 100644</span><br><span>index 0000000..b956482</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/meminit.c</span><br><span>@@ -0,0 +1,40 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/early_variables.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <chip.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/mtrr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <compiler.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/cse.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pmclib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <memory_info.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/intel/common/smbios.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/romstage.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "meminit.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void memory_init(bool s3wake)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ fsp_memory_init(s3wake);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/meminit.h b/src/soc/intel/cannonlake/romstage/meminit.h</span><br><span>new file mode 100644</span><br><span>index 0000000..233948b</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/meminit.h</span><br><span>@@ -0,0 +1,15 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void memory_init(bool s3wake);</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>index 113798d..071c6cc 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/romstage.c</span><br><span>@@ -21,7 +21,6 @@</span><br><span> #include <cbmem.h></span><br><span> #include <compiler.h></span><br><span> #include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <fsp/util.h></span><br><span> #include <intelblocks/cse.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span> #include <memory_info.h></span><br><span>@@ -32,81 +31,11 @@</span><br><span> #include <soc/romstage.h></span><br><span> #include <string.h></span><br><span> #include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "meminit.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "dimminfo.h"</span><br><span> </span><br><span> static struct chipset_power_state power_state CAR_GLOBAL;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define FSP_SMBIOS_MEMORY_INFO_GUID \</span><br><span style="color: hsl(0, 100%, 40%);">-{ \</span><br><span style="color: hsl(0, 100%, 40%);">- 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \</span><br><span style="color: hsl(0, 100%, 40%);">- 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* Save the DIMM information for SMBIOS table 17 */</span><br><span style="color: hsl(0, 100%, 40%);">-static void save_dimm_info(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- int channel, dimm, dimm_max, index;</span><br><span style="color: hsl(0, 100%, 40%);">- size_t hob_size;</span><br><span style="color: hsl(0, 100%, 40%);">- const CONTROLLER_INFO *ctrlr_info;</span><br><span style="color: hsl(0, 100%, 40%);">- const CHANNEL_INFO *channel_info;</span><br><span style="color: hsl(0, 100%, 40%);">- const DIMM_INFO *src_dimm;</span><br><span style="color: hsl(0, 100%, 40%);">- struct dimm_info *dest_dimm;</span><br><span style="color: hsl(0, 100%, 40%);">- struct memory_info *mem_info;</span><br><span style="color: hsl(0, 100%, 40%);">- const MEMORY_INFO_DATA_HOB *memory_info_hob;</span><br><span style="color: hsl(0, 100%, 40%);">- const uint8_t smbios_memory_info_guid[16] =</span><br><span style="color: hsl(0, 100%, 40%);">- FSP_SMBIOS_MEMORY_INFO_GUID;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Locate the memory info HOB, presence validated by raminit */</span><br><span style="color: hsl(0, 100%, 40%);">- memory_info_hob = fsp_find_extension_hob_by_guid(</span><br><span style="color: hsl(0, 100%, 40%);">- smbios_memory_info_guid,</span><br><span style="color: hsl(0, 100%, 40%);">- &hob_size);</span><br><span style="color: hsl(0, 100%, 40%);">- if (memory_info_hob == NULL || hob_size == 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Allocate CBMEM area for DIMM information used to populate SMBIOS</span><br><span style="color: hsl(0, 100%, 40%);">- * table 17</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));</span><br><span style="color: hsl(0, 100%, 40%);">- if (mem_info == NULL) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- memset(mem_info, 0, sizeof(*mem_info));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Describe the first N DIMMs in the system */</span><br><span style="color: hsl(0, 100%, 40%);">- index = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_max = ARRAY_SIZE(mem_info->dimm);</span><br><span style="color: hsl(0, 100%, 40%);">- ctrlr_info = &memory_info_hob->Controller[0];</span><br><span style="color: hsl(0, 100%, 40%);">- for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {</span><br><span style="color: hsl(0, 100%, 40%);">- channel_info = &ctrlr_info->ChannelInfo[channel];</span><br><span style="color: hsl(0, 100%, 40%);">- if (channel_info->Status != CHANNEL_PRESENT)</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">- for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {</span><br><span style="color: hsl(0, 100%, 40%);">- src_dimm = &channel_info->DimmInfo[dimm];</span><br><span style="color: hsl(0, 100%, 40%);">- dest_dimm = &mem_info->dimm[index];</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (src_dimm->Status != DIMM_PRESENT)</span><br><span style="color: hsl(0, 100%, 40%);">- continue;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Populate the DIMM information */</span><br><span style="color: hsl(0, 100%, 40%);">- dimm_info_fill(dest_dimm,</span><br><span style="color: hsl(0, 100%, 40%);">- src_dimm->DimmCapacity,</span><br><span style="color: hsl(0, 100%, 40%);">- memory_info_hob->MemoryType,</span><br><span style="color: hsl(0, 100%, 40%);">- memory_info_hob->ConfiguredMemoryClockSpeed,</span><br><span style="color: hsl(0, 100%, 40%);">- channel_info->ChannelId,</span><br><span style="color: hsl(0, 100%, 40%);">- src_dimm->DimmId,</span><br><span style="color: hsl(0, 100%, 40%);">- (const char *)src_dimm->ModulePartNum,</span><br><span style="color: hsl(0, 100%, 40%);">- sizeof(src_dimm->ModulePartNum),</span><br><span style="color: hsl(0, 100%, 40%);">- memory_info_hob->DataWidth);</span><br><span style="color: hsl(0, 100%, 40%);">- index++;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- mem_info->dimm_cnt = index;</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> asmlinkage void car_stage_entry(void)</span><br><span> {</span><br><span> bool s3wake;</span><br><span>@@ -123,7 +52,7 @@</span><br><span> </span><br><span> timestamp_add_now(TS_START_ROMSTAGE);</span><br><span> s3wake = pmc_fill_power_state(ps) == ACPI_S3;</span><br><span style="color: hsl(0, 100%, 40%);">- fsp_memory_init(s3wake);</span><br><span style="color: hsl(120, 100%, 40%);">+ memory_init(s3wake);</span><br><span> pmc_set_disb();</span><br><span> if (!s3wake)</span><br><span> save_dimm_info();</span><br><span>@@ -146,3 +75,13 @@</span><br><span> </span><br><span> run_postcar_phase(&pcf);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__weak void save_dimm_info()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "%s weak function called\n", __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+__weak void memory_init(bool s3wake)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ die("No FSP to run memory_init");</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/siliconinit.c b/src/soc/intel/cannonlake/siliconinit.c</span><br><span>new file mode 100644</span><br><span>index 0000000..892c2ff</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/siliconinit.c</span><br><span>@@ -0,0 +1,18 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/api.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "siliconinit.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void silicon_init(bool s3wake)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ fsp_silicon_init(s3wake);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void display_fvi_version_hob(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ fsp_display_fvi_version_hob();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_fsps_load(bool s3wake)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ fsps_load(s3wake);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/siliconinit.h b/src/soc/intel/cannonlake/siliconinit.h</span><br><span>new file mode 100644</span><br><span>index 0000000..dad9026</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/siliconinit.h</span><br><span>@@ -0,0 +1,3 @@</span><br><span style="color: hsl(120, 100%, 40%);">+void silicon_init(bool s3wake);</span><br><span style="color: hsl(120, 100%, 40%);">+void display_fvi_version_hob(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_fsps_load(bool s3wake);</span><br><span>diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c</span><br><span>index fff68c7..5aa36d5 100644</span><br><span>--- a/src/soc/intel/cannonlake/vr_config.c</span><br><span>+++ b/src/soc/intel/cannonlake/vr_config.c</span><br><span>@@ -14,7 +14,6 @@</span><br><span> *</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#include <fsp/api.h></span><br><span> #include <soc/ramstage.h></span><br><span> #include <soc/vr_config.h></span><br><span> </span><br><span>diff --git a/src/soc/intel/common/basecode/include/intelbasecode/memmap.h b/src/soc/intel/common/basecode/include/intelbasecode/memmap.h</span><br><span>new file mode 100644</span><br><span>index 0000000..965bce6</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/basecode/include/intelbasecode/memmap.h</span><br><span>@@ -0,0 +1,47 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015-2016 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _COMMON_MEMMAP_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _COMMON_MEMMAP_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * mmap_region_granularity must to return a size which is a positive non-zero</span><br><span style="color: hsl(120, 100%, 40%);">+ * integer multiple of the SMM size when SMM is in use. When not using SMM,</span><br><span style="color: hsl(120, 100%, 40%);">+ * this value should be set to 8 MiB.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+size_t mmap_region_granularity(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Fills in the arguments for the entire SMM region covered by chipset</span><br><span style="color: hsl(120, 100%, 40%);">+ * protections. e.g. TSEG. */</span><br><span style="color: hsl(120, 100%, 40%);">+void smm_region(void **start, size_t *size);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SMM handler area. */</span><br><span style="color: hsl(120, 100%, 40%);">+ SMM_SUBREGION_HANDLER,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SMM cache region. */</span><br><span style="color: hsl(120, 100%, 40%);">+ SMM_SUBREGION_CACHE,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Chipset specific area. */</span><br><span style="color: hsl(120, 100%, 40%);">+ SMM_SUBREGION_CHIPSET,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Total sub regions supported. */</span><br><span style="color: hsl(120, 100%, 40%);">+ SMM_SUBREGION_NUM,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Fills in the start and size for the requested SMM subregion. Returns</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 on susccess, < 0 on failure. */</span><br><span style="color: hsl(120, 100%, 40%);">+int smm_subregion(int sub, void **start, size_t *size);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _COMMON_MEMMAP_H_ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28674">change 28674</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28674"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I557b8001a2f59220a9da096100b601c9bd8764ee </div>
<div style="display:none"> Gerrit-Change-Number: 28674 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>