[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: [WIP] Make FSP completely optional

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has uploaded a new patch set (#2). ( https://review.coreboot.org/28674 )

Change subject: soc/intel/cannonlake: [WIP] Make FSP completely optional
......................................................................

soc/intel/cannonlake: [WIP] Make FSP completely optional

Change-Id: I557b8001a2f59220a9da096100b601c9bd8764ee
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
M src/lib/coreboot_table.c
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/cpu.c
A src/soc/intel/cannonlake/fsp_igd_bar.c
A src/soc/intel/cannonlake/fsp_rst_handle.c
M src/soc/intel/cannonlake/graphics.c
M src/soc/intel/cannonlake/include/soc/ramstage.h
M src/soc/intel/cannonlake/include/soc/romstage.h
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/include/soc/vr_config.h
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/reset.c
M src/soc/intel/cannonlake/romstage/Makefile.inc
A src/soc/intel/cannonlake/romstage/dimminfo.c
A src/soc/intel/cannonlake/romstage/dimminfo.h
A src/soc/intel/cannonlake/romstage/meminit.c
A src/soc/intel/cannonlake/romstage/meminit.h
M src/soc/intel/cannonlake/romstage/romstage.c
A src/soc/intel/cannonlake/siliconinit.c
A src/soc/intel/cannonlake/siliconinit.h
M src/soc/intel/cannonlake/vr_config.c
A src/soc/intel/common/basecode/include/intelbasecode/memmap.h
24 files changed, 325 insertions(+), 110 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28674/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I557b8001a2f59220a9da096100b601c9bd8764ee
Gerrit-Change-Number: 28674
Gerrit-PatchSet: 2
Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi at intel.com>
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