[coreboot-gerrit] Change in ...coreboot[master]: mb/intel/kblrvp: Add new Kaby lake RVP11 support
PraveenX Hodagatta Pranesh (Code Review)
gerrit at coreboot.org
Fri Nov 23 10:01:52 CET 2018
PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29809
Change subject: mb/intel/kblrvp: Add new Kaby lake RVP11 support
......................................................................
mb/intel/kblrvp: Add new Kaby lake RVP11 support
The RVP11 is a dual-channel DDR4 SO-DIMM on skylake H platform.
This patch add following chages
- Add devicetree.cb for RVP11 in the variants path.
- Select cannonlake PCH-H chipset config for RVP11.
- Add GPIO table as per board schematics.
- Add audio verb table for RVP11.
- Set the UserBd UPD to BOARD_TYPE_DESKTOP.
BUG=None
TEST= Build and flash, confirm boot into yocto OS on KBL RVP11
platform. verified PCI, USB, ethernet, SATA, display,
audio and power functionalities.
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh at intel.com>
Change-Id: Id86f56df06795601cc9d7830766e54396d218e00
---
M src/mainboard/intel/kblrvp/Kconfig
M src/mainboard/intel/kblrvp/Kconfig.name
M src/mainboard/intel/kblrvp/ramstage.c
M src/mainboard/intel/kblrvp/romstage.c
M src/mainboard/intel/kblrvp/smihandler.c
A src/mainboard/intel/kblrvp/variants/rvp11/devicetree.cb
A src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h
A src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h
8 files changed, 806 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/29809/1
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index bf17c4b..1af4e30 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 || BOARD_INTEL_KBLRVP8
+if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 || BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
@@ -8,9 +8,9 @@
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_SMI_HANDLER
- select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_KBLRVP8
select SOC_INTEL_SKYLAKE
- select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8
+ select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11
select MAINBOARD_USES_FSP2_0
select MAINBOARD_HAS_CHROMEOS
select GENERIC_SPD_BIN
@@ -32,6 +32,7 @@
default "rvp3" if BOARD_INTEL_KBLRVP3
default "rvp7" if BOARD_INTEL_KBLRVP7
default "rvp8" if BOARD_INTEL_KBLRVP8
+ default "rvp11" if BOARD_INTEL_KBLRVP11
config MAINBOARD_PART_NUMBER
string
@@ -64,6 +65,7 @@
default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp3.bin" if BOARD_INTEL_KBLRVP3
default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp7.bin" if BOARD_INTEL_KBLRVP7
default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp8.bin" if BOARD_INTEL_KBLRVP8
+ default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp11.bin" if BOARD_INTEL_KBLRVP11
config ME_BIN_PATH
string
@@ -71,6 +73,7 @@
default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp3.bin" if BOARD_INTEL_KBLRVP3
default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp7.bin" if BOARD_INTEL_KBLRVP7
default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp8.bin" if BOARD_INTEL_KBLRVP8
+ default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp11.bin" if BOARD_INTEL_KBLRVP11
config PRERAM_CBMEM_CONSOLE_SIZE
hex
@@ -78,5 +81,5 @@
config DIMM_SPD_SIZE
int
- default 512 if BOARD_INTEL_KBLRVP8 #DDR4
+ default 512 if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 #DDR4
endif
diff --git a/src/mainboard/intel/kblrvp/Kconfig.name b/src/mainboard/intel/kblrvp/Kconfig.name
index b275b17..df65e32 100644
--- a/src/mainboard/intel/kblrvp/Kconfig.name
+++ b/src/mainboard/intel/kblrvp/Kconfig.name
@@ -4,3 +4,5 @@
bool "Kabylake DDR3L RVP7"
config BOARD_INTEL_KBLRVP8
bool "Kabylake DDR4 RVP8"
+config BOARD_INTEL_KBLRVP11
+ bool "Kabylake DDR4 RVP11"
diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c
index 1e6aa11..453a4da 100644
--- a/src/mainboard/intel/kblrvp/ramstage.c
+++ b/src/mainboard/intel/kblrvp/ramstage.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corporation
+ * Copyright (C) 2016-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -32,6 +32,9 @@
static void ioexpander_init(void *unused)
{
+ #if IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP11)
+
+ #else
printk(BIOS_DEBUG, "Programming TCA6424A I/O expander\n");
/* I/O Expander 1, Port 0 Data */
@@ -61,6 +64,7 @@
/* Port 0 Configuration */
i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_1_ADDR, IO_EXPANDER_P0CONF,
0x00);
+ #endif
}
diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c
index a29a4af..fe3b59c 100644
--- a/src/mainboard/intel/kblrvp/romstage.c
+++ b/src/mainboard/intel/kblrvp/romstage.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corporation.
+ * Copyright (C) 2016-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -59,13 +59,15 @@
mem_cfg->MemorySpdDataLen = blk.len;
mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2];
- if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) {
+ if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8) ||
+ IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP11)) {
mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1];
mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];
}
}
mupd->FspmTestConfig.DmiVc1 = 1;
- if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8))
+ if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8) ||
+ IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP11))
mem_cfg->UserBd = BOARD_TYPE_DESKTOP;
}
diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c
index 6006767..1bc2d82 100644
--- a/src/mainboard/intel/kblrvp/smihandler.c
+++ b/src/mainboard/intel/kblrvp/smihandler.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2016-2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -52,9 +52,10 @@
if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8))
return;
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ #if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
if (gpi_status_get(sts, EC_SMI_GPI))
chromeec_smi_process_events();
+ #endif
}
void mainboard_smi_sleep(u8 slp_typ)
@@ -67,8 +68,9 @@
int mainboard_smi_apmc(u8 apmc)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ #if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
+ #endif
return 0;
}
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/devicetree.cb
new file mode 100644
index 0000000..eb2ce5d
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/devicetree.cb
@@ -0,0 +1,307 @@
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s5_enable_ac" = "0"
+ register "deep_s5_enable_dc" = "0"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command range is in 0x800-0x8ff
+ register "gen1_dec" = "0x00fc0801"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
+ # FSP Configuration
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "0"
+ register "IoBufferOwnership" = "0"
+ register "SmbusEnable" = "1"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "0"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "0"
+ register "Heci3Enabled" = "0"
+
+ register "SaGv" = "3"
+ register "PmTimerDisabled" = "0"
+
+ # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
+ # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
+ register "PmConfigSlpS3MinAssert" = "0x02"
+
+ # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
+ register "PmConfigSlpS4MinAssert" = "0x04"
+
+ # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
+ register "PmConfigSlpSusMinAssert" = "0x03"
+
+ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
+ register "PmConfigSlpAMinAssert" = "0x03"
+
+ # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
+ register "SerialIrqConfigSirqEnable" = "0x01"
+ register "SerialIrqConfigSirqMode" = "0x01"
+
+ # VR Settings Configuration for 4 Domains
+ #+----------------+-------+-------+-------+-------+
+ #| Domain/Setting | SA | IA | GTUS | GTS |
+ #+----------------+-------+-------+-------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-------+-------+-------+-------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x10, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x1C, \
+ .voltage_limit = 0x5F0 \
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x88, \
+ .voltage_limit = 0x5F0 \
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x8C ,\
+ .voltage_limit = 0x5F0 \
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x8C, \
+ .voltage_limit = 0x5F0 \
+ }"
+
+ # Enable PCIE slot
+ register "PcieRpEnable[5]" = "1"
+ register "PcieRpClkReqSupport[5]" = "1"
+ register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1
+ # RP6, uses uses CLK SRC 1
+ register "PcieRpClkSrcNumber[5]" = "1"
+
+ register "PcieRpEnable[6]" = "1"
+ register "PcieRpClkReqSupport[6]" = "1"
+ register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2
+ # RP7, uses uses CLK SRC 2
+ register "PcieRpClkSrcNumber[6]" = "2"
+
+ register "PcieRpEnable[7]" = "1"
+ register "PcieRpClkReqSupport[7]" = "1"
+ register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3
+ # RP8, uses uses CLK SRC 3
+ register "PcieRpClkSrcNumber[7]" = "3"
+
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4
+ # RP9, uses uses CLK SRC 4
+ register "PcieRpClkSrcNumber[8]" = "4"
+
+ register "PcieRpEnable[13]" = "1"
+ register "PcieRpClkReqSupport[13]" = "1"
+ register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5
+ # RP14, uses uses CLK SRC 5
+ register "PcieRpClkSrcNumber[13]" = "5"
+
+ register "PcieRpEnable[16]" = "1"
+ register "PcieRpClkReqSupport[16]" = "1"
+ register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7
+ # RP17, uses uses CLK SRC 7
+ register "PcieRpClkSrcNumber[16]" = "7"
+
+ register EnableLan = "1"
+
+ # USB related
+ register "SsicPortEnable" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
+ register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
+ register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor
+ register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
+ register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
+ register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
+ register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
+ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
+ register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
+
+
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
+
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+
+ register "pirqa_routing" = "0x0b"
+ register "pirqb_routing" = "0x0a"
+ register "pirqc_routing" = "0x0b"
+ register "pirqd_routing" = "0x0b"
+ register "pirqe_routing" = "0x0b"
+ register "pirqf_routing" = "0x0b"
+ register "pirqg_routing" = "0x0b"
+ register "pirqh_routing" = "0x0b"
+
+ register "PmTimerDisabled" = "0"
+
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable" = "{ \
+ [0] = 1, \
+ [1] = 1, \
+ [2] = 1, \
+ [3] = 1, \
+ [4] = 1, \
+ [5] = 1, \
+ [6] = 1, \
+ [7] = 1, \
+ }"
+ register "SerialIoDevMode" = "{ \
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C4] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart0] = PchSerialIoPci, \
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
+ }"
+
+ # PL2 override 60W
+ register "tdp_pl2_override" = "60"
+
+ # Power Limit Related
+ register "PowerLimit4" = "0"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Enable/Disable VMX feature
+ register "VmxEnable" = "0"
+
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 on end # I2C #0
+ device pci 15.1 on end # I2C #1
+ device pci 15.2 on end # I2C #2
+ device pci 15.3 on end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 on end # I2C #5
+ device pci 19.2 on end # I2C #4
+ device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 on end # UART #1
+ device pci 1e.2 on end # GSPI #0
+ device pci 1e.3 on end # GSPI #1
+ device pci 1e.4 off end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 off end # SDCard
+ device pci 1f.0 on
+ #chip drivers/pc80/tpm
+ # device pnp 0c31.0 on end
+ #end
+ #chip ec/google/chromeec
+ # device pnp 0c09.0 on end
+ #end
+ end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 on end # GbE
+ end
+end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h
new file mode 100644
index 0000000..d3224b2
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h
@@ -0,0 +1,275 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _GPIORVP11_H
+#define _GPIORVP11_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* EC in RW */
+#define GPIO_EC_IN_RW GPP_C6
+
+/* BIOS Flash Write Protect */
+#define GPIO_PCH_WP GPP_C23
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0 GPP_C12
+#define GPIO_MEM_CONFIG_1 GPP_C13
+#define GPIO_MEM_CONFIG_2 GPP_C14
+#define GPIO_MEM_CONFIG_3 GPP_C15
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE GPE0_LAN_WAK
+
+/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
+#define GPE_WLAN_WAKE GPE0_DW0_16
+
+/* Input device interrupt configuration */
+#define TOUCHPAD_INT_L GPP_B3_IRQ
+#define TOUCHSCREEN_INT_L GPP_E7_IRQ
+#define MIC_INT_L GPP_F10_IRQ
+
+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
+#define EC_SCI_GPI GPE0_DW2_16
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+
+static const struct pad_config gpio_table[] = {
+/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
+/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
+/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
+/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
+/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+/* ESPI ALERT */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF2),
+/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
+/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+/* EC_HID_INT */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP),
+/* ISH_KB_PROX_INT */ PAD_CFG_GPI(GPP_A12, NONE, DEEP),
+/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+/* SLP_S0ix_N */ PAD_CFG_GPO(GPP_A16, 1, DEEP),
+/* M.2 WLAN PWR EN */ PAD_CFG_GPO(GPP_A17, 1, DEEP),
+/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+/* GPP_A19 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
+/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
+/* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP),
+/* GPP_A23 */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP),
+
+/* screen lock */ PAD_CFG_GPI(GPP_B0, NONE, DEEP),
+/* Tch pnl pwren */ PAD_CFG_GPO(GPP_B1, 1, DEEP),
+/* HSJ_MIC_DET */
+/* BT_RF_kill */ PAD_CFG_GPO(GPP_B3, 1, DEEP),
+/* SNI_DRV_PCH */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1),
+/* M.2 BT UART wake */ PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP),
+/* WIFI_CLK_REQ */
+/* KEPLR_CLK_REQ */
+/* SRCCLKREQ3# */ /* GPP_B8 */
+/* SSD_CLK_REQ */
+/* SRCCLKREQ5# */ /* GPP_B10 */
+/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+/* GPP_B_14_SPKR */ PAD_CFG_GPI_ACPI_SMI(GPP_B14, NONE, DEEP, YES),
+/* GSPI0_CS# */ /* GPP_B15 */
+/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
+/* SSD_PCIE_WAKE */ PAD_CFG_GPO(GPP_B17, 1, DEEP),
+/* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 1, DEEP),
+/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
+/* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 1, DEEP),
+
+/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+/* SMBALERT# */ PAD_CFG_GPI(GPP_C2, NONE, DEEP),
+/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+/* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+/* USB_CTL */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+/* NFC_RST* */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
+/* EN_PP3300_KEPLER */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+/* PCH_MEM_CFG0 */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+/* PCH_MEM_CFG1 */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+/* PCH_MEM_CFG2 */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+/* PCH_MEM_CFG3 */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+/* TCH_PNL_PWREN */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
+/* SPI_WP_STATUS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
+
+/* ITCH_SPI_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
+/* ITCH_SPI_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
+/* ITCH_SPI_MISO_1 */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
+/* ITCH_SPI_MISO_0 */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
+/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
+/* EN_PP3300_DX_EMMC */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+/* EN_PP1800_DX_EMMC */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+/* TBD */
+/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 1, DEEP),
+/* USB_A1_ILIM_SEL */
+/* EN_PP3300_DX_CAM */
+/* EN_PP1800_DX_AUDIO */PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
+/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+/* ITCH_SPI_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
+/* ITCH_SPI_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
+/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+
+/* SPI_TPM_IRQ */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),
+/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF3),
+/* SSD_PEDET */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF3),
+/* CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1),
+/* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
+/* SATA_DEVSLP1 */ /* GPP_E5 */
+/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF3),
+/* TCH_PNL_INTR* */
+/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
+/* I2S2_TXD */ PAD_CFG_GPO(GPP_F2, 0, DEEP),
+/* I2S2_RXD */ PAD_CFG_GPO(GPP_F3, 1, DEEP),
+/* I2C2_SDA */ PAD_CFG_GPO(GPP_F4, 0, DEEP),
+/* I2C2_SCL */ PAD_CFG_GPI_APIC(GPP_F5, NONE, DEEP),
+/* I2C3_SDA */ PAD_CFG_GPO(GPP_F6, 0, DEEP),
+/* I2C3_SCL */ PAD_CFG_GPO(GPP_F7, 0, DEEP),
+/* I2C4_SDA */ PAD_CFG_GPI(GPP_F8, NONE, DEEP),
+/* I2C4_SDA */ PAD_CFG_GPI_APIC(GPP_F9, NONE, DEEP),
+/* AUDIO_IRQ */ PAD_CFG_GPI(GPP_F10, NONE, DEEP),
+/* I2C5_SCL */ PAD_CFG_GPI(GPP_F11, NONE, DEEP),
+/* EMMC_CMD */ PAD_CFG_GPI_ACPI_SCI(GPP_F12, NONE, DEEP, YES),
+/* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F13, NONE, DEEP),
+/* EMMC_DATA1 */ PAD_CFG_GPI(GPP_F14, NONE, DEEP),
+/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+/* EMMC_DATA4 */ PAD_CFG_GPO(GPP_F17, 1, DEEP),
+/* EMMC_DATA5 */ PAD_CFG_GPO(GPP_F18, 1, DEEP),
+/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+/* EMMC_CLK */ PAD_CFG_GPO(GPP_F22, 1, DEEP),
+/* GPP_F23 */
+
+/* SD_CMD */ PAD_CFG_GPI_APIC(GPP_G0, 20K_PD, DEEP),
+/* SD_DATA0 */ PAD_CFG_GPO(GPP_G1, 1, DEEP),
+/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
+/* SD_DATA2 */ PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES),
+/* SD_DATA3 */ PAD_CFG_GPO(GPP_G4, 0, DEEP),
+/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 0, DEEP),
+/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP),
+/* SD_WP */ PAD_CFG_GPI_APIC(GPP_G7, NONE, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_G8, 1, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_G9, 1, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_G10, 0, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_G11, 1, DEEP),
+/* TBD */ PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES),
+/* TBD */ PAD_CFG_GPO(GPP_G13, 1, DEEP),
+/* TBD */
+/* TBD */ PAD_CFG_GPO(GPP_G15, 1, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_G16, 0, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_G17, 1, DEEP),
+/* TBD */ PAD_CFG_GPI_ACPI_SCI(GPP_G18, NONE, DEEP, YES),
+/* TBD */
+/* TBD */ PAD_CFG_GPO(GPP_G20, 1, DEEP),
+/* TBD */ PAD_CFG_GPI_APIC(GPP_G21, 20K_PD, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_G22, 1, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_G23, 1, DEEP),
+
+/* SD_CMD */ PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),
+/* SD_DATA0 */
+/* SD_DATA1 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+/* SD_DATA2 */
+/* SD_DATA3 */ PAD_CFG_GPO(GPP_H4, 0, DEEP),
+/* SD_CD# */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+/* SD_CLK */ PAD_CFG_GPO(GPP_H6, 1, DEEP),
+/* SD_WP */ PAD_CFG_GPO(GPP_H7, 1, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_H8, 1, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_H9, 1, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_H10, 1, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_H11, 1, DEEP),
+/* TBD */
+/* TBD */ PAD_CFG_GPI(GPP_H13, NONE, DEEP),
+/* TBD */ PAD_CFG_GPI(GPP_H14, NONE, DEEP),
+/* TBD */ PAD_CFG_GPI(GPP_H15, NONE, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_H16, 1, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_H17, 1, DEEP),
+/* TBD */ PAD_CFG_GPO(GPP_H18, 1, DEEP),
+/* TBD */ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+/* TBD */ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
+/* TBD */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+/* TBD */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+/* TBD */ PAD_CFG_GPO(GPP_H23, 0, DEEP),
+
+/* SD_CMD */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
+/* SD_CMD */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
+/* SD_CMD */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
+/* SD_CMD */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),
+/* SD_CMD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
+/* SD_CMD */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
+/* SD_CMD */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
+/* SD_CMD */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
+/* SD_CMD */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
+/* SD_CMD */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
+/* SD_CMD */ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
+
+/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+ /* GPD7 */
+/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+};
+
+#endif
+#endif
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h
new file mode 100644
index 0000000..1312d9b
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien at zamaudio.com>
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+
+ 0x8086280B,
+ 0x00000000,
+ 0x00000005,
+
+ /*
+ * Display Audio Verb Table
+ * Enable the third converter and Pin first (NID 08h)
+ */
+ 0x00878101,
+ 0x00878101,
+ 0x00878101,
+ 0x00878101,
+
+ AZALIA_PIN_CFG(0, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(0, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(0, 0x07, 0x18560030),
+
+ /* Disable the third converter and third Pin (NID 08h) */
+ 0x00878100,
+ 0x00878100,
+ 0x00878100,
+ 0x00878100,
+
+ /* ALC 298 */
+ 0x10EC0298,
+ 0x00000000,
+ 0x00000023,
+
+ AZALIA_SUBVENDOR(0, 0x10EC109C),
+ AZALIA_PIN_CFG(0, 0x01, 0x00000000),
+ AZALIA_PIN_CFG(0, 0x12, 0x411111F0),
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x14, 0x9017011F),
+ AZALIA_PIN_CFG(0, 0x17, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x18, 0x03A11040),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111F0),
+ AZALIA_PIN_CFG(0, 0x1A, 0x411111F0),
+ AZALIA_PIN_CFG(0, 0x1D, 0x4066A22D),
+ AZALIA_PIN_CFG(0, 0x1E, 0x411111F0),
+ AZALIA_PIN_CFG(0, 0x21, 0x03211020),
+
+ /* Widget node 0x20 */
+ 0x0205004F,
+ 0x0204B009,
+ 0x02050050,
+ 0x02041000,
+ /* Widget node 0x20 - 1 */
+ 0x02050019,
+ 0x02040017,
+ 0x02050020,
+ 0x02040002,
+ /* Widget node 0x20 - 2 */
+ 0x0205008F,
+ 0x02041008,
+ 0x02050036,
+ 0x020462C0,
+ /* Widget node 0x20 - 3 */
+ 0x0205002B,
+ 0x02040D10,
+ 0x0205002D,
+ 0x02044020,
+ /* Widget node 0x20 - 4 */
+ 0x0205000E,
+ 0x02046F80,
+ 0x01771F90,
+ 0x01771F90,
+ /* Widget node 0x20 - 5 */
+ 0x02050079,
+ 0x02046800,
+ 0x02050079,
+ 0x02046800,
+
+ /* TI AMP settings */
+ 0x02050022,
+ 0x0204004C,
+ 0x02050023,
+ 0x02040000,
+ 0x02050025,
+ 0x02040000,
+ 0x02050026,
+ 0x0204B010,
+
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+
+ 0x02050022,
+ 0x0204004C,
+ 0x02050023,
+ 0x02040002,
+ 0x02050025,
+ 0x02040011,
+ 0x02050026,
+ 0x0204B010,
+
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+
+ 0x02050022,
+ 0x0204004C,
+ 0x02050023,
+ 0x0204000F,
+ 0x02050025,
+ 0x02040010,
+ 0x02050026,
+ 0x0204B010,
+
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+
+ 0x02050022,
+ 0x0204004C,
+ 0x02050023,
+ 0x02040025,
+ 0x02050025,
+ 0x02040008,
+ 0x02050026,
+ 0x0204B010,
+
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+
+ 0x02050022,
+ 0x0204004C,
+ 0x02050023,
+ 0x02040002,
+ 0x02050025,
+ 0x02040000,
+ 0x02050026,
+ 0x0204B010,
+
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+ 0x000F0000,
+
+ 0x02050022,
+ 0x0204004C,
+ 0x02050023,
+ 0x02040003,
+ 0x02050025,
+ 0x02040000,
+ 0x02050026,
+ 0x0204B010
+};
+
+const u32 pc_beep_verbs[] = {
+};
+AZALIA_ARRAY_SIZES;
+#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id86f56df06795601cc9d7830766e54396d218e00
Gerrit-Change-Number: 29809
Gerrit-PatchSet: 1
Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh at intel.com>
Gerrit-MessageType: newchange
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