<p>PraveenX Hodagatta Pranesh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29809">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/intel/kblrvp: Add new Kaby lake RVP11 support<br><br>The RVP11 is a dual-channel DDR4 SO-DIMM on skylake H platform.<br><br>This patch add following chages<br>- Add devicetree.cb for RVP11 in the variants path.<br>- Select cannonlake PCH-H chipset config for RVP11.<br>- Add GPIO table as per board schematics.<br>- Add audio verb table for RVP11.<br>- Set the UserBd UPD to BOARD_TYPE_DESKTOP.<br><br>BUG=None<br>TEST= Build and flash, confirm boot into yocto OS on KBL RVP11<br> platform. verified PCI, USB, ethernet, SATA, display,<br> audio and power functionalities.<br><br>Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com><br>Change-Id: Id86f56df06795601cc9d7830766e54396d218e00<br>---<br>M src/mainboard/intel/kblrvp/Kconfig<br>M src/mainboard/intel/kblrvp/Kconfig.name<br>M src/mainboard/intel/kblrvp/ramstage.c<br>M src/mainboard/intel/kblrvp/romstage.c<br>M src/mainboard/intel/kblrvp/smihandler.c<br>A src/mainboard/intel/kblrvp/variants/rvp11/devicetree.cb<br>A src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h<br>A src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h<br>8 files changed, 806 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/29809/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig</span><br><span>index bf17c4b..1af4e30 100644</span><br><span>--- a/src/mainboard/intel/kblrvp/Kconfig</span><br><span>+++ b/src/mainboard/intel/kblrvp/Kconfig</span><br><span>@@ -1,4 +1,4 @@</span><br><span style="color: hsl(0, 100%, 40%);">-if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 || BOARD_INTEL_KBLRVP8</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 || BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11</span><br><span> </span><br><span> config BOARD_SPECIFIC_OPTIONS # dummy</span><br><span> def_bool y</span><br><span>@@ -8,9 +8,9 @@</span><br><span> select HAVE_ACPI_TABLES</span><br><span> select HAVE_OPTION_TABLE</span><br><span> select HAVE_SMI_HANDLER</span><br><span style="color: hsl(0, 100%, 40%);">- select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_KBLRVP8</span><br><span> select SOC_INTEL_SKYLAKE</span><br><span style="color: hsl(0, 100%, 40%);">- select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8</span><br><span style="color: hsl(120, 100%, 40%);">+ select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11</span><br><span> select MAINBOARD_USES_FSP2_0</span><br><span> select MAINBOARD_HAS_CHROMEOS</span><br><span> select GENERIC_SPD_BIN</span><br><span>@@ -32,6 +32,7 @@</span><br><span> default "rvp3" if BOARD_INTEL_KBLRVP3</span><br><span> default "rvp7" if BOARD_INTEL_KBLRVP7</span><br><span> default "rvp8" if BOARD_INTEL_KBLRVP8</span><br><span style="color: hsl(120, 100%, 40%);">+ default "rvp11" if BOARD_INTEL_KBLRVP11</span><br><span> </span><br><span> config MAINBOARD_PART_NUMBER</span><br><span> string</span><br><span>@@ -64,6 +65,7 @@</span><br><span> default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp3.bin" if BOARD_INTEL_KBLRVP3</span><br><span> default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp7.bin" if BOARD_INTEL_KBLRVP7</span><br><span> default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp8.bin" if BOARD_INTEL_KBLRVP8</span><br><span style="color: hsl(120, 100%, 40%);">+ default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp11.bin" if BOARD_INTEL_KBLRVP11</span><br><span> </span><br><span> config ME_BIN_PATH</span><br><span> string</span><br><span>@@ -71,6 +73,7 @@</span><br><span> default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp3.bin" if BOARD_INTEL_KBLRVP3</span><br><span> default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp7.bin" if BOARD_INTEL_KBLRVP7</span><br><span> default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp8.bin" if BOARD_INTEL_KBLRVP8</span><br><span style="color: hsl(120, 100%, 40%);">+ default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp11.bin" if BOARD_INTEL_KBLRVP11</span><br><span> </span><br><span> config PRERAM_CBMEM_CONSOLE_SIZE</span><br><span> hex</span><br><span>@@ -78,5 +81,5 @@</span><br><span> </span><br><span> config DIMM_SPD_SIZE</span><br><span> int</span><br><span style="color: hsl(0, 100%, 40%);">- default 512 if BOARD_INTEL_KBLRVP8 #DDR4</span><br><span style="color: hsl(120, 100%, 40%);">+ default 512 if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 #DDR4</span><br><span> endif</span><br><span>diff --git a/src/mainboard/intel/kblrvp/Kconfig.name b/src/mainboard/intel/kblrvp/Kconfig.name</span><br><span>index b275b17..df65e32 100644</span><br><span>--- a/src/mainboard/intel/kblrvp/Kconfig.name</span><br><span>+++ b/src/mainboard/intel/kblrvp/Kconfig.name</span><br><span>@@ -4,3 +4,5 @@</span><br><span> bool "Kabylake DDR3L RVP7"</span><br><span> config BOARD_INTEL_KBLRVP8</span><br><span> bool "Kabylake DDR4 RVP8"</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_INTEL_KBLRVP11</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "Kabylake DDR4 RVP11"</span><br><span>diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c</span><br><span>index 1e6aa11..453a4da 100644</span><br><span>--- a/src/mainboard/intel/kblrvp/ramstage.c</span><br><span>+++ b/src/mainboard/intel/kblrvp/ramstage.c</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2016 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016-2018 Intel Corporation.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -32,6 +32,9 @@</span><br><span> </span><br><span> static void ioexpander_init(void *unused)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ #if IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP11)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ #else</span><br><span> printk(BIOS_DEBUG, "Programming TCA6424A I/O expander\n");</span><br><span> </span><br><span> /* I/O Expander 1, Port 0 Data */</span><br><span>@@ -61,6 +64,7 @@</span><br><span> /* Port 0 Configuration */</span><br><span> i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_1_ADDR, IO_EXPANDER_P0CONF,</span><br><span> 0x00);</span><br><span style="color: hsl(120, 100%, 40%);">+ #endif</span><br><span> </span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c</span><br><span>index a29a4af..fe3b59c 100644</span><br><span>--- a/src/mainboard/intel/kblrvp/romstage.c</span><br><span>+++ b/src/mainboard/intel/kblrvp/romstage.c</span><br><span>@@ -1,7 +1,7 @@</span><br><span> /*</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2016 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016-2018 Intel Corporation.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -59,13 +59,15 @@</span><br><span> mem_cfg->MemorySpdDataLen = blk.len;</span><br><span> mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];</span><br><span> mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2];</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8) ||</span><br><span style="color: hsl(120, 100%, 40%);">+ IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP11)) {</span><br><span> mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1];</span><br><span> mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];</span><br><span> }</span><br><span> </span><br><span> }</span><br><span> mupd->FspmTestConfig.DmiVc1 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8))</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8) ||</span><br><span style="color: hsl(120, 100%, 40%);">+ IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP11))</span><br><span> mem_cfg->UserBd = BOARD_TYPE_DESKTOP;</span><br><span> }</span><br><span>diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c</span><br><span>index 6006767..1bc2d82 100644</span><br><span>--- a/src/mainboard/intel/kblrvp/smihandler.c</span><br><span>+++ b/src/mainboard/intel/kblrvp/smihandler.c</span><br><span>@@ -2,7 +2,7 @@</span><br><span> * This file is part of the coreboot project.</span><br><span> *</span><br><span> * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2016 Intel Corp.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2016-2018 Intel Corp.</span><br><span> *</span><br><span> * This program is free software; you can redistribute it and/or modify</span><br><span> * it under the terms of the GNU General Public License as published by</span><br><span>@@ -52,9 +52,10 @@</span><br><span> if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8))</span><br><span> return;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))</span><br><span style="color: hsl(120, 100%, 40%);">+ #if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))</span><br><span> if (gpi_status_get(sts, EC_SMI_GPI))</span><br><span> chromeec_smi_process_events();</span><br><span style="color: hsl(120, 100%, 40%);">+ #endif</span><br><span> }</span><br><span> </span><br><span> void mainboard_smi_sleep(u8 slp_typ)</span><br><span>@@ -67,8 +68,9 @@</span><br><span> </span><br><span> int mainboard_smi_apmc(u8 apmc)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))</span><br><span style="color: hsl(120, 100%, 40%);">+ #if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))</span><br><span> chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,</span><br><span> MAINBOARD_EC_SMI_EVENTS);</span><br><span style="color: hsl(120, 100%, 40%);">+ #endif</span><br><span> return 0;</span><br><span> }</span><br><span>diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..eb2ce5d</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/kblrvp/variants/rvp11/devicetree.cb</span><br><span>@@ -0,0 +1,307 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip soc/intel/skylake</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable deep Sx states</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s5_enable_ac" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_s5_enable_dc" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # GPE configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ # Note that GPE events called out in ASL code rely on this</span><br><span style="color: hsl(120, 100%, 40%);">+ # route. i.e. If this route changes then the affected GPE</span><br><span style="color: hsl(120, 100%, 40%);">+ # offset bits also need to be changed.</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw0" = "GPP_B"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw1" = "GPP_D"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpe0_dw2" = "GPP_E"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # EC host command range is in 0x800-0x8ff</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x00fc0801"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable "Intel Speed Shift Technology"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "speed_shift_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable DPTF</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dptf_enable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # FSP Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableAzalia" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "DspEnable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "IoBufferOwnership" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SmbusEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcEnabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsEmmcHs400Enabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "ScsSdCardEnabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "InternalGfx" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SkipExtGfxScan" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Device4Enable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "Heci3Enabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SaGv" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmTimerDisabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch</span><br><span style="color: hsl(120, 100%, 40%);">+ # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS3MinAssert" = "0x02"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpS4MinAssert" = "0x04"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpSusMinAssert" = "0x03"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmConfigSlpAMinAssert" = "0x03"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIrqConfigSirqEnable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIrqConfigSirqMode" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # VR Settings Configuration for 4 Domains</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Domain/Setting | SA | IA | GTUS | GTS |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi1Threshold | 20A | 20A | 20A | 20A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi2Threshold | 4A | 5A | 5A | 5A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi3Threshold | 1A | 1A | 1A | 1A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi3Enable | 1 | 1 | 1 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| Psi4Enable | 1 | 1 | 1 | 1 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| ImonSlope | 0 | 0 | 0 | 0 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| ImonOffset | 0 | 0 | 0 | 0 |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| IccMax | 7A | 34A | 35A | 35A |</span><br><span style="color: hsl(120, 100%, 40%);">+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |</span><br><span style="color: hsl(120, 100%, 40%);">+ #+----------------+-------+-------+-------+-------+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = 0x50, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = 0x10, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = 0x4, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = 0x1C, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 0x5F0 \</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_IA_CORE]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = 0x50, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = 0x14, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = 0x4, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = 0x88, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 0x5F0 \</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_GT_UNSLICED]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = 0x50, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = 0x14, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = 0x4, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = 0x8C ,\</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 0x5F0 \</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "domain_vr_config[VR_GT_SLICED]" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .vr_config_enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi1threshold = 0x50, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi2threshold = 0x14, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3threshold = 0x4, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi3enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .psi4enable = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_slope = 0x0, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .imon_offset = 0x0, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .icc_max = 0x8C, \</span><br><span style="color: hsl(120, 100%, 40%);">+ .voltage_limit = 0x5F0 \</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable PCIE slot</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP6, uses uses CLK SRC 1</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[5]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[6]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP7, uses uses CLK SRC 2</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[6]" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[7]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP8, uses uses CLK SRC 3</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[7]" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[8]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP9, uses uses CLK SRC 4</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[8]" = "4"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[13]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[13]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP14, uses uses CLK SRC 5</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[13]" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpEnable[16]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqSupport[16]" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7</span><br><span style="color: hsl(120, 100%, 40%);">+ # RP17, uses uses CLK SRC 7</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PcieRpClkSrcNumber[16]" = "7"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register EnableLan = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # USB related</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SsicPortEnable" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn</span><br><span style="color: hsl(120, 100%, 40%);">+ register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Must leave UART0 enabled or SD/eMMC will not work as PCI</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqa_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqb_routing" = "0x0a"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqc_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqd_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqe_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqf_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqg_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pirqh_routing" = "0x0b"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PmTimerDisabled" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ register "EnableSata" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataSalpSupport" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SataPortsEnable" = "{ \</span><br><span style="color: hsl(120, 100%, 40%);">+ [0] = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [1] = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [2] = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [3] = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [4] = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [5] = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [6] = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [7] = 1, \</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SerialIoDevMode" = "{ \</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C4] = PchSerialIoPci, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart0] = PchSerialIoPci, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \</span><br><span style="color: hsl(120, 100%, 40%);">+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # PL2 override 60W</span><br><span style="color: hsl(120, 100%, 40%);">+ register "tdp_pl2_override" = "60"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Power Limit Related</span><br><span style="color: hsl(120, 100%, 40%);">+ register "PowerLimit4" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Send an extra VR mailbox command for the PS4 exit issue</span><br><span style="color: hsl(120, 100%, 40%);">+ register "SendVrMbxCmd" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Enable/Disable VMX feature</span><br><span style="color: hsl(120, 100%, 40%);">+ register "VmxEnable" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ # Lock Down</span><br><span style="color: hsl(120, 100%, 40%);">+ register "common_soc_config" = "{</span><br><span style="color: hsl(120, 100%, 40%);">+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,</span><br><span style="color: hsl(120, 100%, 40%);">+ }"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on end # Host Bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on end # USB xHCI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.1 off end # USB xDCI (OTG)</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.2 on end # Thermal Subsystem</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.0 on end # I2C #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.1 on end # I2C #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.2 on end # I2C #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 15.3 on end # I2C #3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on end # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off end # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off end # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 off end # Management Engine KT Redirection</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.4 off end # Management Engine Interface 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 17.0 on end # SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on end # UART #2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.1 on end # I2C #5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.2 on end # I2C #4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on end # PCI Express Port 1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 off end # PCI Express Port 2</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 off end # PCI Express Port 3</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off end # PCI Express Port 4</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 off end # PCI Express Port 5</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off end # PCI Express Port 6</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off end # PCI Express Port 7</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off end # PCI Express Port 8</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on end # PCI Express Port 9</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.1 off end # PCI Express Port 10</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.2 off end # PCI Express Port 11</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.3 off end # PCI Express Port 12</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 on end # UART #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.1 on end # UART #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.2 on end # GSPI #0</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.3 on end # GSPI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.4 off end # eMMC</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.5 off end # SDIO</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.6 off end # SDCard</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ #chip drivers/pc80/tpm</span><br><span style="color: hsl(120, 100%, 40%);">+ # device pnp 0c31.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ #end</span><br><span style="color: hsl(120, 100%, 40%);">+ #chip ec/google/chromeec</span><br><span style="color: hsl(120, 100%, 40%);">+ # device pnp 0c09.0 on end</span><br><span style="color: hsl(120, 100%, 40%);">+ #end</span><br><span style="color: hsl(120, 100%, 40%);">+ end # LPC Interface</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.1 on end # P2SB</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on end # Power Management Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on end # Intel HDA</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.4 on end # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 on end # PCH SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 on end # GbE</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h</span><br><span>new file mode 100644</span><br><span>index 0000000..d3224b2</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h</span><br><span>@@ -0,0 +1,275 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2013 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _GPIORVP11_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define _GPIORVP11_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpe.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC in RW */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_EC_IN_RW GPP_C6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* BIOS Flash Write Protect */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PCH_WP GPP_C23</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Memory configuration board straps */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_0 GPP_C12</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_1 GPP_C13</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_2 GPP_C14</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_MEM_CONFIG_3 GPP_C15</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_EC_WAKE GPE0_LAN_WAK</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_WLAN_WAKE GPE0_DW0_16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Input device interrupt configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOUCHPAD_INT_L GPP_B3_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+#define TOUCHSCREEN_INT_L GPP_E7_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+#define MIC_INT_L GPP_F10_IRQ</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_SCI_GPI GPE0_DW2_16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef __ACPI__</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Pad configuration in ramstage. */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ESPI ALERT */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF2),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_HID_INT */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_KB_PROX_INT */ PAD_CFG_GPI(GPP_A12, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SLP_S0ix_N */ PAD_CFG_GPO(GPP_A16, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* M.2 WLAN PWR EN */ PAD_CFG_GPO(GPP_A17, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_A19 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_A23 */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* screen lock */ PAD_CFG_GPI(GPP_B0, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* Tch pnl pwren */ PAD_CFG_GPO(GPP_B1, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* HSJ_MIC_DET */</span><br><span style="color: hsl(120, 100%, 40%);">+/* BT_RF_kill */ PAD_CFG_GPO(GPP_B3, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SNI_DRV_PCH */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* M.2 BT UART wake */ PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* WIFI_CLK_REQ */</span><br><span style="color: hsl(120, 100%, 40%);">+/* KEPLR_CLK_REQ */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ3# */ /* GPP_B8 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SSD_CLK_REQ */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SRCCLKREQ5# */ /* GPP_B10 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_B_14_SPKR */ PAD_CFG_GPI_ACPI_SMI(GPP_B14, NONE, DEEP, YES),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_CS# */ /* GPP_B15 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SSD_PCIE_WAKE */ PAD_CFG_GPO(GPP_B17, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SMBALERT# */ PAD_CFG_GPI(GPP_C2, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB_CTL */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* NFC_RST* */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP3300_KEPLER */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_MEM_CFG0 */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_MEM_CFG1 */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_MEM_CFG2 */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_MEM_CFG3 */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TCH_PNL_PWREN */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI_WP_STATUS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_MISO_1 */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_MISO_0 */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP3300_DX_EMMC */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP1800_DX_EMMC */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB_A1_ILIM_SEL */</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP3300_DX_CAM */</span><br><span style="color: hsl(120, 100%, 40%);">+/* EN_PP1800_DX_AUDIO */PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* ITCH_SPI_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SPI_TPM_IRQ */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SSD_PEDET */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP1 */ /* GPP_E5 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF3),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TCH_PNL_INTR* */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_TXD */ PAD_CFG_GPO(GPP_F2, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2S2_RXD */ PAD_CFG_GPO(GPP_F3, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SDA */ PAD_CFG_GPO(GPP_F4, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C2_SCL */ PAD_CFG_GPI_APIC(GPP_F5, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SDA */ PAD_CFG_GPO(GPP_F6, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C3_SCL */ PAD_CFG_GPO(GPP_F7, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SDA */ PAD_CFG_GPI(GPP_F8, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C4_SDA */ PAD_CFG_GPI_APIC(GPP_F9, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* AUDIO_IRQ */ PAD_CFG_GPI(GPP_F10, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* I2C5_SCL */ PAD_CFG_GPI(GPP_F11, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CMD */ PAD_CFG_GPI_ACPI_SCI(GPP_F12, NONE, DEEP, YES),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F13, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA1 */ PAD_CFG_GPI(GPP_F14, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA4 */ PAD_CFG_GPO(GPP_F17, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA5 */ PAD_CFG_GPO(GPP_F18, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EMMC_CLK */ PAD_CFG_GPO(GPP_F22, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* GPP_F23 */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_GPI_APIC(GPP_G0, 20K_PD, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA0 */ PAD_CFG_GPO(GPP_G1, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA2 */ PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA3 */ PAD_CFG_GPO(GPP_G4, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_WP */ PAD_CFG_GPI_APIC(GPP_G7, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_G8, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_G9, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_G10, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_G11, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_G13, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_G15, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_G16, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_G17, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPI_ACPI_SCI(GPP_G18, NONE, DEEP, YES),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_G20, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPI_APIC(GPP_G21, 20K_PD, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_G22, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_G23, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA0 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA1 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA2 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_DATA3 */ PAD_CFG_GPO(GPP_H4, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CD# */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CLK */ PAD_CFG_GPO(GPP_H6, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_WP */ PAD_CFG_GPO(GPP_H7, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_H8, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_H9, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_H10, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_H11, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPI(GPP_H13, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPI(GPP_H14, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPI(GPP_H15, NONE, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_H16, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_H17, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_H18, 1, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* TBD */ PAD_CFG_GPO(GPP_H23, 0, DEEP),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* SD_CMD */ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+ /* GPD7 */</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Early pad configuration in romstage. */</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pad_config early_gpio_table[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h</span><br><span>new file mode 100644</span><br><span>index 0000000..1312d9b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h</span><br><span>@@ -0,0 +1,200 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef HDA_VERB_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define HDA_VERB_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x8086280B,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000005,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Display Audio Verb Table</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enable the third converter and Pin first (NID 08h)</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00878101,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00878101,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00878101,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00878101,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x05, 0x18560010),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x06, 0x18560020),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x07, 0x18560030),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable the third converter and third Pin (NID 08h) */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00878100,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00878100,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00878100,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00878100,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ALC 298 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10EC0298,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00000023,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_SUBVENDOR(0, 0x10EC109C),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x01, 0x00000000),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x12, 0x411111F0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x13, 0x40000000),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x14, 0x9017011F),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x17, 0x90170110),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x18, 0x03A11040),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x19, 0x411111F0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1A, 0x411111F0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1D, 0x4066A22D),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x1E, 0x411111F0),</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0, 0x21, 0x03211020),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Widget node 0x20 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0205004F,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204B009,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050050,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02041000,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Widget node 0x20 - 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050019,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040017,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050020,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040002,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Widget node 0x20 - 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0205008F,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02041008,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050036,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x020462C0,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Widget node 0x20 - 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0205002B,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040D10,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0205002D,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02044020,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Widget node 0x20 - 4 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0205000E,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02046F80,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x01771F90,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x01771F90,</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Widget node 0x20 - 5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050079,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02046800,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050079,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02046800,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TI AMP settings */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050022,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204004C,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050023,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050025,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050026,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204B010,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050022,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204004C,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050023,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040002,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050025,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040011,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050026,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204B010,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050022,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204004C,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050023,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204000F,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050025,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040010,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050026,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204B010,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050022,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204004C,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050023,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040025,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050025,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040008,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050026,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204B010,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050022,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204004C,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050023,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040002,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050025,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050026,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204B010,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x000F0000,</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050022,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204004C,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050023,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040003,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050025,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02040000,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x02050026,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0204B010</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+AZALIA_ARRAY_SIZES;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29809">change 29809</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29809"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Id86f56df06795601cc9d7830766e54396d218e00 </div>
<div style="display:none"> Gerrit-Change-Number: 29809 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>