[coreboot-gerrit] Change in ...coreboot[master]: siemens/mc_apl5: Adjust the settings for the PCIe root ports

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29810


Change subject: siemens/mc_apl5: Adjust the settings for the PCIe root ports
......................................................................

siemens/mc_apl5: Adjust the settings for the PCIe root ports

This mainboard has four connected PCIe devices. The required root ports
are switched on and configured.

Change-Id: I82b13e1d245a172762ebd689ae136a762027033f
Signed-off-by: Mario Scheithauer <mario.scheithauer at siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
1 file changed, 12 insertions(+), 12 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/29810/1

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
index f3e8a77..7dbeea1 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
@@ -7,12 +7,12 @@
 	register "sci_irq" = "SCIS_IRQ10"
 
 	# Disable unused clkreq of PCIe root ports
-	register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge
-	register "pcie_rp_clkreq_pin[1]" = "2" # FPGA
-	register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY
-	register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY
-	register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
-	register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
+	register "pcie_rp_clkreq_pin[0]" = "1"			# 14.0
+	register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"	# 14.1
+	register "pcie_rp_clkreq_pin[2]" = "0"			# 13.0
+	register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"	# 13.1
+	register "pcie_rp_clkreq_pin[4]" = "2"			# 13.2
+	register "pcie_rp_clkreq_pin[5]" = "3"			# 13.3
 
 	# EMMC TX DATA Delay 1
 	# Refer to EDS-Vol2-22.3.
@@ -71,12 +71,12 @@
 		device pci 0e.0 off end	# - Audio
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on  end	# - SATA
-		device pci 13.0 on  end	# - RP 2 - PCIe A 0 - MACPHY
-		device pci 13.1 on  end	# - RP 3 - PCIe A 1 - MACPHY
-		device pci 13.2 off end	# - RP 4 - PCIe-A 2
-		device pci 13.3 off end	# - RP 5 - PCIe-A 3
-		device pci 14.0 on  end	# - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge
-		device pci 14.1 on  end	# - RP 1 - PCIe-B 1 - FPGA
+		device pci 13.0 on  end	# - RP 2 - PCIe A 0
+		device pci 13.1 off end	# - RP 3 - PCIe A 1
+		device pci 13.2 on  end	# - RP 4 - PCIe-A 2
+		device pci 13.3 on  end	# - RP 5 - PCIe-A 3
+		device pci 14.0 on  end	# - RP 0 - PCIe-B 0
+		device pci 14.1 off end	# - RP 1 - PCIe-B 1
 		device pci 15.0 on  end	# - XHCI
 		device pci 15.1 off end	# - XDCI
 		device pci 16.0 on	# - I2C 0

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I82b13e1d245a172762ebd689ae136a762027033f
Gerrit-Change-Number: 29810
Gerrit-PatchSet: 1
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
Gerrit-MessageType: newchange
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