[coreboot-gerrit] Change in ...coreboot[master]: nb/intel/haswell: Enable PCIe on the processor
Iru Cai (vimacs) (Code Review)
gerrit at coreboot.org
Mon Dec 17 09:50:43 CET 2018
Hello Iru Cai,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/30268
to review the following change.
Change subject: nb/intel/haswell: Enable PCIe on the processor
......................................................................
nb/intel/haswell: Enable PCIe on the processor
The code is mostly from nb/intel/sandybridge.
Tested with ASRock H81M-HDS with GTX650 on the PCIe x16 slot.
Change-Id: Ifcb017eceef73553fc230c60d08b7d61a1796fce
Signed-off-by: Iru Cai <mytbk920423 at gmail.com>
---
M src/northbridge/intel/haswell/Makefile.inc
M src/northbridge/intel/haswell/early_init.c
A src/northbridge/intel/haswell/pcie.c
3 files changed, 133 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/30268/1
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index 055c2a8..11cb6b4 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -18,6 +18,7 @@
ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
+ramstage-y += pcie.c
ramstage-y += acpi.c
ramstage-y += minihd.c
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 663812a..c4e4a77 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -119,8 +119,33 @@
reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV);
}
+static void start_peg_link_training(void)
+{
+ u32 tmp;
+ u32 deven;
+
+ deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
+
+ if (deven & DEVEN_D1F0EN) {
+ tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5));
+ }
+
+ if (deven & DEVEN_D1F1EN) {
+ tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5));
+ }
+
+ if (deven & DEVEN_D1F2EN) {
+ tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16);
+ pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5));
+ }
+}
+
void haswell_early_initialization(int chipset_type)
{
+ u32 tmp;
+
/* Setup all BARs required for early PCIe and raminit */
haswell_setup_bars();
@@ -128,8 +153,11 @@
haswell_setup_iommu();
/* Device Enable: IGD and Mini-HD Audio */
+ tmp = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN,
- DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
+ tmp | DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
haswell_setup_graphics();
+
+ start_peg_link_training();
}
diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c
new file mode 100644
index 0000000..b850172
--- /dev/null
+++ b/src/northbridge/intel/haswell/pcie.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017-2018 Patrick Rudolph <siro at das-labor.org>
+ * Copyright (C) 2018 Iru Cai <mytbk920423 at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+#include <assert.h>
+
+static void pcie_disable(struct device *dev)
+{
+ printk(BIOS_INFO, "%s: Disabling device\n", dev_path(dev));
+ dev->enabled = 0;
+}
+
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+static const char *pcie_acpi_name(const struct device *dev)
+{
+ assert(dev);
+
+ if (dev->path.type != DEVICE_PATH_PCI)
+ return NULL;
+
+ assert(dev->bus);
+ if (dev->bus->secondary == 0)
+ switch (dev->path.pci.devfn) {
+ case PCI_DEVFN(1, 0):
+ return "PEGP";
+ case PCI_DEVFN(1, 1):
+ return "PEG1";
+ case PCI_DEVFN(1, 2):
+ return "PEG2";
+ };
+
+ struct device *const port = dev->bus->dev;
+ assert(port);
+ assert(port->bus);
+
+ if (dev->path.pci.devfn == PCI_DEVFN(0, 0) &&
+ port->bus->secondary == 0 &&
+ (port->path.pci.devfn == PCI_DEVFN(1, 0) ||
+ port->path.pci.devfn == PCI_DEVFN(1, 1) ||
+ port->path.pci.devfn == PCI_DEVFN(1, 2)))
+ return "DEV0";
+
+ return NULL;
+}
+#endif
+
+static void
+pcie_set_subsystem(struct device *dev, unsigned int ven, unsigned int device)
+{
+ /* NOTE: This is not the default position! */
+ if (!ven || !device)
+ pci_write_config32(dev, 0x94,
+ pci_read_config32(dev, 0));
+ else
+ pci_write_config32(dev, 0x94,
+ ((device & 0xffff) << 16) | (ven & 0xffff));
+}
+
+static struct pci_operations pci_ops = {
+ .set_subsystem = pcie_set_subsystem,
+};
+
+static struct device_operations device_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .scan_bus = pciexp_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .disable = pcie_disable,
+ .init = pci_dev_init,
+ .ops_pci = &pci_ops,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+ .acpi_name = pcie_acpi_name,
+#endif
+};
+
+static const unsigned short pci_device_ids[] = {
+ 0x0c01, 0x0c05, 0x0c09,
+ 0 };
+
+static const struct pci_driver pch_pcie __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
--
To view, visit https://review.coreboot.org/c/coreboot/+/30268
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifcb017eceef73553fc230c60d08b7d61a1796fce
Gerrit-Change-Number: 30268
Gerrit-PatchSet: 1
Gerrit-Owner: Iru Cai (vimacs) <mytbk920423 at gmail.com>
Gerrit-Reviewer: Iru Cai <mytbk920423 at gmail.com>
Gerrit-MessageType: newchange
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