[coreboot-gerrit] Change in ...coreboot[master]: nb/intel/haswell: Enable PCIe on the processor

[Tristan Corrick (Code Review)]

Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30268 )

Change subject: nb/intel/haswell: Enable PCIe on the processor
......................................................................


Patch Set 1:

With Haswell, since we are forced to use the MRC, the link training
can't always be done in romstage. This is because the MRC will disable
the IGD if it finds a PCIe device of VGA class in a PEG slot, but it
won't find it until the link training is done.

I've actually done most of this work, but I was waiting for the 4.9
release before pushing it. Sorry if this has led to duplicated work.
I'll push what I've done in a moment.

Were you able to connect the display to the GTX650 and get output?
I've tried this with two AMD graphics cards on SNB and HSW with my
patches and neither worked.


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifcb017eceef73553fc230c60d08b7d61a1796fce
Gerrit-Change-Number: 30268
Gerrit-PatchSet: 1
Gerrit-Owner: Iru Cai (vimacs) <mytbk920423 at gmail.com>
Gerrit-Reviewer: Iru Cai (vimacs) <mytbk920423 at gmail.com>
Gerrit-Reviewer: Iru Cai <mytbk920423 at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Tristan Corrick <tristan at corrick.kiwi>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Mon, 17 Dec 2018 09:03:42 +0000
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