<p>Iru Cai (vimacs) would like Iru Cai to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/30268">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/haswell: Enable PCIe on the processor<br><br>The code is mostly from nb/intel/sandybridge.<br><br>Tested with ASRock H81M-HDS with GTX650 on the PCIe x16 slot.<br><br>Change-Id: Ifcb017eceef73553fc230c60d08b7d61a1796fce<br>Signed-off-by: Iru Cai <mytbk920423@gmail.com><br>---<br>M src/northbridge/intel/haswell/Makefile.inc<br>M src/northbridge/intel/haswell/early_init.c<br>A src/northbridge/intel/haswell/pcie.c<br>3 files changed, 133 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/30268/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc</span><br><span>index 055c2a8..11cb6b4 100644</span><br><span>--- a/src/northbridge/intel/haswell/Makefile.inc</span><br><span>+++ b/src/northbridge/intel/haswell/Makefile.inc</span><br><span>@@ -18,6 +18,7 @@</span><br><span> ramstage-y += ram_calc.c</span><br><span> ramstage-y += northbridge.c</span><br><span> ramstage-y += gma.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += pcie.c</span><br><span> </span><br><span> ramstage-y += acpi.c</span><br><span> ramstage-y += minihd.c</span><br><span>diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c</span><br><span>index 663812a..c4e4a77 100644</span><br><span>--- a/src/northbridge/intel/haswell/early_init.c</span><br><span>+++ b/src/northbridge/intel/haswell/early_init.c</span><br><span>@@ -119,8 +119,33 @@</span><br><span> reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void start_peg_link_training(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tmp;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 deven;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (deven & DEVEN_D1F0EN) {</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (deven & DEVEN_D1F1EN) {</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (deven & DEVEN_D1F2EN) {</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void haswell_early_initialization(int chipset_type)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 tmp;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Setup all BARs required for early PCIe and raminit */</span><br><span> haswell_setup_bars();</span><br><span> </span><br><span>@@ -128,8 +153,11 @@</span><br><span> haswell_setup_iommu();</span><br><span> </span><br><span> /* Device Enable: IGD and Mini-HD Audio */</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);</span><br><span> pci_write_config32(PCI_DEV(0, 0, 0), DEVEN,</span><br><span style="color: hsl(0, 100%, 40%);">- DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ tmp | DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);</span><br><span> </span><br><span> haswell_setup_graphics();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ start_peg_link_training();</span><br><span> }</span><br><span>diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c</span><br><span>new file mode 100644</span><br><span>index 0000000..b850172</span><br><span>--- /dev/null</span><br><span>+++ b/src/northbridge/intel/haswell/pcie.c</span><br><span>@@ -0,0 +1,103 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017-2018 Patrick Rudolph <siro@das-labor.org></span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Iru Cai <mytbk920423@gmail.com></span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pciexp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pcie_disable(struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_INFO, "%s: Disabling device\n", dev_path(dev));</span><br><span style="color: hsl(120, 100%, 40%);">+ dev->enabled = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span style="color: hsl(120, 100%, 40%);">+static const char *pcie_acpi_name(const struct device *dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.type != DEVICE_PATH_PCI)</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(dev->bus);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->bus->secondary == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (dev->path.pci.devfn) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(1, 0):</span><br><span style="color: hsl(120, 100%, 40%);">+ return "PEGP";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(1, 1):</span><br><span style="color: hsl(120, 100%, 40%);">+ return "PEG1";</span><br><span style="color: hsl(120, 100%, 40%);">+ case PCI_DEVFN(1, 2):</span><br><span style="color: hsl(120, 100%, 40%);">+ return "PEG2";</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *const port = dev->bus->dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(port);</span><br><span style="color: hsl(120, 100%, 40%);">+ assert(port->bus);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev->path.pci.devfn == PCI_DEVFN(0, 0) &&</span><br><span style="color: hsl(120, 100%, 40%);">+ port->bus->secondary == 0 &&</span><br><span style="color: hsl(120, 100%, 40%);">+ (port->path.pci.devfn == PCI_DEVFN(1, 0) ||</span><br><span style="color: hsl(120, 100%, 40%);">+ port->path.pci.devfn == PCI_DEVFN(1, 1) ||</span><br><span style="color: hsl(120, 100%, 40%);">+ port->path.pci.devfn == PCI_DEVFN(1, 2)))</span><br><span style="color: hsl(120, 100%, 40%);">+ return "DEV0";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void</span><br><span style="color: hsl(120, 100%, 40%);">+pcie_set_subsystem(struct device *dev, unsigned int ven, unsigned int device)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NOTE: This is not the default position! */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!ven || !device)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, 0x94,</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_read_config32(dev, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, 0x94,</span><br><span style="color: hsl(120, 100%, 40%);">+ ((device & 0xffff) << 16) | (ven & 0xffff));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct pci_operations pci_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set_subsystem = pcie_set_subsystem,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct device_operations device_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .read_resources = pci_bus_read_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ .set_resources = pci_dev_set_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_resources = pci_bus_enable_resources,</span><br><span style="color: hsl(120, 100%, 40%);">+ .scan_bus = pciexp_scan_bridge,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset_bus = pci_bus_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ .disable = pcie_disable,</span><br><span style="color: hsl(120, 100%, 40%);">+ .init = pci_dev_init,</span><br><span style="color: hsl(120, 100%, 40%);">+ .ops_pci = &pci_ops,</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)</span><br><span style="color: hsl(120, 100%, 40%);">+ .acpi_name = pcie_acpi_name,</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const unsigned short pci_device_ids[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0c01, 0x0c05, 0x0c09,</span><br><span style="color: hsl(120, 100%, 40%);">+ 0 };</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pci_driver pch_pcie __pci_driver = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .ops = &device_ops,</span><br><span style="color: hsl(120, 100%, 40%);">+ .vendor = PCI_VENDOR_ID_INTEL,</span><br><span style="color: hsl(120, 100%, 40%);">+ .devices = pci_device_ids,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/30268">change 30268</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/30268"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ifcb017eceef73553fc230c60d08b7d61a1796fce </div>
<div style="display:none"> Gerrit-Change-Number: 30268 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Iru Cai (vimacs) <mytbk920423@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Iru Cai <mytbk920423@gmail.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>