[coreboot-gerrit] Change in coreboot[master]: intel/fsp2_0: Add FSP_NXT shared stack feature support

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/28358


Change subject: intel/fsp2_0: Add FSP_NXT shared stack feature support
......................................................................

intel/fsp2_0: Add FSP_NXT shared stack feature support

FSP_NXT implementation is adding features on top of fsp2_0.
One such feature is a shared stack implementation that requires
coreboot to allocate stack for fspm and fspm then uses the same
stack as coreboot. This implementation adds support for shared
stack feature.

Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/arch/x86/car.ld
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/memory_init.c
3 files changed, 37 insertions(+), 15 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/28358/1

diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 7122776..b0c23c8 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -36,6 +36,9 @@
 	 * the stack size. */
 #if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
 	_car_stack_start = .;
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP_NXT)
+	. += CONFIG_FSP_NXT_STACK_SIZE;
+#endif
 	. += CONFIG_DCACHE_BSP_STACK_SIZE;
 	_car_stack_end = .;
 #endif
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index f149544..d7bcbd3 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -19,6 +19,13 @@
 	help
 	  Include FSP 2.0 wrappers and functionality
 
+config PLATFORM_USES_FSP_NXT
+	bool
+	default n
+	select PLATFORM_USES_FSP2_0
+	help
+	  Include FSP next feature support
+
 if PLATFORM_USES_FSP2_0
 
 config ADD_FSP_BINARIES
@@ -133,4 +140,12 @@
 	  This allows deployed systems to bump their version number
 	  with the same FSP which will trigger a retrain of the memory.
 
+config FSP_NXT_STACK_SIZE
+	hex
+	depends on PLATFORM_USES_FSP_NXT
+	default 0x20000
+	help
+	  Stack size to be allocated for fsp-m. The FSP NXT version expects
+	  the stack being allocated from coreboot and it uses the same stack
+	  as coreboot.
 endif
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index cf033d7..aa13872 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -170,22 +170,26 @@
 					bool s3wake, uint32_t fsp_version,
 					const struct memranges *memmap)
 {
-	uintptr_t stack_begin;
-	uintptr_t stack_end;
+	if (!IS_ENABLED(CONFIG_PLATFORM_USES_FSP_NXT))
+	{
+		uintptr_t stack_begin;
+		uintptr_t stack_end;
+		/*
+		 * FSPM_UPD passed here is populated with default values provided by
+		 * the blob itself. We let FSPM use top of CAR region of the size it
+		 * requests.
+		 */
+		stack_end = (uintptr_t)_car_region_end;
+		stack_begin = stack_end - arch_upd->StackSize;
+		if (check_region_overlap(memmap, "FSPM stack", stack_begin,
+					stack_end) != CB_SUCCESS)
+			return CB_ERR;
 
-	/*
-	 * FSPM_UPD passed here is populated with default values provided by
-	 * the blob itself. We let FSPM use top of CAR region of the size it
-	 * requests.
-	 */
-	stack_end = (uintptr_t)_car_region_end;
-	stack_begin = stack_end - arch_upd->StackSize;
-
-	if (check_region_overlap(memmap, "FSPM stack", stack_begin,
-				stack_end) != CB_SUCCESS)
-		return CB_ERR;
-
-	arch_upd->StackBase = (void *)stack_begin;
+		arch_upd->StackBase = (void *)stack_begin;
+	} else {
+		arch_upd->StackBase = (void *)_car_stack_end;
+		arch_upd->StackSize = CONFIG_FSP_NXT_STACK_SIZE;
+	}
 
 	fsp_fill_mrc_cache(arch_upd, fsp_version);
 

-- 
To view, visit https://review.coreboot.org/28358
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7
Gerrit-Change-Number: 28358
Gerrit-PatchSet: 1
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180827/d5190972/attachment.html>