[coreboot-gerrit] Change in coreboot[master]: riscv: fix to write XS

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/28357


Change subject: riscv: fix to write XS
......................................................................

riscv: fix to write XS

XS is a read-only field of mstatus. Unable to be write. So remove this code.

Change-Id: I3ad6b0029900124ac7cce062e668a0ea5a8b2c0e
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/virtual_memory.c
1 file changed, 0 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28357/1

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 71e2ac9..68936b6 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -39,7 +39,6 @@
 	uintptr_t ms = 0;
 
 	ms = INSERT_FIELD(ms, MSTATUS_FS, 3);
-	ms = INSERT_FIELD(ms, MSTATUS_XS, 3);
 	write_csr(mstatus, ms);
 
 	// clear any pending timer interrupts.

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3ad6b0029900124ac7cce062e668a0ea5a8b2c0e
Gerrit-Change-Number: 28357
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
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