[coreboot-gerrit] Change in coreboot[master]: rk3288: Dig up two more KB of SRAM from under the couch cushions

[Julius Werner (Code Review)]

Hello Patrick Rudolph,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/27950

to review the following change.


Change subject: rk3288: Dig up two more KB of SRAM from under the couch cushions
......................................................................

rk3288: Dig up two more KB of SRAM from under the couch cushions

RK3288 has always been notoriously low on SRAM, to the point where its
boards have less than 100 bytes left in both their bootblock/verstage
sections. This becomes a problem every time we try to add a tiny amount
of code to common coreboot interfaces that are included in them.

This patch manages to add another KB to each, one from the CBMEM console
(which now might get cut off a bit, but that's life) and one by moving
the TTB_SUBTABLES to PMUSRAM. PMUSRAM is a weird world where write
accesses must always be exactly 4 bytes long or they hang the CPU, so we
mostly ignore it... but thankfully, page table entries are exactly 4
bytes long and that's the only thing we write to this region, so it
works out in this case.

Change-Id: I5aecd66db40b3f52299b270322b8c8784dbe7e6f
Signed-off-by: Julius Werner <jwerner at chromium.org>
---
M src/soc/rockchip/rk3288/include/soc/memlayout.ld
1 file changed, 4 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27950/1

diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index daff503..fc3758b 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -30,11 +30,10 @@
 
 	SRAM_START(0xFF700000)
 	TTB(0xFF700000, 16K)
-	BOOTBLOCK(0xFF704004, 19K - 4)
-	PRERAM_CBMEM_CONSOLE(0xFF708C00, 4K)
+	BOOTBLOCK(0xFF704004, 20K - 4)
+	PRERAM_CBMEM_CONSOLE(0xFF709000, 3K)
 	VBOOT2_WORK(0xFF709C00, 12K)
-	OVERLAP_VERSTAGE_ROMSTAGE(0xFF70CC00, 40K)
-	TTB_SUBTABLES(0xFF716C00, 1K)
+	OVERLAP_VERSTAGE_ROMSTAGE(0xFF70CC00, 41K)
 	PRERAM_CBFS_CACHE(0xFF717000, 1K)
 	TIMESTAMP(0xFF717400, 0x180)
 	STACK(0xFF717580, 3K - 0x180)
@@ -43,6 +42,7 @@
 	/* 4K of special SRAM in PMU power domain.
 	 * Careful: only supports 32-bit wide write accesses! */
 	SYMBOL(pmu_sram, 0xFF720000)
+	TTB_SUBTABLES(0xFF720800, 1K)
 	WATCHDOG_TOMBSTONE(0xFF720FFC, 4)
 	SYMBOL(epmu_sram, 0xFF721000)
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5aecd66db40b3f52299b270322b8c8784dbe7e6f
Gerrit-Change-Number: 27950
Gerrit-PatchSet: 1
Gerrit-Owner: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph at 9elements.com>
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