[coreboot-gerrit] Change in coreboot[master]: src/mainboard: Fix typo
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Tue Aug 7 12:26:41 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27912
Change subject: src/mainboard: Fix typo
......................................................................
src/mainboard: Fix typo
Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/mainboard/advansus/a785e-i/resourcemap.c
M src/mainboard/amd/bimini_fam10/mainboard.c
M src/mainboard/amd/bimini_fam10/resourcemap.c
M src/mainboard/amd/db-ft3b-lc/mptable.c
M src/mainboard/amd/lamar/mptable.c
M src/mainboard/amd/mahogany_fam10/resourcemap.c
M src/mainboard/amd/persimmon/mainboard.c
M src/mainboard/amd/persimmon/mptable.c
M src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
M src/mainboard/amd/south_station/mainboard.c
M src/mainboard/amd/tilapia_fam10/resourcemap.c
M src/mainboard/amd/torpedo/gpio.h
M src/mainboard/amd/torpedo/platform_cfg.h
M src/mainboard/amd/union_station/mainboard.c
M src/mainboard/asus/am1i-a/mptable.c
M src/mainboard/asus/kcma-d8/resourcemap.c
M src/mainboard/asus/kfsn4-dre/resourcemap.c
M src/mainboard/asus/kgpe-d16/resourcemap.c
M src/mainboard/asus/m4a78-em/mainboard.c
M src/mainboard/asus/m4a78-em/resourcemap.c
M src/mainboard/asus/m4a785-m/mainboard.c
M src/mainboard/asus/m4a785-m/resourcemap.c
M src/mainboard/asus/m5a88-v/resourcemap.c
M src/mainboard/avalue/eax-785e/resourcemap.c
M src/mainboard/bap/ode_e20XX/mptable.c
M src/mainboard/biostar/am1ml/mptable.c
M src/mainboard/elmex/pcm205400/mainboard.c
M src/mainboard/elmex/pcm205400/mptable.c
M src/mainboard/emulation/qemu-armv7/mainboard.c
M src/mainboard/gigabyte/ma785gm/resourcemap.c
M src/mainboard/gigabyte/ma785gmt/resourcemap.c
M src/mainboard/gigabyte/ma78gm/resourcemap.c
M src/mainboard/gizmosphere/gizmo2/mptable.c
M src/mainboard/google/daisy/romstage.c
M src/mainboard/google/peach_pit/romstage.c
M src/mainboard/google/urara/urara_boardid.h
M src/mainboard/iei/kino-780am2-fam10/resourcemap.c
M src/mainboard/jetway/nf81-t56n-lf/mainboard.c
M src/mainboard/jetway/nf81-t56n-lf/mptable.c
M src/mainboard/jetway/pa78vm5/resourcemap.c
M src/mainboard/msi/ms9652_fam10/resourcemap.c
M src/mainboard/pcengines/apu1/mainboard.c
M src/mainboard/pcengines/apu1/mptable.c
M src/mainboard/pcengines/apu2/mptable.c
M src/mainboard/siemens/mc_tcu3/ptn3460.c
M src/mainboard/siemens/mc_tcu3/ptn3460.h
M src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
M src/mainboard/supermicro/h8qme_fam10/resourcemap.c
M src/mainboard/supermicro/h8scm_fam10/resourcemap.c
M src/mainboard/tyan/s2912_fam10/resourcemap.c
50 files changed, 61 insertions(+), 61 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/27912/1
diff --git a/src/mainboard/advansus/a785e-i/resourcemap.c b/src/mainboard/advansus/a785e-i/resourcemap.c
index 4f2c074..19181fb 100644
--- a/src/mainboard/advansus/a785e-i/resourcemap.c
+++ b/src/mainboard/advansus/a785e-i/resourcemap.c
@@ -119,7 +119,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c
index 572405d..6372c4b 100644
--- a/src/mainboard/amd/bimini_fam10/mainboard.c
+++ b/src/mainboard/amd/bimini_fam10/mainboard.c
@@ -29,7 +29,7 @@
volatile u8 *gpio_reg;
- pm_iowrite(0xEA, 0x01); /* diable the PCIB */
+ pm_iowrite(0xEA, 0x01); /* disable the PCIB */
/* Disable Gec */
byte = pm_ioread(0xF6);
byte |= 1;
diff --git a/src/mainboard/amd/bimini_fam10/resourcemap.c b/src/mainboard/amd/bimini_fam10/resourcemap.c
index dbd6341..b647f48 100644
--- a/src/mainboard/amd/bimini_fam10/resourcemap.c
+++ b/src/mainboard/amd/bimini_fam10/resourcemap.c
@@ -120,7 +120,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c
index 020bc27..ebe20ac 100644
--- a/src/mainboard/amd/db-ft3b-lc/mptable.c
+++ b/src/mainboard/amd/db-ft3b-lc/mptable.c
@@ -30,7 +30,7 @@
struct mp_config_table *mc;
int bus_isa;
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c
index 92b4d27..7cc635c 100644
--- a/src/mainboard/amd/lamar/mptable.c
+++ b/src/mainboard/amd/lamar/mptable.c
@@ -44,7 +44,7 @@
struct mp_config_table *mc;
int bus_isa;
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/amd/mahogany_fam10/resourcemap.c b/src/mainboard/amd/mahogany_fam10/resourcemap.c
index 95d009a..acdf645 100644
--- a/src/mainboard/amd/mahogany_fam10/resourcemap.c
+++ b/src/mainboard/amd/mahogany_fam10/resourcemap.c
@@ -121,7 +121,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
index c21e0ea..95aec3d 100644
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ b/src/mainboard/amd/persimmon/mainboard.c
@@ -85,7 +85,7 @@
*/
/*
* Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because PCI INT_PIN swizzling isnt implemented to match
+ * but because PCI INT_PIN swizzling isn't implemented to match
* the IDSEL (dev 3) of the slot, the table is adjusted for the
* swizzle and INTA is connected to PIRQH so PINA/B/C/D on
* off-chip devices should get mapped to PIRQH/E/F/G.
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index ccf0958..9e92ae8 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -39,7 +39,7 @@
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
index fd14a80..0e47c52 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
@@ -119,7 +119,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
index d069838..1587d32 100644
--- a/src/mainboard/amd/south_station/mainboard.c
+++ b/src/mainboard/amd/south_station/mainboard.c
@@ -18,7 +18,7 @@
#include <device/device.h>
#include <southbridge/amd/sb800/sb800.h>
-#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
+#include "SBPLATFORM.h" /* Platform Specific Definitions */
/**
* Southstation using SB GPIO 17/18 to control the Red/Green LED
diff --git a/src/mainboard/amd/tilapia_fam10/resourcemap.c b/src/mainboard/amd/tilapia_fam10/resourcemap.c
index d696c4d..5a43814 100644
--- a/src/mainboard/amd/tilapia_fam10/resourcemap.c
+++ b/src/mainboard/amd/tilapia_fam10/resourcemap.c
@@ -119,7 +119,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h
index 04897f5..938de53 100644
--- a/src/mainboard/amd/torpedo/gpio.h
+++ b/src/mainboard/amd/torpedo/gpio.h
@@ -298,8 +298,8 @@
#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE
#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE
// option for HDMI CEC signal OW ACTIVE
-#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active
-#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT
+#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECEIVER, INPUT, low active
+#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERRUPT FROM BATT CHARGER, INPUT
#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA
#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK
#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK,
diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h
index 72a97d1..622fffe 100644
--- a/src/mainboard/amd/torpedo/platform_cfg.h
+++ b/src/mainboard/amd/torpedo/platform_cfg.h
@@ -329,7 +329,7 @@
/**
* @section INCHIP_AZALIA_CONTROLLER INCHIP_AZALIA_CONTROLLER
* @li <b>0</b> - Auto : Detect Azalia controller automatically.
- * @li <b>1</b> - Diable : Disable Azalia controller.
+ * @li <b>1</b> - Disable : Disable Azalia controller.
* @li <b>2</b> - Enable : Enable Azalia controller.
*/
#define INCHIP_AZALIA_CONTROLLER 2
diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c
index 8c71fd6..7ed27d8 100644
--- a/src/mainboard/amd/union_station/mainboard.c
+++ b/src/mainboard/amd/union_station/mainboard.c
@@ -17,7 +17,7 @@
#include <device/device.h>
#include <southbridge/amd/sb800/sb800.h>
-#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
+#include "SBPLATFORM.h" /* Platform Specific Definitions */
/**********************************************
* Enable the dedicated functions of the board.
diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c
index bc7853b..82be639 100644
--- a/src/mainboard/asus/am1i-a/mptable.c
+++ b/src/mainboard/asus/am1i-a/mptable.c
@@ -39,7 +39,7 @@
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c
index 0de14ad..60bc3a7 100644
--- a/src/mainboard/asus/kcma-d8/resourcemap.c
+++ b/src/mainboard/asus/kcma-d8/resourcemap.c
@@ -124,7 +124,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
@@ -379,7 +379,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c
index f4e549b..9644201 100644
--- a/src/mainboard/asus/kfsn4-dre/resourcemap.c
+++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c
@@ -124,7 +124,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c
index dcd7f77..c4dea39 100644
--- a/src/mainboard/asus/kgpe-d16/resourcemap.c
+++ b/src/mainboard/asus/kgpe-d16/resourcemap.c
@@ -124,7 +124,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
@@ -379,7 +379,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c
index 8a017a0..b39f9db 100644
--- a/src/mainboard/asus/m4a78-em/mainboard.c
+++ b/src/mainboard/asus/m4a78-em/mainboard.c
@@ -76,7 +76,7 @@
/*
* justify the dev3 is exist or not
* NOTE: This just copied from AMD Tilapia code.
- * It is completly unknown if it will work at all for this board.
+ * It is completely unknown if it will work at all for this board.
*/
int is_dev3_present(void)
{
diff --git a/src/mainboard/asus/m4a78-em/resourcemap.c b/src/mainboard/asus/m4a78-em/resourcemap.c
index 95d009a..acdf645 100644
--- a/src/mainboard/asus/m4a78-em/resourcemap.c
+++ b/src/mainboard/asus/m4a78-em/resourcemap.c
@@ -121,7 +121,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index 23ead56..00a12cc 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -86,7 +86,7 @@
/*
* justify the dev3 is exist or not
* NOTE: This just copied from AMD Tilapia code.
- * It is completly unknown it it will work at all for ASUS M4A785-M.
+ * It is completely unknown it it will work at all for ASUS M4A785-M.
*/
int is_dev3_present(void)
{
diff --git a/src/mainboard/asus/m4a785-m/resourcemap.c b/src/mainboard/asus/m4a785-m/resourcemap.c
index 95d009a..acdf645 100644
--- a/src/mainboard/asus/m4a785-m/resourcemap.c
+++ b/src/mainboard/asus/m4a785-m/resourcemap.c
@@ -121,7 +121,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/asus/m5a88-v/resourcemap.c b/src/mainboard/asus/m5a88-v/resourcemap.c
index 2978bab..2987b7c 100644
--- a/src/mainboard/asus/m5a88-v/resourcemap.c
+++ b/src/mainboard/asus/m5a88-v/resourcemap.c
@@ -119,7 +119,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/avalue/eax-785e/resourcemap.c b/src/mainboard/avalue/eax-785e/resourcemap.c
index 4f2c074..19181fb 100644
--- a/src/mainboard/avalue/eax-785e/resourcemap.c
+++ b/src/mainboard/avalue/eax-785e/resourcemap.c
@@ -119,7 +119,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c
index bc42bb0..42d8431 100644
--- a/src/mainboard/bap/ode_e20XX/mptable.c
+++ b/src/mainboard/bap/ode_e20XX/mptable.c
@@ -38,7 +38,7 @@
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c
index 1124ad9..dcf4321 100644
--- a/src/mainboard/biostar/am1ml/mptable.c
+++ b/src/mainboard/biostar/am1ml/mptable.c
@@ -38,7 +38,7 @@
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c
index 01d67c4..8f8b735 100644
--- a/src/mainboard/elmex/pcm205400/mainboard.c
+++ b/src/mainboard/elmex/pcm205400/mainboard.c
@@ -84,7 +84,7 @@
*/
/*
* Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because PCI INT_PIN swizzling isnt implemented to match
+ * but because PCI INT_PIN swizzling isn't implemented to match
* the IDSEL (dev 3) of the slot, the table is adjusted for the
* swizzle and INTA is connected to PIRQH so PINA/B/C/D on
* off-chip devices should get mapped to PIRQH/E/F/G.
diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c
index ccf0958..9e92ae8 100644
--- a/src/mainboard/elmex/pcm205400/mptable.c
+++ b/src/mainboard/elmex/pcm205400/mptable.c
@@ -39,7 +39,7 @@
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c
index d91d77a..857365b 100644
--- a/src/mainboard/emulation/qemu-armv7/mainboard.c
+++ b/src/mainboard/emulation/qemu-armv7/mainboard.c
@@ -36,7 +36,7 @@
write32(pl111 + 1, height - 1);
/* registers 2, 3 and 5 are ignored by qemu. Set them correctly if
we ever go for real hw. */
- /* framebuffer adress offset. Has to be in vram. */
+ /* framebuffer address offset. Has to be in vram. */
write32(pl111 + 4, framebuffer);
write32(pl111 + 7, 0);
write32(pl111 + 10, 0xff);
diff --git a/src/mainboard/gigabyte/ma785gm/resourcemap.c b/src/mainboard/gigabyte/ma785gm/resourcemap.c
index 95d009a..acdf645 100644
--- a/src/mainboard/gigabyte/ma785gm/resourcemap.c
+++ b/src/mainboard/gigabyte/ma785gm/resourcemap.c
@@ -121,7 +121,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/gigabyte/ma785gmt/resourcemap.c b/src/mainboard/gigabyte/ma785gmt/resourcemap.c
index 95d009a..acdf645 100644
--- a/src/mainboard/gigabyte/ma785gmt/resourcemap.c
+++ b/src/mainboard/gigabyte/ma785gmt/resourcemap.c
@@ -121,7 +121,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/gigabyte/ma78gm/resourcemap.c b/src/mainboard/gigabyte/ma78gm/resourcemap.c
index 95d009a..acdf645 100644
--- a/src/mainboard/gigabyte/ma78gm/resourcemap.c
+++ b/src/mainboard/gigabyte/ma78gm/resourcemap.c
@@ -121,7 +121,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c
index bc42bb0..42d8431 100644
--- a/src/mainboard/gizmosphere/gizmo2/mptable.c
+++ b/src/mainboard/gizmosphere/gizmo2/mptable.c
@@ -38,7 +38,7 @@
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c
index 33efdf7..24c9034 100644
--- a/src/mainboard/google/daisy/romstage.c
+++ b/src/mainboard/google/daisy/romstage.c
@@ -88,7 +88,7 @@
if (error) {
printk(BIOS_CRIT, "%s: PMIC error: %#x\n", __func__, error);
- die("Failed to intialize PMIC.\n");
+ die("Failed to initialize PMIC.\n");
}
}
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 1268df2..751b40b 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -241,7 +241,7 @@
exception_init();
if (power_init_failed)
- die("Failed to intialize power.\n");
+ die("Failed to initialize power.\n");
/* re-initialize PMIC I2C channel after (re-)setting system clocks */
i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */
diff --git a/src/mainboard/google/urara/urara_boardid.h b/src/mainboard/google/urara/urara_boardid.h
index bc61085..7c7c045 100644
--- a/src/mainboard/google/urara/urara_boardid.h
+++ b/src/mainboard/google/urara/urara_boardid.h
@@ -17,7 +17,7 @@
#define __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__
/*
- * List of URARA derivatives board ID defintions. They are stored in uint8_t
+ * List of URARA derivatives board ID definitions. They are stored in uint8_t
* across the code, using #defines here not to imply any specific size.
*/
#define URARA_BOARD_ID_BUB 0
diff --git a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c b/src/mainboard/iei/kino-780am2-fam10/resourcemap.c
index 95d009a..acdf645 100644
--- a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c
+++ b/src/mainboard/iei/kino-780am2-fam10/resourcemap.c
@@ -121,7 +121,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index 205b655..567a586 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -87,7 +87,7 @@
*/
/*
* Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because PCI INT_PIN swizzling isnt implemented to match
+ * but because PCI INT_PIN swizzling isn't implemented to match
* the IDSEL (dev 3) of the slot, the table is adjusted for the
* swizzle and INTA is connected to PIRQH so PINA/B/C/D on
* off-chip devices should get mapped to PIRQH/E/F/G.
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index 92564c2..a933f60 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -42,7 +42,7 @@
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/jetway/pa78vm5/resourcemap.c b/src/mainboard/jetway/pa78vm5/resourcemap.c
index d6c8608..58b681f 100644
--- a/src/mainboard/jetway/pa78vm5/resourcemap.c
+++ b/src/mainboard/jetway/pa78vm5/resourcemap.c
@@ -122,7 +122,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c
index 610baf3..825f5ae 100644
--- a/src/mainboard/msi/ms9652_fam10/resourcemap.c
+++ b/src/mainboard/msi/ms9652_fam10/resourcemap.c
@@ -122,7 +122,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
index 290a0ed..de94937 100644
--- a/src/mainboard/pcengines/apu1/mainboard.c
+++ b/src/mainboard/pcengines/apu1/mainboard.c
@@ -91,7 +91,7 @@
*/
/*
* The PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because of PCI INT_PIN swizzle isnt implemented to match
+ * but because of PCI INT_PIN swizzle isn't implemented to match
* the IDSEL (dev 3) of the slot, the table is adjusted for the
* swizzle and INTA is connected to PIRQH so PINA/B/C/D on
* off-chip devices should get mapped to PIRQH/E/F/G.
diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c
index b183d8d..94a7d6f 100644
--- a/src/mainboard/pcengines/apu1/mptable.c
+++ b/src/mainboard/pcengines/apu1/mptable.c
@@ -39,7 +39,7 @@
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
index dff5fbd..772ee31 100644
--- a/src/mainboard/pcengines/apu2/mptable.c
+++ b/src/mainboard/pcengines/apu2/mptable.c
@@ -24,7 +24,7 @@
struct mp_config_table *mc;
int bus_isa;
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c
index 347bc9c..89bc293 100644
--- a/src/mainboard/siemens/mc_tcu3/ptn3460.c
+++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c
@@ -38,7 +38,7 @@
return 1;
}
- status = i2c_init(PTN_I2C_CONTROLER);
+ status = i2c_init(PTN_I2C_CONTROLLER);
if (status)
return (PTN_BUS_ERROR | status);
@@ -66,7 +66,7 @@
/* Select this table to be emulated */
ptn_select_edid(6);
/* Read PTN configuration data */
- status = i2c_read(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF,
+ status = i2c_read(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF,
(u8*)&cfg, PTN_CONFIG_LEN);
if (status)
return (PTN_BUS_ERROR | status);
@@ -94,7 +94,7 @@
cfg.backlight_ctrl = 0; /* Enable backlight control */
/* Write back configuration data to PTN3460 */
- status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF,
+ status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF,
(u8*)&cfg, PTN_CONFIG_LEN);
if (status)
return (PTN_BUS_ERROR | status);
@@ -114,13 +114,13 @@
if (edid_num > PTN_MAX_EDID_NUM)
return PTN_INVALID_EDID;
/* First enable access to the desired EDID table */
- status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,
+ status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,
&edid_num, 1);
if (status)
return (PTN_BUS_ERROR | status);
/* Now we can simply read back EDID-data */
- status = i2c_read(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_EDID_OFF,
+ status = i2c_read(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF,
data, PTN_EDID_LEN);
if (status)
return (PTN_BUS_ERROR | status);
@@ -140,13 +140,13 @@
if (edid_num > PTN_MAX_EDID_NUM)
return PTN_INVALID_EDID;
/* First enable access to the desired EDID table */
- status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,
+ status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,
&edid_num, 1);
if (status)
return (PTN_BUS_ERROR | status);
/* Now we can simply write EDID-data to ptn3460 */
- status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_EDID_OFF,
+ status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF,
data, PTN_EDID_LEN);
if (status)
return (PTN_BUS_ERROR | status);
@@ -168,7 +168,7 @@
return PTN_INVALID_EDID;
/* Enable emulation of the desired EDID table */
val = (edid_num << 1) | 1;
- status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4,
+ status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4,
&val, 1);
if (status)
return (PTN_BUS_ERROR | status);
@@ -191,7 +191,7 @@
flash.cmd = 0x01; /* perform erase and flash cycle */
flash.magic = 0x7845; /* Magic number to protect flash operation */
flash.trigger = 0x56; /* This value starts flash operation */
- status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_FLASH_CFG_OFF,
+ status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_FLASH_CFG_OFF,
(u8*)&flash, PTN_FLASH_CFG_LEN);
if (status) {
return (PTN_BUS_ERROR | status);
diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.h b/src/mainboard/siemens/mc_tcu3/ptn3460.h
index e662f61..5988c93 100644
--- a/src/mainboard/siemens/mc_tcu3/ptn3460.h
+++ b/src/mainboard/siemens/mc_tcu3/ptn3460.h
@@ -21,7 +21,7 @@
#include "lcd_panel.h"
#define PTN_SLAVE_ADR 0x20
-#define PTN_I2C_CONTROLER 0
+#define PTN_I2C_CONTROLLER 0
#define PTN_EDID_OFF 0x00
#define PTN_EDID_LEN 0x80
diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
index b35d3e5..d4cbc93 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c
@@ -122,7 +122,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
index b35d3e5..d4cbc93 100644
--- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
+++ b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c
@@ -122,7 +122,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c
index 95d009a..acdf645 100644
--- a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c
+++ b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c
@@ -121,7 +121,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c
index bc03d21..10c97f5 100644
--- a/src/mainboard/tyan/s2912_fam10/resourcemap.c
+++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c
@@ -122,7 +122,7 @@
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
--
To view, visit https://review.coreboot.org/27912
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410
Gerrit-Change-Number: 27912
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180807/802fb85c/attachment-0001.html>
More information about the coreboot-gerrit
mailing list