<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27912">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/mainboard: Fix typo<br><br>Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/advansus/a785e-i/resourcemap.c<br>M src/mainboard/amd/bimini_fam10/mainboard.c<br>M src/mainboard/amd/bimini_fam10/resourcemap.c<br>M src/mainboard/amd/db-ft3b-lc/mptable.c<br>M src/mainboard/amd/lamar/mptable.c<br>M src/mainboard/amd/mahogany_fam10/resourcemap.c<br>M src/mainboard/amd/persimmon/mainboard.c<br>M src/mainboard/amd/persimmon/mptable.c<br>M src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c<br>M src/mainboard/amd/south_station/mainboard.c<br>M src/mainboard/amd/tilapia_fam10/resourcemap.c<br>M src/mainboard/amd/torpedo/gpio.h<br>M src/mainboard/amd/torpedo/platform_cfg.h<br>M src/mainboard/amd/union_station/mainboard.c<br>M src/mainboard/asus/am1i-a/mptable.c<br>M src/mainboard/asus/kcma-d8/resourcemap.c<br>M src/mainboard/asus/kfsn4-dre/resourcemap.c<br>M src/mainboard/asus/kgpe-d16/resourcemap.c<br>M src/mainboard/asus/m4a78-em/mainboard.c<br>M src/mainboard/asus/m4a78-em/resourcemap.c<br>M src/mainboard/asus/m4a785-m/mainboard.c<br>M src/mainboard/asus/m4a785-m/resourcemap.c<br>M src/mainboard/asus/m5a88-v/resourcemap.c<br>M src/mainboard/avalue/eax-785e/resourcemap.c<br>M src/mainboard/bap/ode_e20XX/mptable.c<br>M src/mainboard/biostar/am1ml/mptable.c<br>M src/mainboard/elmex/pcm205400/mainboard.c<br>M src/mainboard/elmex/pcm205400/mptable.c<br>M src/mainboard/emulation/qemu-armv7/mainboard.c<br>M src/mainboard/gigabyte/ma785gm/resourcemap.c<br>M src/mainboard/gigabyte/ma785gmt/resourcemap.c<br>M src/mainboard/gigabyte/ma78gm/resourcemap.c<br>M src/mainboard/gizmosphere/gizmo2/mptable.c<br>M src/mainboard/google/daisy/romstage.c<br>M src/mainboard/google/peach_pit/romstage.c<br>M src/mainboard/google/urara/urara_boardid.h<br>M src/mainboard/iei/kino-780am2-fam10/resourcemap.c<br>M src/mainboard/jetway/nf81-t56n-lf/mainboard.c<br>M src/mainboard/jetway/nf81-t56n-lf/mptable.c<br>M src/mainboard/jetway/pa78vm5/resourcemap.c<br>M src/mainboard/msi/ms9652_fam10/resourcemap.c<br>M src/mainboard/pcengines/apu1/mainboard.c<br>M src/mainboard/pcengines/apu1/mptable.c<br>M src/mainboard/pcengines/apu2/mptable.c<br>M src/mainboard/siemens/mc_tcu3/ptn3460.c<br>M src/mainboard/siemens/mc_tcu3/ptn3460.h<br>M src/mainboard/supermicro/h8dmr_fam10/resourcemap.c<br>M src/mainboard/supermicro/h8qme_fam10/resourcemap.c<br>M src/mainboard/supermicro/h8scm_fam10/resourcemap.c<br>M src/mainboard/tyan/s2912_fam10/resourcemap.c<br>50 files changed, 61 insertions(+), 61 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/27912/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/advansus/a785e-i/resourcemap.c b/src/mainboard/advansus/a785e-i/resourcemap.c</span><br><span>index 4f2c074..19181fb 100644</span><br><span>--- a/src/mainboard/advansus/a785e-i/resourcemap.c</span><br><span>+++ b/src/mainboard/advansus/a785e-i/resourcemap.c</span><br><span>@@ -119,7 +119,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c</span><br><span>index 572405d..6372c4b 100644</span><br><span>--- a/src/mainboard/amd/bimini_fam10/mainboard.c</span><br><span>+++ b/src/mainboard/amd/bimini_fam10/mainboard.c</span><br><span>@@ -29,7 +29,7 @@</span><br><span> </span><br><span> volatile u8 *gpio_reg;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- pm_iowrite(0xEA, 0x01); /* diable the PCIB */</span><br><span style="color: hsl(120, 100%, 40%);">+ pm_iowrite(0xEA, 0x01); /* disable the PCIB */</span><br><span> /* Disable Gec */</span><br><span> byte = pm_ioread(0xF6);</span><br><span> byte |= 1;</span><br><span>diff --git a/src/mainboard/amd/bimini_fam10/resourcemap.c b/src/mainboard/amd/bimini_fam10/resourcemap.c</span><br><span>index dbd6341..b647f48 100644</span><br><span>--- a/src/mainboard/amd/bimini_fam10/resourcemap.c</span><br><span>+++ b/src/mainboard/amd/bimini_fam10/resourcemap.c</span><br><span>@@ -120,7 +120,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c</span><br><span>index 020bc27..ebe20ac 100644</span><br><span>--- a/src/mainboard/amd/db-ft3b-lc/mptable.c</span><br><span>+++ b/src/mainboard/amd/db-ft3b-lc/mptable.c</span><br><span>@@ -30,7 +30,7 @@</span><br><span> struct mp_config_table *mc;</span><br><span> int bus_isa;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Intialize the MP_Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the MP_Table */</span><br><span> mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span> </span><br><span> mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span>diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c</span><br><span>index 92b4d27..7cc635c 100644</span><br><span>--- a/src/mainboard/amd/lamar/mptable.c</span><br><span>+++ b/src/mainboard/amd/lamar/mptable.c</span><br><span>@@ -44,7 +44,7 @@</span><br><span> struct mp_config_table *mc;</span><br><span> int bus_isa;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Intialize the MP_Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the MP_Table */</span><br><span> mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span> </span><br><span> mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span>diff --git a/src/mainboard/amd/mahogany_fam10/resourcemap.c b/src/mainboard/amd/mahogany_fam10/resourcemap.c</span><br><span>index 95d009a..acdf645 100644</span><br><span>--- a/src/mainboard/amd/mahogany_fam10/resourcemap.c</span><br><span>+++ b/src/mainboard/amd/mahogany_fam10/resourcemap.c</span><br><span>@@ -121,7 +121,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c</span><br><span>index c21e0ea..95aec3d 100644</span><br><span>--- a/src/mainboard/amd/persimmon/mainboard.c</span><br><span>+++ b/src/mainboard/amd/persimmon/mainboard.c</span><br><span>@@ -85,7 +85,7 @@</span><br><span> */</span><br><span> /*</span><br><span> * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H</span><br><span style="color: hsl(0, 100%, 40%);">- * but because PCI INT_PIN swizzling isnt implemented to match</span><br><span style="color: hsl(120, 100%, 40%);">+ * but because PCI INT_PIN swizzling isn't implemented to match</span><br><span> * the IDSEL (dev 3) of the slot, the table is adjusted for the</span><br><span> * swizzle and INTA is connected to PIRQH so PINA/B/C/D on</span><br><span> * off-chip devices should get mapped to PIRQH/E/F/G.</span><br><span>diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c</span><br><span>index ccf0958..9e92ae8 100644</span><br><span>--- a/src/mainboard/amd/persimmon/mptable.c</span><br><span>+++ b/src/mainboard/amd/persimmon/mptable.c</span><br><span>@@ -39,7 +39,7 @@</span><br><span> u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);</span><br><span> u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Intialize the MP_Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the MP_Table */</span><br><span> mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span> </span><br><span> mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span>diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c</span><br><span>index fd14a80..0e47c52 100644</span><br><span>--- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c</span><br><span>+++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c</span><br><span>@@ -119,7 +119,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c</span><br><span>index d069838..1587d32 100644</span><br><span>--- a/src/mainboard/amd/south_station/mainboard.c</span><br><span>+++ b/src/mainboard/amd/south_station/mainboard.c</span><br><span>@@ -18,7 +18,7 @@</span><br><span> #include <device/device.h></span><br><span> </span><br><span> #include <southbridge/amd/sb800/sb800.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "SBPLATFORM.h" /* Platfrom Specific Definitions */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "SBPLATFORM.h" /* Platform Specific Definitions */</span><br><span> </span><br><span> /**</span><br><span> * Southstation using SB GPIO 17/18 to control the Red/Green LED</span><br><span>diff --git a/src/mainboard/amd/tilapia_fam10/resourcemap.c b/src/mainboard/amd/tilapia_fam10/resourcemap.c</span><br><span>index d696c4d..5a43814 100644</span><br><span>--- a/src/mainboard/amd/tilapia_fam10/resourcemap.c</span><br><span>+++ b/src/mainboard/amd/tilapia_fam10/resourcemap.c</span><br><span>@@ -119,7 +119,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h</span><br><span>index 04897f5..938de53 100644</span><br><span>--- a/src/mainboard/amd/torpedo/gpio.h</span><br><span>+++ b/src/mainboard/amd/torpedo/gpio.h</span><br><span>@@ -298,8 +298,8 @@</span><br><span> #define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE</span><br><span> #define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE</span><br><span> // option for HDMI CEC signal OW ACTIVE</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECEIVER, INPUT, low active</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERRUPT FROM BATT CHARGER, INPUT</span><br><span> #define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA</span><br><span> #define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK</span><br><span> #define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK,</span><br><span>diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h</span><br><span>index 72a97d1..622fffe 100644</span><br><span>--- a/src/mainboard/amd/torpedo/platform_cfg.h</span><br><span>+++ b/src/mainboard/amd/torpedo/platform_cfg.h</span><br><span>@@ -329,7 +329,7 @@</span><br><span> /**</span><br><span> * @section INCHIP_AZALIA_CONTROLLER INCHIP_AZALIA_CONTROLLER</span><br><span> * @li <b>0</b> - Auto : Detect Azalia controller automatically.</span><br><span style="color: hsl(0, 100%, 40%);">- * @li <b>1</b> - Diable : Disable Azalia controller.</span><br><span style="color: hsl(120, 100%, 40%);">+ * @li <b>1</b> - Disable : Disable Azalia controller.</span><br><span> * @li <b>2</b> - Enable : Enable Azalia controller.</span><br><span> */</span><br><span> #define INCHIP_AZALIA_CONTROLLER 2</span><br><span>diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c</span><br><span>index 8c71fd6..7ed27d8 100644</span><br><span>--- a/src/mainboard/amd/union_station/mainboard.c</span><br><span>+++ b/src/mainboard/amd/union_station/mainboard.c</span><br><span>@@ -17,7 +17,7 @@</span><br><span> #include <device/device.h></span><br><span> </span><br><span> #include <southbridge/amd/sb800/sb800.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "SBPLATFORM.h" /* Platfrom Specific Definitions */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "SBPLATFORM.h" /* Platform Specific Definitions */</span><br><span> </span><br><span> /**********************************************</span><br><span> * Enable the dedicated functions of the board.</span><br><span>diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c</span><br><span>index bc7853b..82be639 100644</span><br><span>--- a/src/mainboard/asus/am1i-a/mptable.c</span><br><span>+++ b/src/mainboard/asus/am1i-a/mptable.c</span><br><span>@@ -39,7 +39,7 @@</span><br><span> u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);</span><br><span> u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Intialize the MP_Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the MP_Table */</span><br><span> mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span> </span><br><span> mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span>diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c</span><br><span>index 0de14ad..60bc3a7 100644</span><br><span>--- a/src/mainboard/asus/kcma-d8/resourcemap.c</span><br><span>+++ b/src/mainboard/asus/kcma-d8/resourcemap.c</span><br><span>@@ -124,7 +124,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>@@ -379,7 +379,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c</span><br><span>index f4e549b..9644201 100644</span><br><span>--- a/src/mainboard/asus/kfsn4-dre/resourcemap.c</span><br><span>+++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c</span><br><span>@@ -124,7 +124,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c</span><br><span>index dcd7f77..c4dea39 100644</span><br><span>--- a/src/mainboard/asus/kgpe-d16/resourcemap.c</span><br><span>+++ b/src/mainboard/asus/kgpe-d16/resourcemap.c</span><br><span>@@ -124,7 +124,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>@@ -379,7 +379,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c</span><br><span>index 8a017a0..b39f9db 100644</span><br><span>--- a/src/mainboard/asus/m4a78-em/mainboard.c</span><br><span>+++ b/src/mainboard/asus/m4a78-em/mainboard.c</span><br><span>@@ -76,7 +76,7 @@</span><br><span> /*</span><br><span> * justify the dev3 is exist or not</span><br><span> * NOTE: This just copied from AMD Tilapia code.</span><br><span style="color: hsl(0, 100%, 40%);">- * It is completly unknown if it will work at all for this board.</span><br><span style="color: hsl(120, 100%, 40%);">+ * It is completely unknown if it will work at all for this board.</span><br><span> */</span><br><span> int is_dev3_present(void)</span><br><span> {</span><br><span>diff --git a/src/mainboard/asus/m4a78-em/resourcemap.c b/src/mainboard/asus/m4a78-em/resourcemap.c</span><br><span>index 95d009a..acdf645 100644</span><br><span>--- a/src/mainboard/asus/m4a78-em/resourcemap.c</span><br><span>+++ b/src/mainboard/asus/m4a78-em/resourcemap.c</span><br><span>@@ -121,7 +121,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c</span><br><span>index 23ead56..00a12cc 100644</span><br><span>--- a/src/mainboard/asus/m4a785-m/mainboard.c</span><br><span>+++ b/src/mainboard/asus/m4a785-m/mainboard.c</span><br><span>@@ -86,7 +86,7 @@</span><br><span> /*</span><br><span> * justify the dev3 is exist or not</span><br><span> * NOTE: This just copied from AMD Tilapia code.</span><br><span style="color: hsl(0, 100%, 40%);">- * It is completly unknown it it will work at all for ASUS M4A785-M.</span><br><span style="color: hsl(120, 100%, 40%);">+ * It is completely unknown it it will work at all for ASUS M4A785-M.</span><br><span> */</span><br><span> int is_dev3_present(void)</span><br><span> {</span><br><span>diff --git a/src/mainboard/asus/m4a785-m/resourcemap.c b/src/mainboard/asus/m4a785-m/resourcemap.c</span><br><span>index 95d009a..acdf645 100644</span><br><span>--- a/src/mainboard/asus/m4a785-m/resourcemap.c</span><br><span>+++ b/src/mainboard/asus/m4a785-m/resourcemap.c</span><br><span>@@ -121,7 +121,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/asus/m5a88-v/resourcemap.c b/src/mainboard/asus/m5a88-v/resourcemap.c</span><br><span>index 2978bab..2987b7c 100644</span><br><span>--- a/src/mainboard/asus/m5a88-v/resourcemap.c</span><br><span>+++ b/src/mainboard/asus/m5a88-v/resourcemap.c</span><br><span>@@ -119,7 +119,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/avalue/eax-785e/resourcemap.c b/src/mainboard/avalue/eax-785e/resourcemap.c</span><br><span>index 4f2c074..19181fb 100644</span><br><span>--- a/src/mainboard/avalue/eax-785e/resourcemap.c</span><br><span>+++ b/src/mainboard/avalue/eax-785e/resourcemap.c</span><br><span>@@ -119,7 +119,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c</span><br><span>index bc42bb0..42d8431 100644</span><br><span>--- a/src/mainboard/bap/ode_e20XX/mptable.c</span><br><span>+++ b/src/mainboard/bap/ode_e20XX/mptable.c</span><br><span>@@ -38,7 +38,7 @@</span><br><span> u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);</span><br><span> u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Intialize the MP_Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the MP_Table */</span><br><span> mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span> </span><br><span> mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span>diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c</span><br><span>index 1124ad9..dcf4321 100644</span><br><span>--- a/src/mainboard/biostar/am1ml/mptable.c</span><br><span>+++ b/src/mainboard/biostar/am1ml/mptable.c</span><br><span>@@ -38,7 +38,7 @@</span><br><span> u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);</span><br><span> u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Intialize the MP_Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the MP_Table */</span><br><span> mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span> </span><br><span> mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span>diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c</span><br><span>index 01d67c4..8f8b735 100644</span><br><span>--- a/src/mainboard/elmex/pcm205400/mainboard.c</span><br><span>+++ b/src/mainboard/elmex/pcm205400/mainboard.c</span><br><span>@@ -84,7 +84,7 @@</span><br><span> */</span><br><span> /*</span><br><span> * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H</span><br><span style="color: hsl(0, 100%, 40%);">- * but because PCI INT_PIN swizzling isnt implemented to match</span><br><span style="color: hsl(120, 100%, 40%);">+ * but because PCI INT_PIN swizzling isn't implemented to match</span><br><span> * the IDSEL (dev 3) of the slot, the table is adjusted for the</span><br><span> * swizzle and INTA is connected to PIRQH so PINA/B/C/D on</span><br><span> * off-chip devices should get mapped to PIRQH/E/F/G.</span><br><span>diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c</span><br><span>index ccf0958..9e92ae8 100644</span><br><span>--- a/src/mainboard/elmex/pcm205400/mptable.c</span><br><span>+++ b/src/mainboard/elmex/pcm205400/mptable.c</span><br><span>@@ -39,7 +39,7 @@</span><br><span> u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);</span><br><span> u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Intialize the MP_Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the MP_Table */</span><br><span> mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span> </span><br><span> mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span>diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c</span><br><span>index d91d77a..857365b 100644</span><br><span>--- a/src/mainboard/emulation/qemu-armv7/mainboard.c</span><br><span>+++ b/src/mainboard/emulation/qemu-armv7/mainboard.c</span><br><span>@@ -36,7 +36,7 @@</span><br><span> write32(pl111 + 1, height - 1);</span><br><span> /* registers 2, 3 and 5 are ignored by qemu. Set them correctly if</span><br><span> we ever go for real hw. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* framebuffer adress offset. Has to be in vram. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* framebuffer address offset. Has to be in vram. */</span><br><span> write32(pl111 + 4, framebuffer);</span><br><span> write32(pl111 + 7, 0);</span><br><span> write32(pl111 + 10, 0xff);</span><br><span>diff --git a/src/mainboard/gigabyte/ma785gm/resourcemap.c b/src/mainboard/gigabyte/ma785gm/resourcemap.c</span><br><span>index 95d009a..acdf645 100644</span><br><span>--- a/src/mainboard/gigabyte/ma785gm/resourcemap.c</span><br><span>+++ b/src/mainboard/gigabyte/ma785gm/resourcemap.c</span><br><span>@@ -121,7 +121,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/gigabyte/ma785gmt/resourcemap.c b/src/mainboard/gigabyte/ma785gmt/resourcemap.c</span><br><span>index 95d009a..acdf645 100644</span><br><span>--- a/src/mainboard/gigabyte/ma785gmt/resourcemap.c</span><br><span>+++ b/src/mainboard/gigabyte/ma785gmt/resourcemap.c</span><br><span>@@ -121,7 +121,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/gigabyte/ma78gm/resourcemap.c b/src/mainboard/gigabyte/ma78gm/resourcemap.c</span><br><span>index 95d009a..acdf645 100644</span><br><span>--- a/src/mainboard/gigabyte/ma78gm/resourcemap.c</span><br><span>+++ b/src/mainboard/gigabyte/ma78gm/resourcemap.c</span><br><span>@@ -121,7 +121,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c</span><br><span>index bc42bb0..42d8431 100644</span><br><span>--- a/src/mainboard/gizmosphere/gizmo2/mptable.c</span><br><span>+++ b/src/mainboard/gizmosphere/gizmo2/mptable.c</span><br><span>@@ -38,7 +38,7 @@</span><br><span> u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);</span><br><span> u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Intialize the MP_Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the MP_Table */</span><br><span> mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span> </span><br><span> mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span>diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c</span><br><span>index 33efdf7..24c9034 100644</span><br><span>--- a/src/mainboard/google/daisy/romstage.c</span><br><span>+++ b/src/mainboard/google/daisy/romstage.c</span><br><span>@@ -88,7 +88,7 @@</span><br><span> </span><br><span> if (error) {</span><br><span> printk(BIOS_CRIT, "%s: PMIC error: %#x\n", __func__, error);</span><br><span style="color: hsl(0, 100%, 40%);">- die("Failed to intialize PMIC.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Failed to initialize PMIC.\n");</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c</span><br><span>index 1268df2..751b40b 100644</span><br><span>--- a/src/mainboard/google/peach_pit/romstage.c</span><br><span>+++ b/src/mainboard/google/peach_pit/romstage.c</span><br><span>@@ -241,7 +241,7 @@</span><br><span> exception_init();</span><br><span> </span><br><span> if (power_init_failed)</span><br><span style="color: hsl(0, 100%, 40%);">- die("Failed to intialize power.\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ die("Failed to initialize power.\n");</span><br><span> </span><br><span> /* re-initialize PMIC I2C channel after (re-)setting system clocks */</span><br><span> i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */</span><br><span>diff --git a/src/mainboard/google/urara/urara_boardid.h b/src/mainboard/google/urara/urara_boardid.h</span><br><span>index bc61085..7c7c045 100644</span><br><span>--- a/src/mainboard/google/urara/urara_boardid.h</span><br><span>+++ b/src/mainboard/google/urara/urara_boardid.h</span><br><span>@@ -17,7 +17,7 @@</span><br><span> #define __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__</span><br><span> </span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- * List of URARA derivatives board ID defintions. They are stored in uint8_t</span><br><span style="color: hsl(120, 100%, 40%);">+ * List of URARA derivatives board ID definitions. They are stored in uint8_t</span><br><span> * across the code, using #defines here not to imply any specific size.</span><br><span> */</span><br><span> #define URARA_BOARD_ID_BUB 0</span><br><span>diff --git a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c b/src/mainboard/iei/kino-780am2-fam10/resourcemap.c</span><br><span>index 95d009a..acdf645 100644</span><br><span>--- a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c</span><br><span>+++ b/src/mainboard/iei/kino-780am2-fam10/resourcemap.c</span><br><span>@@ -121,7 +121,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c</span><br><span>index 205b655..567a586 100644</span><br><span>--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c</span><br><span>+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c</span><br><span>@@ -87,7 +87,7 @@</span><br><span> */</span><br><span> /*</span><br><span> * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H</span><br><span style="color: hsl(0, 100%, 40%);">- * but because PCI INT_PIN swizzling isnt implemented to match</span><br><span style="color: hsl(120, 100%, 40%);">+ * but because PCI INT_PIN swizzling isn't implemented to match</span><br><span> * the IDSEL (dev 3) of the slot, the table is adjusted for the</span><br><span> * swizzle and INTA is connected to PIRQH so PINA/B/C/D on</span><br><span> * off-chip devices should get mapped to PIRQH/E/F/G.</span><br><span>diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c</span><br><span>index 92564c2..a933f60 100644</span><br><span>--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c</span><br><span>+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c</span><br><span>@@ -42,7 +42,7 @@</span><br><span> u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);</span><br><span> u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Intialize the MP_Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the MP_Table */</span><br><span> mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span> </span><br><span> mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span>diff --git a/src/mainboard/jetway/pa78vm5/resourcemap.c b/src/mainboard/jetway/pa78vm5/resourcemap.c</span><br><span>index d6c8608..58b681f 100644</span><br><span>--- a/src/mainboard/jetway/pa78vm5/resourcemap.c</span><br><span>+++ b/src/mainboard/jetway/pa78vm5/resourcemap.c</span><br><span>@@ -122,7 +122,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c</span><br><span>index 610baf3..825f5ae 100644</span><br><span>--- a/src/mainboard/msi/ms9652_fam10/resourcemap.c</span><br><span>+++ b/src/mainboard/msi/ms9652_fam10/resourcemap.c</span><br><span>@@ -122,7 +122,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c</span><br><span>index 290a0ed..de94937 100644</span><br><span>--- a/src/mainboard/pcengines/apu1/mainboard.c</span><br><span>+++ b/src/mainboard/pcengines/apu1/mainboard.c</span><br><span>@@ -91,7 +91,7 @@</span><br><span> */</span><br><span> /*</span><br><span> * The PCI slot INTA/B/C/D connected to PIRQE/F/G/H</span><br><span style="color: hsl(0, 100%, 40%);">- * but because of PCI INT_PIN swizzle isnt implemented to match</span><br><span style="color: hsl(120, 100%, 40%);">+ * but because of PCI INT_PIN swizzle isn't implemented to match</span><br><span> * the IDSEL (dev 3) of the slot, the table is adjusted for the</span><br><span> * swizzle and INTA is connected to PIRQH so PINA/B/C/D on</span><br><span> * off-chip devices should get mapped to PIRQH/E/F/G.</span><br><span>diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c</span><br><span>index b183d8d..94a7d6f 100644</span><br><span>--- a/src/mainboard/pcengines/apu1/mptable.c</span><br><span>+++ b/src/mainboard/pcengines/apu1/mptable.c</span><br><span>@@ -39,7 +39,7 @@</span><br><span> u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);</span><br><span> u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Intialize the MP_Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the MP_Table */</span><br><span> mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span> </span><br><span> mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span>diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c</span><br><span>index dff5fbd..772ee31 100644</span><br><span>--- a/src/mainboard/pcengines/apu2/mptable.c</span><br><span>+++ b/src/mainboard/pcengines/apu2/mptable.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> struct mp_config_table *mc;</span><br><span> int bus_isa;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Intialize the MP_Table */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Initialize the MP_Table */</span><br><span> mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);</span><br><span> </span><br><span> mptable_init(mc, LOCAL_APIC_ADDR);</span><br><span>diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c</span><br><span>index 347bc9c..89bc293 100644</span><br><span>--- a/src/mainboard/siemens/mc_tcu3/ptn3460.c</span><br><span>+++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c</span><br><span>@@ -38,7 +38,7 @@</span><br><span> return 1;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- status = i2c_init(PTN_I2C_CONTROLER);</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_init(PTN_I2C_CONTROLLER);</span><br><span> if (status)</span><br><span> return (PTN_BUS_ERROR | status);</span><br><span> </span><br><span>@@ -66,7 +66,7 @@</span><br><span> /* Select this table to be emulated */</span><br><span> ptn_select_edid(6);</span><br><span> /* Read PTN configuration data */</span><br><span style="color: hsl(0, 100%, 40%);">- status = i2c_read(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_read(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF,</span><br><span> (u8*)&cfg, PTN_CONFIG_LEN);</span><br><span> if (status)</span><br><span> return (PTN_BUS_ERROR | status);</span><br><span>@@ -94,7 +94,7 @@</span><br><span> cfg.backlight_ctrl = 0; /* Enable backlight control */</span><br><span> </span><br><span> /* Write back configuration data to PTN3460 */</span><br><span style="color: hsl(0, 100%, 40%);">- status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF,</span><br><span> (u8*)&cfg, PTN_CONFIG_LEN);</span><br><span> if (status)</span><br><span> return (PTN_BUS_ERROR | status);</span><br><span>@@ -114,13 +114,13 @@</span><br><span> if (edid_num > PTN_MAX_EDID_NUM)</span><br><span> return PTN_INVALID_EDID;</span><br><span> /* First enable access to the desired EDID table */</span><br><span style="color: hsl(0, 100%, 40%);">- status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,</span><br><span> &edid_num, 1);</span><br><span> if (status)</span><br><span> return (PTN_BUS_ERROR | status);</span><br><span> </span><br><span> /* Now we can simply read back EDID-data */</span><br><span style="color: hsl(0, 100%, 40%);">- status = i2c_read(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_EDID_OFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_read(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF,</span><br><span> data, PTN_EDID_LEN);</span><br><span> if (status)</span><br><span> return (PTN_BUS_ERROR | status);</span><br><span>@@ -140,13 +140,13 @@</span><br><span> if (edid_num > PTN_MAX_EDID_NUM)</span><br><span> return PTN_INVALID_EDID;</span><br><span> /* First enable access to the desired EDID table */</span><br><span style="color: hsl(0, 100%, 40%);">- status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 5,</span><br><span> &edid_num, 1);</span><br><span> if (status)</span><br><span> return (PTN_BUS_ERROR | status);</span><br><span> </span><br><span> /* Now we can simply write EDID-data to ptn3460 */</span><br><span style="color: hsl(0, 100%, 40%);">- status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_EDID_OFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_EDID_OFF,</span><br><span> data, PTN_EDID_LEN);</span><br><span> if (status)</span><br><span> return (PTN_BUS_ERROR | status);</span><br><span>@@ -168,7 +168,7 @@</span><br><span> return PTN_INVALID_EDID;</span><br><span> /* Enable emulation of the desired EDID table */</span><br><span> val = (edid_num << 1) | 1;</span><br><span style="color: hsl(0, 100%, 40%);">- status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4,</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_CONFIG_OFF + 4,</span><br><span> &val, 1);</span><br><span> if (status)</span><br><span> return (PTN_BUS_ERROR | status);</span><br><span>@@ -191,7 +191,7 @@</span><br><span> flash.cmd = 0x01; /* perform erase and flash cycle */</span><br><span> flash.magic = 0x7845; /* Magic number to protect flash operation */</span><br><span> flash.trigger = 0x56; /* This value starts flash operation */</span><br><span style="color: hsl(0, 100%, 40%);">- status = i2c_write(PTN_I2C_CONTROLER, PTN_SLAVE_ADR, PTN_FLASH_CFG_OFF,</span><br><span style="color: hsl(120, 100%, 40%);">+ status = i2c_write(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, PTN_FLASH_CFG_OFF,</span><br><span> (u8*)&flash, PTN_FLASH_CFG_LEN);</span><br><span> if (status) {</span><br><span> return (PTN_BUS_ERROR | status);</span><br><span>diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.h b/src/mainboard/siemens/mc_tcu3/ptn3460.h</span><br><span>index e662f61..5988c93 100644</span><br><span>--- a/src/mainboard/siemens/mc_tcu3/ptn3460.h</span><br><span>+++ b/src/mainboard/siemens/mc_tcu3/ptn3460.h</span><br><span>@@ -21,7 +21,7 @@</span><br><span> #include "lcd_panel.h"</span><br><span> </span><br><span> #define PTN_SLAVE_ADR 0x20</span><br><span style="color: hsl(0, 100%, 40%);">-#define PTN_I2C_CONTROLER 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PTN_I2C_CONTROLLER 0</span><br><span> </span><br><span> #define PTN_EDID_OFF 0x00</span><br><span> #define PTN_EDID_LEN 0x80</span><br><span>diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c</span><br><span>index b35d3e5..d4cbc93 100644</span><br><span>--- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c</span><br><span>+++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c</span><br><span>@@ -122,7 +122,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c</span><br><span>index b35d3e5..d4cbc93 100644</span><br><span>--- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c</span><br><span>+++ b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c</span><br><span>@@ -122,7 +122,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c</span><br><span>index 95d009a..acdf645 100644</span><br><span>--- a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c</span><br><span>+++ b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c</span><br><span>@@ -121,7 +121,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span>diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c</span><br><span>index bc03d21..10c97f5 100644</span><br><span>--- a/src/mainboard/tyan/s2912_fam10/resourcemap.c</span><br><span>+++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c</span><br><span>@@ -122,7 +122,7 @@</span><br><span> * 0 = CPU writes may be posted</span><br><span> * 1 = CPU writes must be non-posted</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span style="color: hsl(0, 100%, 40%);">- * This field defines the upp adddress bits of a 40-bit address that</span><br><span style="color: hsl(120, 100%, 40%);">+ * This field defines the upp address bits of a 40-bit address that</span><br><span> * defines the end of a memory-mapped I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27912">change 27912</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27912"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 </div>
<div style="display:none"> Gerrit-Change-Number: 27912 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>