Author: wmb Date: 2009-06-25 23:13:27 +0200 (Thu, 25 Jun 2009) New Revision: 1222
Added: cpu/x86/pc/olpc/via/acpi.fth cpu/x86/pc/olpc/via/dsdt.dsl cpu/x86/pc/olpc/via/rtcwake.fth Log: Checked in new files
Added: cpu/x86/pc/olpc/via/acpi.fth =================================================================== --- cpu/x86/pc/olpc/via/acpi.fth (rev 0) +++ cpu/x86/pc/olpc/via/acpi.fth 2009-06-25 21:13:27 UTC (rev 1222) @@ -0,0 +1,577 @@ +\ Make some ACPI descriptor tables + +h# 0. 2constant xsdt-adr + +create fadt +( 000 4 ) " FACP" $, \ Signature +( 004 4 ) h# 84 l, \ Table Length +( 008 1 ) h# 02 c, \ Revision (supports reset adr) +( 009 1 ) h# 00 c, \ Checksum +( 00A 6 ) " OLPC " $, \ Oem ID +( 010 8 ) " OLPC_000" $, \ Oem Table ID +( 018 4 ) " 0000" $, \ Oem Revision +( 01C 4 ) " OLPC" $, \ Asl Compiler ID +( 020 4 ) " 0000" $, \ Asl Compiler Revision +( 024 4 ) facs-adr l, \ FACS Address +( 028 4 ) dsdt-adr l, \ DSDT Address +( 02C 1 ) h# 00 c, \ Was Model, now reserved +( 02D 1 ) h# 00 c, \ PM Profile +( 02E 2 ) h# 000a w, \ SCI Interrupt + +\ Setting all of these to 0 tells the OS that the system is always in ACPI mode +( 030 4 ) h# 0 l, \ SMI Command Port +( 034 1 ) h# 0 c, \ ACPI Enable Value +( 035 1 ) h# 0 c, \ ACPI Disable Value + +( 036 1 ) h# 00 c, \ S4BIOS Command +( 037 1 ) h# 00 c, \ P-State Control +( 038 4 ) h# 400 l, \ PM1A Event Block Address +( 03C 4 ) h# 0 l, \ PM1B Event Block Address +\ ( 040 4 ) h# 9c28 l, \ PM1A Control Block Address +( 040 4 ) h# 404 l, \ PM1A Control Block Address +( 044 4 ) h# 0 l, \ PM1B Control Block Address +( 048 4 ) h# 0 l, \ PM2 Control Block Address (don't support) +\ ( 04C 4 ) h# 9c10 l, \ PM Timer Block Address +( 04C 4 ) h# 408 l, \ PM Timer Block Address +( 050 4 ) h# 420 l, \ GPE0 Block Address +( 054 4 ) h# 0 l, \ GPE1 Block Address +( 058 1 ) h# 4 c, \ PM1 Event Block Length +( 059 1 ) h# 2 c, \ PM1 Control Block Length +( 05A 1 ) h# 0 c, \ PM2 Control Block Length +( 05B 1 ) h# 4 c, \ PM Timer Block Length +( 05C 1 ) h# 4 c, \ GPE0 Block Length +( 05D 1 ) h# 0 c, \ GPE1 Block Length +( 05E 1 ) h# 10 c, \ GPE1 Base Offset +( 05F 1 ) h# 85 c, \ _CST Support +( 060 2 ) h# 1 w, \ C2 Latency +( 062 2 ) h# 1 w, \ C3 Latency +( 064 2 ) h# 0 w, \ CPU Cache Size +( 066 2 ) h# 0 w, \ Cache Flush Stride +( 068 1 ) h# 0 c, \ Duty Cycle Offset +( 069 1 ) h# 4 c, \ Duty Cycle Width +( 06A 1 ) h# 7d c, \ RTC Day Alarm Index +( 06B 1 ) h# 7e c, \ RTC Month Alarm Index +( 06C 1 ) h# 7f c, \ RTC Century Index +( 06D 2 ) h# 0 w, \ Boot Architecture Flags +( 06F 1 ) h# 0 c, \ Reserved +( 070 4 ) h# 5a5 l, \ Flags - see below for bit definitions +( 074 12 ) 1 c, 8 c, 0 c, 1 c, h# 92. d, \ Reset register - I/O, 8 bits, 0 offset, byte access + +( 080 1 ) h# 1 c, \ Reset value +( 081 3 ) 0 c, 0 c, 0 c, \ Reserved +here fadt - constant /fadt + +\ FADT Flags: +\ WBINVD is operational : 1 +\ WBINVD does not invalidate : 0 +\ All CPUs support C1 : 1 +\ C2 works on MP system : 0 +\ Power button is generic : 0 +\ Sleep button is generic : 1 +\ RTC wakeup not fixed : 0 +\ RTC wakeup/S4 not possible : 1 +\ 32-bit PM Timer : 1 +\ Docking Supported : 0 +\ Reset Register Supported: 1 + +create rsdp +( 00 8 ) " RSD PTR " $, \ Signature +( 08 1 ) 00 c, \ Checksum +( 09 6 ) " OLPC " $, \ Oem Id +( 0f 1 ) 2 c, \ ACPI revision (3.0b) +( 10 4 ) rsdt-adr l, \ RSDT Address + +( 14 4 ) d# 36 l, \ Length for extended version +( 18 8 ) xsdt-adr d, \ XSDT Address +( 20 1 ) 0 c, \ extended checksum +( 21 3 ) 0 c, 0 c, 0 c, \ reserved +here rsdp - constant /rsdp + +create madt \ Multiple APIC Descriptor Table +( 000 4 ) " APIC" $, \ Signature +( 004 4 ) h# 5a l, \ Table Length +( 008 1 ) h# 01 c, \ Revision +( 009 1 ) h# 00 c, \ Checksum +( 00A 6 ) " OLPC " $, \ Oem ID +( 010 8 ) " OLPC_000" $, \ Oem Table ID +( 018 4 ) " 0000" $, \ Oem Revision +( 01C 4 ) " OLPC" $, \ Asl Compiler ID +( 020 4 ) " 0000" $, \ Asl Compiler Revision +( 024 4 ) apic-mmio-base l, \ APIC base address +( 028 4 ) 1 l, \ Flags - 1 means that an 8259 PIC is present too + +( 02c 1 ) 0 c, \ Processor-local APIC +( 02d 1 ) 8 c, \ length +( 02e 1 ) 0 c, \ processor ID +( 02f 1 ) 0 c, \ ACPI ID +( 030 4 ) 1 l, \ Flags - 1 means this processor is usable + + +( 034 1 ) 1 c, \ I/O APIC +( 035 1 ) d# 12 c, \ length +( 036 1 ) 1 c, \ I/O APIC ID +( 037 1 ) 0 c, \ reserved +( 038 4 ) io-apic-mmio-base l, \ I/O APIC base address +( 03c 4 ) 0 l, \ Global system interrupt base + +( 040 1 ) 4 c, \ local APIC NMI +( 041 1 ) 6 c, \ length +( 042 1 ) 0 c, \ processor ID +( 043 2 ) 5 w, \ flags - edge-triggered, active high +( 045 1 ) 1 c, \ Local APIC LINT# + +( 046 1 ) 2 c, \ Int src override (for PIT timer) +( 047 1 ) d# 10 c, \ length +( 048 1 ) 0 c, \ Bus - ISA +( 049 1 ) 0 c, \ Bus-relative IRQ +( 04a 4 ) 2 l, \ Interrupt # that this source will trigger +( 04e 2 ) 5 w, \ flags - edge-triggered, active high + +( 050 1 ) 2 c, \ Int src override +( 051 1 ) d# 10 c, \ length +( 052 1 ) 0 c, \ Bus - ISA +( 053 1 ) 9 c, \ Bus-relative IRQ +( 054 4 ) 9 l, \ Interrupt # that this source will trigger +( 058 2 ) h# f w, \ Flags - active low, level triggered +here madt - constant /madt + +create hpet \ High Precision Event Timer table +( 000 4 ) " HPET" $, \ Signature +( 004 4 ) h# 38 l, \ Table Length +( 008 1 ) h# 01 c, \ Revision +( 009 1 ) h# 00 c, \ Checksum +( 00A 6 ) " OLPC " $, \ Oem ID +( 010 8 ) " OLPC_000" $, \ Oem Table ID +( 018 4 ) " 0000" $, \ Oem Revision +( 01C 4 ) " OLPC" $, \ Asl Compiler ID +( 020 4 ) " 0000" $, \ Asl Compiler Revision + +( 024 4 ) h# 11068201 l, \ Hardware ID of event timer block - 1106 is PCI VID, rest are misc, see HPET spec +( 028 1 ) 0 c, \ ID +( 029 1 ) 0 c, \ Bit width +( 02a 1 ) 0 c, \ Bit offset +( 02b 1 ) 0 c, \ Access width +( 02c 8 ) hpet-mmio-base d, \ HPET base address +( 034 1 ) 0 c, \ Sequence +( 035 2 ) 0 w, \ Min tick +( 037 1 ) 0 c, \ flags +here hpet - constant /hpet + +create rsdt +( 00 4 ) " RSDT" $, \ Signature +( 04 4 ) h# 34 l, \ Length +\ ( 04 4 ) h# 30 l, \ Length +\ ( 04 4 ) h# 2c l, \ Length +( 08 1 ) 1 c, \ Revision +( 09 1 ) 00 c, \ Checksum +( 0a 6 ) " OLPC " $, \ Oem Id +( 10 8 ) " OLPC_000" $, \ Oem Table Id +( 18 4 ) " 0000" $, \ Oem revision +( 1c 4 ) " OLPC" $, \ Creator ID +( 20 4 ) " 0000" $, \ Creator revision +( 24 4 ) fadt-adr l, \ FADT Address +( 28 4 ) dsdt-adr l, \ DSDT Address +( 2c 4 ) madt-adr l, \ MADT Address +( 30 4 ) hpet-adr l, \ HPET Address +\ ( 2c 4 ) dbgp-adr l, \ DBGP Address +\ ( 30 4 ) ssdt-adr l, \ SSDT Address +\ ( 30 4 ) prtn-adr l, \ PRTN Address +here rsdt - constant /rsdt + +0 [if] +create dbgp +( 00 4 ) " DBGP" $, \ Signature +( 04 4 ) d# 52 l, \ Length +( 08 1 ) 1 c, \ Revision +( 09 1 ) 00 c, \ Checksum +( 0a 6 ) " OLPC " $, \ Oem Id +( 10 8 ) " OLPC_000" $, \ Oem Table Id +( 18 4 ) " 0000" $, \ Oem revision +( 1c 4 ) " OLPC" $, \ Creator ID +( 20 4 ) " 0000" $, \ Creator revision +( 24 1 ) 0 c, \ Full 16550 interface +( 25 3 ) 0 c, 0 c, 0 c, \ reserved +( 28 c ) 1 c, 8 c, 0 c, 1 c, h# 3f8 l, 0 l, \ Port base address (generic register descriptor) +here dbgp - constant /dbgp +[then] + +create facs +( 00 4 ) " FACS" $, \ Signature +( 04 4 ) h# 40 l, \ Length +( 08 4 ) h# 1234 l, \ Hardware signature +( 0c 4 ) 0 l, \ Waking vector +( 10 4 ) 0 l, \ Global lock +( 14 4 ) 0 l, \ Flags +( 18 8 ) 0. d, \ 64-bit waking vector +( 20 1 ) 1 c, \ Version +( 21 1f ) here d# 31 dup allot erase +here facs - constant /facs + +: fix-checksum ( table /table checksum-offset -- ) + >r over >r ( table /table r: cksum-offset table ) + 0 -rot bounds ?do i c@ + loop ( sum ) + negate h# ff and r> r> + c! +; + +: memory-limit ( -- limit ) + " /memory" find-package 0= abort" No /memory node" ( phandle ) + " available" rot get-package-property abort" No available property" ( $ ) + -1 >r ( $ ) ( r: limit ) + begin dup 0> while ( $ ) + decode-int >r decode-int r> + ( $ piece-end ) + dup 1meg u<= if drop else ( $ piece-end ) + r> umin >r ( $ ) ( r: limit' ) + then ( $ ) + repeat ( $ ) + 2drop r> ( limit ) + h# 1000 - \ Safety page +; + +: setup-acpi ( -- ) +[ifdef] notdef + \ This has to agree with the _SB's _INI method, which gets the memory size + \ from offset h# 180 in the EBDA + memory-limit d# 10 rshift 'ebda h# 180 + l! +[then] + + \ Copy rsdt and fadt to low memory + rsdp rsdp-adr /rsdp move rsdp-adr h# 14 8 fix-checksum rsdp-adr /rsdp h# 20 fix-checksum + rsdt rsdt-adr /rsdt move rsdt-adr /rsdt 9 fix-checksum + fadt fadt-adr /fadt move fadt-adr /fadt 9 fix-checksum + madt madt-adr /madt move madt-adr /madt 9 fix-checksum + hpet hpet-adr /hpet move hpet-adr /hpet 9 fix-checksum +\ dbgp dbgp-adr /dbgp move dbgp-adr /dbgp 9 fix-checksum + facs facs-adr /facs move + + \ Copy in the DSDT + \ I suppose we could point to it in FLASH - if so don't compress it, + \ and fixup the address in the fadt and rechecksum the fadt + " dsdt" find-drop-in 0= abort" No DSDT " ( adr len ) + 2dup dsdt-adr swap move free-mem + +[ifdef] notdef + \ Copy in the SSDT + \ I suppose we could point to it in FLASH - if so don't compress it, + \ and fixup the address in the fadt and rechecksum the fadt + " ssdt" find-drop-in 0= abort" No SSDT " ( adr len ) + 2dup ssdt-adr swap move free-mem +[then] + + 4 acpi-w@ 1 or 4 acpi-w! \ Set SCI_EN bit + h# ffffffff h# 20 acpi-l! \ Ack all leftover events +; + +.( Not setting up ACPI automatically) cr +stand-init: ACPI tables +." Not setting up ACPI automatically" cr +\ setup-acpi +; + +\ Geode h# 6000 constant xp-smbus-base + +defer more-platform-fixup ' noop to more-platform-fixup +: rm-platform-fixup ( -- ) +[ifdef] Later +Geode xp-smbus-base h# f001 h# 5140.000b 3dup msr! find-msr-entry 2! +Geode xp-smbus-base 1+ h# 10 isa-hdr >hdr-value l! + + begin sci-queue@ 0= until \ Clean out the SCI queue + h# 20 acpi-w@ h# 20 acpi-w! \ Ack outstanding events +Geode h# 4e sci-mask! \ Include in the mask only events we care about + +Geode 0 h# 40 pm! \ Restore long delay for power-off button +[then] + more-platform-fixup +; + +0 [if] +===== +APIC @ 0x3beb6f32 + 0000: 41 50 49 43 5a 00 00 00 01 3c 50 54 4c 54 44 20 APICZ....<PTLTD + 0010: 09 20 41 50 49 43 20 20 00 00 04 06 20 4c 54 50 . APIC .... LTP + 0020: 00 00 00 00 + 00 00 e0 fe address of local apic + 01 00 00 00 flags - 1 means that an ISA PIC is present too + + 00 Processor-local APIC 08 length + 00 processor ID + 00 ACPI ID + 0030: 01 00 00 00 flags - 1 means usable + + 01 I/O APIC 0c length + 01 I/O APIC ID + 00 reserved + + 00 00 c0 fe I/O APIC address MMIO Address + 00 00 00 00 Global system interrupt base + + 0040: 04 local APIC NMI 06 length + 00 processor ID + 05 00 flags - edge-triggered, active high + 01 Local APIC LINT# + + 02 Int src override 0a length + 00 Bus - ISA + 00 Bus-relative IRQ + 02 00 00 00 Interrupt # that this source will trigger + 05 00 flags - edge-triggered, active high + + 0050: 02 Int src override 0a length + 00 Bus - ISA + 09 Bus-relative IRQ + 09 00 00 00 Interrupt # that this source will trigger + 0f 00 Flags - active low, level triggered + +MCFG is for memory-mapped PCI config space - unnecessary for us +MCFG @ 0x3beb6f8c + 0000: 4d 43 46 47 + 4 0000003c len + 8 01 rev + 9 67 csum + a "PTLTD " OEM ID + 0010: " MCFG " OEM Table ID + 0018: 00 00 04 06 OEM revision # + 1c: " LTP" Compiler ID + 0020: 00000000 compiler rev + 24: 00 00 00 00 00 00 00 00 reserved + 2c e0000000 00000000 BaseAddress.64 + 34: 0000 pci segment group # + 36: 00 start bus # + 37: 00 end bus # + 38: 00 00 00 00 res + +HPET @ 0x3beb6fc8 + 0000: 48 50 45 54 + 4: 00000038 length + 8: 01 rev + 9: 38 csum + a: "PTLTD " OEM ID + 0010: "HPETTBL " OEM table ID + 00 00 04 06 OEM revision # + 1c: " LTP" Compiler ID + 0020: 00000001 Compiler revision ID + 24: 01 82 06 11 hardware ID of event timer block + 28: 00 00 00 00 id bit_width bit_offset access_width + 2c: fed00000 00000000 address + 34: 00 0000 00 seq, min tick, flags + +XSDT @ 0x3beb2a81 + 0000: 58 53 44 54 4c 00 00 00 01 a2 50 54 4c 54 44 20 XSDTL.....PTLTD + 0010: 09 20 58 53 44 54 20 20 00 00 04 06 20 4c 54 50 . XSDT .... LTP + 0020: 00 00 00 00 + Pointers: +84 69 eb 3b 00 00 00 00 +78 6a eb 3b 00 00 00 00 +32 6f eb 3b 00 00 00 00 +8c 6f eb 3b 00 00 00 00 +c8 6f eb 3b 00 00 00 00 + +FACP @ 0x3beb6910 + 0000: 46 41 43 50 74 00 00 00 01 f6 56 58 38 35 35 20 FACPt.....VX855 + 0010: 50 54 4c 54 57 20 20 20 00 00 04 06 50 54 4c 5f PTLTW ....PTL_ + 0020: 40 42 0f 00 + c0 7f eb 3b &facs + cd 2a eb 3b &dsdt + 00 00 model, preferred profile + 0a 00 sci_interrupt !!! + 0030: 2f 40 00 00 sci_command port + 34 f0 acpi_enable + 35 f1 acpi_disable + 36 00 s4bios_request value + 37 80 pstate control + 38 00 40 00 00 pm1a event block + 3c 00 00 00 00 pm1b event block + 0040: 04 40 00 00 pm1a control block + 00 00 00 00 pm1b control block + 22 00 00 00 pm2 control block + 08 40 00 00 pm_timer block + 0050: 20 40 00 00 gpe0_block + 00 00 00 00 gpe1_block + 04 pm1 event block len + 02 pm1 control block len + 01 pm2 control block len + 04 pm timer block length + 04 gpe0 block len + 00 gpe1 block len + 10 gpe1 base offset + 85 _cst latency + 0060: 01 00 C2_latency + 01 00 C3_latency + 00 00 CPU cache size + 00 00 cache flus stride + 00 duty cycle offset + 04 duty cycle width + 7d rtc day alarm indes + 7e rtc month alarm index + 32 rtc century index + 00 00 boot architecture flags + 00 reserved + 0070: a5 00 00 00 flags + +RSDT @ 0x3beb2a49 + 0000: 52 53 44 54 38 00 00 00 01 1f 50 54 4c 54 44 20 RSDT8.....PTLTD + 0010: 20 20 52 53 44 54 20 20 00 00 04 06 20 4c 54 50 RSDT .... LTP + 0020: 00 00 00 00 + Pointers + 24 10 69 eb 3b + 78 6a eb 3b + 32 6f eb 3b + 0030: 8c 6f eb 3b + c8 6f eb 3b + +RSD PTR @ 0xf7c70 + 0000: 52 53 44 20 50 54 52 20 9e 50 54 4c 54 44 20 02 RSD PTR .PTLTD . + 0010: 49 2a eb 3b rsdt-adr + 24 00 00 00 len + 81 2a eb 3b 00 00 00 00 xdst-adr + 0020: 0b ext-csum res + 00 00 00 .... + +FACS @ 0x3beb7fc0 + 0000: 46 41 43 53 signature + 40 00 00 00 len + 00 00 00 00 HW signature + 00 00 00 00 waking vector + 0010: 00 00 00 00 global lock + 00 00 00 00 flags + 00 00 00 00 00 00 00 00 64-bit waking vector + 0020: 01 00 00 00 version + 00 00 00 00 00 00 00 00 00 00 00 00 working area + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 working area + +FACP @ 0x3beb6984 (version 3, 244 bytes) + 0000: 46 41 43 50 f4 00 00 00 03 27 56 58 38 35 35 20 FACP.....'VX855 + 0010: 50 54 4c 54 57 20 20 20 00 00 04 06 50 54 4c 5f PTLTW ....PTL_ + 0020: 40 42 0f 00 + c0 7f eb 3b facs-adr + cd 2a eb 3b dsdt-adr + 00 res + 00 pm-profile + 0a 00 sci-interrupt + 0030: 2f 40 00 00 + f0 + f1 + 00 + 80 + 00 40 00 00 + 00 00 00 00 /@.......@...... + 0040: 04 40 00 00 + 00 00 00 00 + 22 00 00 00 + 08 40 00 00 + 0050: 20 40 00 00 + 00 00 00 00 + 04 + 02 + 01 + 04 + 04 + 00 + 10 + 85 + 0060: 01 00 + 01 00 + 00 00 + 00 00 + 00 + 04 + 7d + 7e + 32 + 00 00 + 00 + 0070: a5 00 00 00 + + 00 00 00 00 00 00 00 00 00 00 00 00 reset register + 0080: 00 reset value + 00 00 00 res + c0 7f eb 3b 00 00 00 00 facs-adr-64 + cd 2a eb 3b 00 00 00 00 dsdt-adr-64 + 94: 01 20 00 00 00 40 00 00 00 00 00 00 pm1a-event-reg-block + 00a0: 00 00 00 00 00 00 00 00 00 00 00 00 pm1b-event-reg-block + 01 10 00 00 04 40 00 00 00 00 00 00 pm1a-cnt-block + b8: 00 00 00 00 00 00 00 00 00 00 00 00 pm1b-cnt-block + 01 08 00 00 22 00 00 00 00 00 00 00 pm2-cnt-block + 00d0: 01 20 00 00 08 40 00 00 00 00 00 00 pm_tmr_block + 01 20 00 00 20 40 00 00 00 00 00 00 gpe0-block + 00 00 00 00 00 00 00 00 00 00 00 00 gpe1-block + +SSDT @ 0x3beb6a78 + 0000: 53 53 44 54 ba 04 00 00 01 3c 50 50 6d 6d 52 65 SSDT.....<PPmmRe + 0010: 50 50 6d 00 00 00 00 00 00 00 04 06 49 4e 54 4c PPm.........INTL + 0020: 24 02 03 20 10 45 49 5c 2e 5f 50 52 5f 43 50 55 $.. .EI._PR_CPU + 0030: 30 08 50 44 43 54 0a 00 08 50 44 43 52 0a 01 08 0.PDCT...PDCR... + 0040: 50 44 43 4d 0a 01 14 4c 06 5f 50 44 43 01 70 87 PDCM...L._PDC.p. + 0050: 68 60 08 50 44 43 42 11 03 0a 14 70 68 50 44 43 h`.PDCB....phPDC + 0060: 42 8a 50 44 43 42 0a 00 52 45 56 5f 8a 50 44 43 B.PDCB..REV_.PDC + 0070: 42 0a 04 53 49 5a 45 a0 0e 92 93 52 45 56 5f 50 B..SIZE....REV_P + 0080: 44 43 52 a4 0a 00 a0 0b 95 53 49 5a 45 0a 01 a4 DCR......SIZE... + 0090: 0a 00 8a 50 44 43 42 0a 08 44 41 54 30 a0 12 7b ...PDCB..DAT0..{ + 00a0: 44 41 54 30 50 44 43 4d 00 70 0a 01 50 44 43 54 DAT0PDCM.p..PDCT + 00b0: a4 0a 01 08 50 43 54 31 12 2c 02 11 14 0a 11 82 ....PCT1.,...... + 00c0: 0c 00 7f 00 00 00 00 00 00 00 00 00 00 00 79 00 ..............y. + 00d0: 11 14 0a 11 82 0c 00 7f 00 00 00 00 00 00 00 00 ................ + 00e0: 00 00 00 79 00 08 50 43 54 32 12 2c 02 11 14 0a ...y..PCT2.,.... + 00f0: 11 82 0c 00 01 08 00 00 2f 40 00 00 00 00 00 00 ......../@...... + 0100: 79 00 11 14 0a 11 82 0c 00 01 08 00 00 80 00 00 y............... + 0110: 00 00 00 00 00 79 00 08 58 43 54 31 12 2c 02 11 .....y..XCT1.,.. + 0120: 14 0a 11 82 0c 00 7f 40 00 00 99 01 00 00 00 00 .......@........ + 0130: 00 00 79 00 11 14 0a 11 82 0c 00 7f 40 00 00 00 ..y.........@... + 0140: 00 00 00 00 00 00 00 79 00 14 37 5f 50 43 54 00 .......y..7_PCT. + 0150: a0 19 5c 5f 4f 53 49 0d 57 69 6e 64 6f 77 73 20 .._OSI.Windows + 0160: 32 30 30 36 00 a4 58 43 54 31 a1 16 a0 0d 93 50 2006..XCT1.....P + 0170: 44 43 54 0a 00 a4 50 43 54 32 a1 06 a4 50 43 54 DCT...PCT2...PCT + 0180: 31 08 58 50 53 53 12 4b 1b 02 12 36 08 0c e8 03 1.XPSS.K...6.... + 0190: 00 00 0c 10 27 00 00 0c 0a 00 00 00 0c 0a 00 00 ....'........... + 01a0: 00 11 07 0a 04 06 0a 00 00 11 07 0a 04 00 00 00 ................ + 01b0: 00 11 07 0a 04 00 00 00 00 11 07 0a 04 06 0a 00 ................ + 01c0: 00 12 36 08 0c 90 01 00 00 0c a0 0f 00 00 0c 0a ..6............. + 01d0: 00 00 00 0c 0a 00 00 00 11 07 0a 04 06 04 00 00 ................ + 01e0: 11 07 0a 04 00 00 00 00 11 07 0a 04 00 00 00 00 ................ + 01f0: 11 07 0a 04 06 04 00 00 12 36 08 0c 90 01 00 00 .........6...... + 0200: 0c a0 0f 00 00 0c 0a 00 00 00 0c 0a 00 00 00 11 ................ + 0210: 07 0a 04 06 04 00 00 11 07 0a 04 00 00 00 00 11 ................ + 0220: 07 0a 04 00 00 00 00 11 07 0a 04 06 04 00 00 12 ................ + 0230: 36 08 0c 90 01 00 00 0c a0 0f 00 00 0c 0a 00 00 6............... + 0240: 00 0c 0a 00 00 00 11 07 0a 04 06 04 00 00 11 07 ................ + 0250: 0a 04 00 00 00 00 11 07 0a 04 00 00 00 00 11 07 ................ + 0260: 0a 04 06 04 00 00 12 36 08 0c 90 01 00 00 0c a0 .......6........ + 0270: 0f 00 00 0c 0a 00 00 00 0c 0a 00 00 00 11 07 0a ................ + 0280: 04 06 04 00 00 11 07 0a 04 00 00 00 00 11 07 0a ................ + 0290: 04 00 00 00 00 11 07 0a 04 06 04 00 00 12 36 08 ..............6. + 02a0: 0c 90 01 00 00 0c a0 0f 00 00 0c 0a 00 00 00 0c ................ + 02b0: 0a 00 00 00 11 07 0a 04 06 04 00 00 11 07 0a 04 ................ + 02c0: 00 00 00 00 11 07 0a 04 00 00 00 00 11 07 0a 04 ................ + 02d0: 06 04 00 00 12 36 08 0c 90 01 00 00 0c a0 0f 00 .....6.......... + 02e0: 00 0c 0a 00 00 00 0c 0a 00 00 00 11 07 0a 04 06 ................ + 02f0: 04 00 00 11 07 0a 04 00 00 00 00 11 07 0a 04 00 ................ + 0300: 00 00 00 11 07 0a 04 06 04 00 00 12 36 08 0c 90 ............6... + 0310: 01 00 00 0c a0 0f 00 00 0c 0a 00 00 00 0c 0a 00 ................ + 0320: 00 00 11 07 0a 04 06 04 00 00 11 07 0a 04 00 00 ................ + 0330: 00 00 11 07 0a 04 00 00 00 00 11 07 0a 04 06 04 ................ + 0340: 00 00 08 50 50 53 31 12 43 0a 02 12 13 06 0b e8 ...PPS1.C....... + 0350: 03 0b 10 27 0b 0a 00 0a 0a 0b 06 0a 0b 06 0a 12 ...'............ + 0360: 13 06 0b 90 01 0b a0 0f 0b 0a 00 0a 0a 0b 06 04 ................ + 0370: 0b 06 04 12 13 06 0b 90 01 0b a0 0f 0b 0a 00 0a ................ + 0380: 0a 0b 06 04 0b 06 04 12 13 06 0b 90 01 0b a0 0f ................ + 0390: 0b 0a 00 0a 0a 0b 06 04 0b 06 04 12 13 06 0b 90 ................ + 03a0: 01 0b a0 0f 0b 0a 00 0a 0a 0b 06 04 0b 06 04 12 ................ + 03b0: 13 06 0b 90 01 0b a0 0f 0b 0a 00 0a 0a 0b 06 04 ................ + 03c0: 0b 06 04 12 13 06 0b 90 01 0b a0 0f 0b 0a 00 0a ................ + 03d0: 0a 0b 06 04 0b 06 04 12 13 06 0b 90 01 0b a0 0f ................ + 03e0: 0b 0a 00 0a 0a 0b 06 04 0b 06 04 08 50 50 53 32 ............PPS2 + 03f0: 12 43 0a 02 12 13 06 0b e8 03 0b 10 27 0b 26 02 .C..........'.&. + 0400: 0a 0a 0b b0 00 0b b0 00 12 13 06 0b 90 01 0b a0 ................ + 0410: 0f 0b bc 02 0a 0a 0b b1 00 0b b1 00 12 13 06 0b ................ + 0420: 90 01 0b a0 0f 0b bc 02 0a 0a 0b b2 00 0b b2 00 ................ + 0430: 12 13 06 0b 90 01 0b a0 0f 0b bc 02 0a 0a 0b b3 ................ + 0440: 00 0b b3 00 12 13 06 0b 90 01 0b a0 0f 0b bc 02 ................ + 0450: 0a 0a 0b b4 00 0b b4 00 12 13 06 0b 90 01 0b a0 ................ + 0460: 0f 0b bc 02 0a 0a 0b b5 00 0b b5 00 12 13 06 0b ................ + 0470: 90 01 0b a0 0f 0b bc 02 0a 0a 0b b6 00 0b b6 00 ................ + 0480: 12 13 06 0b 90 01 0b a0 0f 0b bc 02 0a 0a 0b b7 ................ + 0490: 00 0b b7 00 14 1b 5f 50 53 53 00 a0 0d 93 50 44 ......_PSS....PD + 04a0: 43 54 0a 00 a4 50 50 53 32 a1 06 a4 50 50 53 31 CT...PPS2...PPS1 + 04b0: 14 09 5f 50 50 43 00 a4 0a 00 .._PPC.... +[then] +
Added: cpu/x86/pc/olpc/via/dsdt.dsl =================================================================== --- cpu/x86/pc/olpc/via/dsdt.dsl (rev 0) +++ cpu/x86/pc/olpc/via/dsdt.dsl 2009-06-25 21:13:27 UTC (rev 1222) @@ -0,0 +1,2449 @@ +DefinitionBlock ("dsdt.aml", // AML file name + "DSDT", // Table signature, DSDT + 0x01, // Compliance Revision + "OLPC", // OEM ID + "XO-1.5 ", // Table ID + 0x00000001) // OEM Revision +{ + +OperationRegion(CMS1, SystemIO, 0x74, 0x2) +Field(CMS1, ByteAcc, NoLock, Preserve) { + CMSI, 8, + CMSD, 8 +} + +Method (CMSW, 2) +{ + Store (Arg0, CMSI) + Store (Arg1, CMSD) +} + // Processor Objects + Scope(_PR) { + Processor(_PR.CPU0,0x00,0x00000410,0x06){} + } + + // System Sleep States + Name(_S0,Package(){0,0,0,0}) + Name(_S1,Package(){4,4,4,4}) + Name(_S3,Package(){1,1,1,1}) + Name(_S4,Package(){2,2,2,2}) + Name(_S5,Package(){2,2,2,2}) + + OperationRegion(\DEBG, SystemIO, 0x80, 0x1) + Field(\DEBG, ByteAcc, NoLock, Preserve) { + DBG1, 8, + } + + OperationRegion(\GPST, SystemIO, 0x0420, 0x2) + Field(\GPST, ByteAcc, NoLock, Preserve) { + GS00,1, + GS01,1, + GS02,1, + GS03,1, + GS04,1, + GS05,1, + GS06,1, + GS07,1, + GS08,1, + GS09,1, + GS10,1, + GS11,1, + GS12,1, + GS13,1, + GS14,1, + GS15,1, + } + + OperationRegion(\GPSE, SystemIO, 0x0424, 0x2) // Genernal Purpose SMI Enable + Field(\GPSE, ByteAcc, NoLock, Preserve) { + GPS0, 1, // GPI0 SMI Enable + GPS1, 1, // GPI1 SMI Enable + KBCE, 1, // PS2 KB PME Enable + , 1, + EXTE, 1, // EXT SMI Enable + PME, 1, // PCI PME Enable + , 2, + RING, 1, // Ring Wakeup + , 5, + USBE, 1, // USB Resume + , 1, + } + + OperationRegion(\Glos, SystemIO, 0x0428, 0x2) // Global Status + Field(\Glos, ByteAcc, NoLock, Preserve) { + , 6, // + SSMI, 1, // software SMI + PRII, 1, // primary IRQ + , 2, // + SLPE, 1, // sleep enable(Rx05) + SIRS, 1, // serirq status + , 4, + } + + OperationRegion(\WIRQ, SystemIO, 0x042a, 0x1) // IRQ Resume Reg + Field(\WIRQ, ByteAcc, NoLock, Preserve) { + IRQR, 8, + } + + OperationRegion(\Stus, SystemIO, 0x0430, 0x1) // Global Status + Field(\Stus, ByteAcc, NoLock, Preserve) { + PADS, 8, + } + + OperationRegion(\Prie, SystemIO, 0x0434, 0x1) + Field(\Prie, ByteAcc, NoLock, Preserve) { + , 5, + CMAE, 1, // COMA_EN + CMBE, 1, // COMB_EN + } + + // + // General Purpose Event + // + Scope(_GPE) + { + Method(_L02) { + Notify(_SB.PCI0.VT86.PS2K, 0x02) //Internal Keyboard PME Status + } + + Method(_L04) { + Notify(_SB.SLPB, 0x80) + } + + Method(_L05) { + Notify(_SB.PCI0,0x2) + } + + Method(_L08) { + Notify(_SB.PCI0.VT86.EUR1, 0x2) + Notify(_SB.PCI0.VT86.EUR2, 0x2) + } + + Method(_L09) { + Notify(_SB.PCI0.VT86.PS2M, 0x02) //Internal Mouse Controller PME Status + } + + Method(_L0D) { + Notify(_SB.PCI0.HDAC, 0x02) + } + + Method(_L0E) { //USB Wake up Status + Notify(_SB.PCI0.USB1, 0x02) + Notify(_SB.PCI0.USB2, 0x02) + Notify(_SB.PCI0.USB3, 0x02) + Notify(_SB.PCI0.EHCI, 0x02) + } + } + + Name(PICF,0x00) // PIC or APIC? + Method(_PIC, 0x01, NotSerialized) { + Store (Arg0, PICF) + } + + // + // System Wake up + // + Method(_WAK, 1, Serialized) + { + Notify(_SB.PCI0.USB1, 0x00) + Notify(_SB.PCI0.USB2, 0x00) + Notify(_SB.PCI0.USB3, 0x00) + Notify(_SB.PCI0.EHCI, 0x00) + + If (LEqual (Arg0, 1)) //S1 + { + Notify (_SB.SLPB, 0x02) + } + + Or (Arg0, 0xA0, Local0) + Store (Local0, DBG1) //80 Port: A1, A2, A3.... + + IF (LEqual(Arg0, 0x01)) { //S1 + And(IRQR,0x7F,IRQR) //Disable IRQ Resume Reg, IRQR:Rx2A + While(PRII){ //PRII:Rx28[7] + Store (One, PRII) //Clear Primary IRQ resume Status + } + While(LNotEqual(PADS, 0x00)){ //PADS: Rx30[1:7] + Store (PADS, PADS) //Clear Primary Activity Detect Status + } + } + + Notify(_SB.SLPB, 0x2) + + IF (LEqual(Arg0, 0x03)) //S3 + { + Store(0x2,_SB.PCI0.MEMC.FSEG) //Set F Segment to Read only + } + + Or (Arg0, 0xB0, Local0) + Store (Local0, DBG1) //80 Port: B1, B2, B3.... + Return (0) + } + + // + // System sleep down + // + Method (_PTS, 1, NotSerialized) + { + + Or (Arg0, 0xF0, Local0) + Store (Local0, DBG1) //80 Port: F1, F2, F3.... + + IF (LEqual(Arg0, 0x01)) { // S1 + While(PRII) + { + Store (One, PRII) //Clear Primary IRQ resume Status + } + While(LNotEqual(PADS, 0x00)) + { + Store (PADS, PADS) //Clear Primary Activity Detect Status + } + Or(IRQR,0x80,IRQR) //Enable IRQ Resume Reg + + } //End of Arg0 EQ 0x01 + + IF (LEqual(Arg0, 0x03)) { //S3 + Store(0x0,_SB.PCI0.MEMC.FSEG) //Disable F Segment Read/Write + } + + IF (LEqual(Arg0, 0x04)) { //S4 + } + + IF (LEqual(Arg0, 0x05)) { //S5 + Store (Zero, GS04) // Clear EXTSMI# Status, why? + } + sleep(0x64) + Return (0x00) + } + + + Method(STRC, 2) { // Compare two String + If(LNotEqual(Sizeof(Arg0), Sizeof(Arg1))) { + Return(1) + } + + Add(Sizeof(Arg0), 1, Local0) + + Name(BUF0, Buffer(Local0) {}) + Name(BUF1, Buffer(Local0) {}) + + Store(Arg0, BUF0) + Store(Arg1, BUF1) + + While(Local0) { + Decrement(Local0) + If(LNotEqual(Derefof(Index(BUF0, Local0)), Derefof(Index(BUF1, Local0)))) { + Return(1) + } + } + Return(0) // Str1 & Str2 are match + } + + + // + // System Bus + // + Scope(_SB) + { + + // define Sleeping button as mentioned in ACPI spec 2.0 + Device (SLPB) + { + Name (_HID, EISAID("PNP0C0E")) // Hardware Device ID SLEEPBTN + Method(_STA, 0) { + Return(0x0B) // non-present, enabled, functioning + } + + Name(_PRW, Package(2){0x04,5}) //Internal Keyboard Controller PME Status; S5 + } + +Device(PCI0) +{ + Name(_HID,EISAID ("PNP0A08")) // Indicates PCI Express host bridge hierarchy + Name(_CID,EISAID ("PNP0A03")) // For legacy OS that doesn't understand the new HID + + Name(_ADR,0x00000000) // Device (HI WORD)=0, Func (LO WORD)=0 + + + Name (_BBN,0) + + Method(_INI, 0) + { + } + + Name (_S3D, 3) + + Method(_STA, 0) { + Return(0x0F) // present, enabled, functioning + } + + Name(_PRW, Package(2){0x5,0x4}) // PME# + + Method(_CRS,0) { + Name(BUF0,ResourceTemplate() { + WORDBusNumber( // Bus 0 + ResourceConsumer, + MinNotFixed, + MaxNotFixed, + PosDecode, + 0x0000, + 0x0000, + 0x00FF, + 0x0000, + 0x0100 + ) + + IO( // IO Resource for PCI Bus + Decode16, + 0x0CF8, + 0x0CF8, + 1, + 8 + ) + + WORDIO( // IO from 0x0000 - 0x0cf7 + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0000, + 0x0000, + 0x0CF7, + 0x0000, + 0x0CF8 + ) + + WORDIO( // IO from 0x0d00 - 0xffff + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x0000, + 0x0D00, + 0xFFFF, + 0x0000, + 0xF300 + ) + + DWORDMemory( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, + 0x000A0000, + 0x000BFFFF, + 0x00000000, + 0x00020000 + ) + + DWORDMemory( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, + 0x000C0000, + 0x000DFFFF, + 0x00000000, + 0x00020000 + ) +// XXX I don't know what this is + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, + 0xFED40000, + 0xFED44FFF, + 0x00000000, + 0x00005000, + ) + DWORDMemory( // Consumed-and-produced resource(all of memory space) + ResourceProducer, // bit 0 of general flags is 0 + PosDecode, // positive Decode + MinFixed, // Range is fixed + MaxFixed, // Range is fixed + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x80000000, // Min (calculated dynamically) + 0xBfffffff, // Max = 4GB - 1MB (fwh + fwh alias...) + 0x00000000, // Translation + 0x40000000, // Range Length (calculated dynamically) + , // Optional field left blank + , // Optional field left blank + MEM3 // Name declaration for this descriptor + ) + }) // end of BUF0 + + CreateDWordField(BUF0,MEM3._MIN, PMRN) + CreateDWordField(BUF0,MEM3._MAX, PMRM) + CreateDWordField(BUF0,MEM3._LEN, PMRL) + \ XXX top of PCI memory space + Store(0xFFE80000, PMRM) + Store(_SB.PCI0.MEMC.LTMA, Local0) + ShiftLeft(Local0, 16, PMRN) + Subtract (PMRM, PMRN, PMRL) + + Return(BUF0) + } // end of CRS + + Device(MEMC) { + Name(_ADR, 0x00000003) + + Method(_STA, 0) { + Return(0x0F) // present, enabled, functioning + } + + OperationRegion(MCPS,PCI_Config,0x00,0x100) + Field(MCPS,ByteAcc,NoLock,Preserve) + { + Offset(0x83), + , 4, + FSEG, 2, //Rx83[4:5] + , 2, + Offset(0x84), + LTMA, 16, //Rx84 and Rx85. Low Top Address of Memory + Offset(0x86), + , 2, + ENTS, 1, //Enable Top SMRAM Size + , 3, + TSMS, 2, // Top SMRAM Size + Offset(0xA1), + , 4, + FBSZ, 3, // Frame Buffer Size + ENIG, 1, // Enable Internal Graphic + } + } + + // USBD Controller + Device (USBD) + { + Name(_ADR, 0x000B0000) + + OperationRegion(RUDC,PCI_Config,0x00,0x100) + Field(RUDC,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + } + + Method(_STA, 0) + { + If(LNotEqual(_SB.PCI0.USBD.VID, 0x1106)) { + Return(0x00) + }Else { + If(LEqual(_SB.PCI0.USBD.CMDR, 0x00)) { + Return(0x0D) + }Else{ + Return(0x0F) // present, enabled, functioning + } + } + } + }//Device(USBD) + + // SDIO Controller + Device (SDIO) + { + Name(_ADR, 0x000C0000) + + OperationRegion(RSDC,PCI_Config,0x00,0x100) + Field(RSDC,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + } + + Method(_STA, 0) + { + If(LNotEqual(_SB.PCI0.SDIO.VID, 0x1106)) { + Return(0x00) + }Else { + If(LEqual(_SB.PCI0.SDIO.CMDR, 0x00)) { + Return(0x0D) + }Else{ + Return(0x0F) // present, enabled, functioning + } + } + } + }//Device(SDIO) + + // SD $ MS Controller + Device (SDMS) + { + Name(_ADR, 0x000D0000) + + OperationRegion(RSDM,PCI_Config,0x00,0x100) + Field(RSDM,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + } + + Method(_STA, 0) + { + If(LNotEqual(_SB.PCI0.SDMS.VID, 0x1106)) { + Return(0x00) + }Else { + If(LEqual(_SB.PCI0.SDMS.CMDR, 0x00)) { + Return(0x0D) + }Else{ + Return(0x0F) // present, enabled, functioning + } + } + } + }//Device(SDMS) + + // CE-ATA $ NF Controller(Card Boot) + Device(CENF) + { + Name(_ADR, 0x000E0000) + + OperationRegion(RENF,PCI_Config,0x00,0x100) + Field(RENF,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + } + + Method(_STA, 0) + { + If(LNotEqual(_SB.PCI0.CENF.VID, 0x1106)) { + Return(0x00) + }Else { + If(LEqual(_SB.PCI0.CENF.CMDR, 0x00)) { + Return(0x0D) + }Else{ + Return(0x0F) // present, enabled, functioning + } + } + } + } + +Device(IDEC) +{ + + Name(_ADR, 0x000F0000) //D15F0: a Pata device + + Method(_STA,0,NotSerialized) //Status of the Pata Device + { + If(LNot(LEqual(_SB.PCI0.IDEC.VID,0x1106))) + { + Return(0x00) //device not exists + } + Else + { + If(LEqual(_SB.PCI0.IDEC.CMDR,0x00)) + { + Return(0x0D) //device exists & disable + } + Else + { + Return(0x0F) //device exists & enable + } + } + } + OperationRegion(SAPR,PCI_Config,0x00,0xC2) + Field(SAPR,ByteAcc,NoLock,Preserve) + { + VID,16, + Offset(0x04), + CMDR,3, + Offset(0x40), + , 1, + EPCH, 1, // Enable Primary channel. + Offset(0x4A), + PSPT, 8, // IDE Timings, Primary Slave + PMPT, 8, // IDE Timings, Primary Master + Offset(0x52), + PSUT, 4, // Primary Slave UDMA Timing + PSCT, 1, // Primary Drive Slave Cabal Type + PSUE, 3, // Primary Slave UDMA Enable + PMUT, 4, // Primary Master UDMA Timing + PMCT, 1, // Primary Drive Master Cabal Type + PMUE, 3, // Primary Master UDMA Enable + } + + Name(REGF,0x01) //accessible OpRegion default + Method(_REG,2,NotSerialized) // is PCI Config space accessible as OpRegion? + { + If(LEqual(Arg0,0x02)) + { + Store(Arg1,REGF) + } + } + /* + Name(TIM0,Package(0x04){ + Package(){0x78,0xB4,0xF0,0x017F,0x0258}, + Package(){0x20,0x22,0x33,0x47,0x5D}, + Package(){0x78,0x50,0x3C,0x2D,0x1E,0x14,0x0F}, + Package(){0x06,0x05,0x04,0x04,0x03,0x03,0x02,0x02,0x01,0x01,0x01,0x01,0x01,0x01,0x00} + }) +*/ + Name(TIM0, Package() + { // Primary / Secondary channels timings + Package(){120, 180, 240, 383, 600}, // Timings in ns - Mode 4,3,2,1,0 defined from ATA spec. + Package(){0x20, 0x22, 0x33, 0x47, 0x5D }, // PIO Timing - Mode 4,3,2,1,0 + Package(){4, 3, 2, 1, 0}, // PIO mode (TIM0,0) + Package(){2, 1, 0, 0}, // Multi-word DMA mode + Package(){120, 80, 60, 45, 30, 20, 15}, // Min UDMA Timings in ns + Package(){6,5,4,4,3,3,2,2,1,1,1,1,1,1,0}, // UDMA mode + Package(){0x0E, 8, 6, 4, 2, 1, 0}, // UDMA timing + }) + + Name(TMD0,Buffer(0x14){}) + CreateDwordField(TMD0,0x00,PIO0) + CreateDwordField(TMD0,0x04,DMA0) + CreateDwordField(TMD0,0x08,PIO1) + CreateDwordField(TMD0,0x0C,DMA1) + CreateDwordField(TMD0,0x10,CHNF) + + Name(GMPT, 0) // Master PIO Timings + Name(GMUE, 0) // Master UDMA enable + Name(GMUT, 0) // Master UDMA Timings + Name(GSPT, 0) // Slave PIO Timings + Name(GSUE, 0) // Slave UDMA enable + Name(GSUT, 0) // Slave UDMA Timings + + Device(CHN0) //Primary Channel: Pata device + { + Name(_ADR,0x00) + + Method(_STA,0,NotSerialized) + { + If(LNotEqual(_SB.PCI0.IDEC.EPCH, 0x1)) + { + Return(0x00) //channel disable + } + Else + { + Return(0x0F) //channel enable + } + } + Method(_GTM,0,NotSerialized) //Get Timing Mode + { + Return(GTM(PMPT,PMUE,PMUT,PSPT,PSUE,PSUT)) + } + Method(_STM, 3) // Set Timing PIO/DMA Mode + { + Store(Arg0, TMD0) // Copy Arg0 into TMD0 buffer + Store(PMPT, GMPT) // Master PIO Timings + Store(PMUE, GMUE) // Master UDMA enable + Store(PMUT, GMUT) // Master UDMA Timings + Store(PSPT, GSPT) // Slave PIO Timings + Store(PSUE, GSUE) // Slave UDMA enable + Store(PSUT, GSUT) // Slave UDMA Timings + STM() + Store(GMPT, PMPT) // Master PIO Timings + Store(GMUE, PMUE) // Master UDMA enable + Store(GMUT, PMUT) // Master UDMA Timings + Store(GSPT, PSPT) // Slave PIO Timings + Store(GSUE, PSUE) // Slave UDMA enable + Store(GSUT, PSUT) // Slave UDMA Timings + } // end Method _STM + + Device(DRV0) //Master Device + { + Name(_ADR,0x00) //0 indicates master drive + Method(_GTF,0,NotSerialized) //Get Task File: return a buffer of ATA command used to re-initialize the device + { + Return(GTF(0,PMUE,PMUT,PMPT)) + } + } + Device(DRV1) //Slave Device + { + Name(_ADR,0x01) //1 indicates slave drive + Method(_GTF,0,NotSerialized) //Get Task File: return a buffer of ATA command used to re-initialize the device + { + Return(GTF(0,PSUE,PSUT,PSPT)) + } + } + } + + Method(GTM,6,Serialized) + { + Store(Ones,PIO0) //default value: all bits set to 1 + Store(Ones,PIO1) //default value: all bits set to 1 + Store(Ones,DMA0) //default value: all bits set to 1 + Store(Ones,DMA1) //default value: all bits set to 1 + Store(0x10,CHNF) //default value: 0x10 + If(REGF) + { + } + Else + { + Return(TMD0) //unable to setup PCI config space as opRegion;return default value + } + Store(Match(DeRefOf(Index(TIM0,0x01)),MEQ,Arg0,MTR,0x00,0x00),Local6) + If(LLess(Local6,Ones)) + { + Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x00)),Local6)),Local7) + Store(Local7,DMA0) + Store(Local7,PIO0) + } + Store(Match(DeRefOf(Index(TIM0,0x01)),MEQ,Arg3,MTR,0x00,0x00),Local6) + If(LLess(Local6,Ones)) + { + Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x00)),Local6)),Local7) + Store(Local7,DMA1) + Store(Local7,PIO1) + } + If(Arg1) + { + Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x05)),Arg2)),Local5) + Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x04)),Local5)),DMA0) + Or(CHNF,0x01,CHNF) + } + If(Arg4) + { + Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x05)),Arg5)),Local5) + Store(DeRefOf(Index(DeRefOf(Index(TIM0,0x04)),Local5)),DMA1) + Or(CHNF,0x04,CHNF) + } + Return(TMD0) //return timing mode + } + + + Method(STM, 0, Serialized) + { + + If(REGF){} // PCI space not accessible + Else { Return(TMD0) } + + Store(0x00, GMUE) // Master UDMA Disable + Store(0x00, GSUE) // Slave UDMA Disable + Store(0x07, GMUT) // Master UDMA Mode 0 + Store(0x07, GSUT) // Slave UDMA Mode 0 + + If(And(CHNF, 0x1)) + { + Store(Match(DeRefOf(Index(TIM0, 4)), MLE, DMA0, MTR,0,0), Local0) // Get DMA mode + Store(DeRefOf(Index(DeReFof(Index(TIM0, 6)), Local0)), GMUT) // Timing bit mask 66Mhz + Or(GMUE, 0x07, GMUE) // Enable UltraDMA for Device 0 + } + Else // non - UDMA mode. Possible Multi word DMA + { + If(Or(LEqual(PIO0,Ones), LEqual(PIO0,0))) + { + If(And(LLess(DMA0,Ones), LGreater(DMA0,0))) + { + Store(DMA0, PIO0) // Make PIO0=DMA0 + } + } + } + + If(And(CHNF, 0x4)) + { + Store(Match(DeRefOf(Index(TIM0, 4)), MLE, DMA1, MTR,0,0), Local0) + Store(DeRefOf(Index(DeReFof(Index(TIM0, 6)), Local0)), GSUT) // Timing bit mask 66Mhz + Or(GSUE, 0x07, GSUE) // Enable UltraDMA for Device 0 + } + Else // non - UDMA mode. Possible Multi word DMA + { + If(Or(LEqual(PIO1, Ones), LEqual(PIO1,0))) + { + If(And(LLess(DMA1, Ones), LGreater(DMA1,0))) + { + Store(DMA1, PIO1) // Make PIO1 = DMA1 + } + } + } + + And(Match(DeRefOf(Index(TIM0, 0)), MGE, PIO0, MTR,0,0), 0x3, Local0) + Store(DeRefOf(Index(DeReFof(Index(TIM0, 1)), Local0)), Local1) + Store(Local1, GMPT) + + And(Match(DeRefOf(Index(TIM0, 0)), MGE, PIO1, MTR,0,0), 0x3, Local0) + Store(DeRefOf(Index(DeReFof(Index(TIM0, 1)), Local0)), Local1) + Store(Local1, GSPT) + Return(TMD0) + } // end Method STM + + Method(GTF , 4 , Serialized) + { + Store(Buffer(7){0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF}, Local1) + Store(Buffer(7){0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF}, Local2) + CreateByteField(Local1, 1, Mode) // PIO mode + CreateByteField(Local2, 1, UMOD) // Ultra mode + CreateByteField(Local1, 5, PCHA) // master or slave + CreateByteField(Local2, 5, UCHA) // master or slave + And(Arg0,0x03,Local3) + + If(Lequal(And(Local3,0x01),0x01)) + { + Store(0xB0,PCHA) // drive 1 + Store(0xB0,UCHA) // drive 1 + } + + If(Arg1) + { + Store(DeRefOf(Index(DeReFof(Index(TIM0, 5)), Arg2)), UMOD) //Programming DMA Mode + Or( UMOD, 0x40, UMOD) + } + Else + { // non-UltraDMA + Store(Match(DeRefOf(Index(TIM0, 1)), MEQ, Arg3, MTR,0,0), Local0) + Or(0x20, DeRefOf(Index(DeReFof(Index(TIM0, 3)), Local0)), UMOD) + } + + Store(Match(DeRefOf(Index(TIM0, 1)), MEQ, Arg3, MTR,0,0), Local0) + Or(0x08, DeRefOf(Index(DeReFof(Index(TIM0, 2)), Local0)), Mode) + Concatenate(Local1, Local2, Local6) + Return(Local6) + + } // end of GTF +} + +//---------------------------------------------------------------- +// +// Copyright (c) 2005-2012 VIA Technologies, Inc. +// This program contains proprietary and confidential information. +// All rights reserved except as may be permitted by prior written +// consent. +// +//---------------------------------------------------------------- +//Rev Date Name Description +//---------------------------------------------------------------- + +Device(USB1) { + Name(_ADR,0x00100000) //Address+function. + + Name(_PRW, Package(2){0x0E,3}) + + Name(_S3D, 3) + + OperationRegion(U2F0,PCI_Config,0x00,0xC2) + Field(U2F0,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x3c), + U3IR, 4, //USB1 Interrupt Line + Offset(0x84), + ECDX, 2 //USB1 PM capability status register + } + + Method(_STA,0) { //Status of the USB1 Device + If(LEqual(_SB.PCI0.USB1.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) + } + } +} + +Device(USB2) { + Name(_ADR,0x00100001) //Address+function. + + Name(_PRW, Package(2){0x0E,3}) + + Name(_S3D, 3) + + OperationRegion(U2F1,PCI_Config,0x00,0xC2) + Field(U2F1,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x3c), + U4IR, 4, //USB2 Interrupt Line + Offset(0x84), + ECDX, 2 //USB2 PM capability status register + } + + Method(_STA,0) { //Status of the USB2 Device + If(LEqual(_SB.PCI0.USB2.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) + } + } +} + +Device(USB3){ + Name(_ADR,0x00100002) //Address+function. + + Name(_PRW, Package(2){0x0E,3}) + + Name(_S3D, 3) + + OperationRegion(U2F2,PCI_Config,0x00,0xC2) + Field(U2F2,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x3c), + U5IR, 4, //USB3 Interrupt Line + Offset(0x84), + ECDX, 2 //USB3 PM capability status register + } + + Method(_STA,0) { //Status of the USB3 Device + If(LEqual(_SB.PCI0.USB3.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) + } + } +} + + +Device(EHCI) { + Name(_ADR,0x00100004) //Address+function. + + Name(_PRW, Package(2){0x0E,3}) + + Name(_S3D, 3) + + OperationRegion(U2F4,PCI_Config,0x00,0xC2) + Field(U2F4,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x3c), + U7IR, 4, //EHCI1 Interrupt Line + Offset(0x84), + ECDX, 2 //EHCI1 PM capability status register + } + + Method(_STA,0) { //Status of the EHCI1 Device + If(LEqual(_SB.PCI0.EHCI.CMDR, 0x00)) { + Return(0x0D) + } Else { + Return(0x0F) + } + } +} + + Device (PEXX) + { + Name (_HID, EISAID ("PNP0C01")) + Method (_STA, 0) + { + Return (0x0F) + } + Name (PXXE, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xE0000000, + 0x10000000, + ) + }) + Method (_CRS, 0) + { + + Return (PXXE) + } + } + +//---------------------------------------------------------------- +// +// Copyright (c) 2005-2012 VIA Technologies, Inc. +// This program contains proprietary and confidential information. +// All rights reserved except as may be permitted by prior written +// consent. +// +//---------------------------------------------------------------- +//Rev Date Name Description +//---------------------------------------------------------------- + + + + + +Device(VT86) { + Name(_ADR,0x00110000) //Address+function. + + + OperationRegion(VTSB, PCI_Config, 0x00, 0x100) + Field(_SB.PCI0.VT86.VTSB,ByteAcc,NoLock,Preserve) { + Offset(0x2), + DEID, 16, // Device ID + Offset(0x2C), + ID2C,8, // RX2C + ID2D,8, // RX2D + ID2E,8, // RX2E + ID2F,8, // RX2F + Offset(0x44), + PIRE, 4, + PIRF, 4, + PIRG, 4, + PIRH, 4, // PIRQH# Routing + Offset(0x46), + POLE, 1, // INTE polarity + POLF, 1, // INTF polarity + POLG, 1, // INTG polarity + POLH, 1, // INTH polarity + ENR8, 1, // enable INTE~H routing by Rx44~Rx45. + , 1, + ECOM, 1, + Offset(0x4E), + , 3, + EP74, 1, // Enable 74/75 Access CMOS + , 4, + Offset(0x50), + , 1, + ESB3, 1, // RX5001 EHCI1 + ESB2, 1, // RX5002 USB3 + EIDE, 1, // RX5003 EIDE + EUSB, 1, // RX5004 USB1 + ESB1, 1, // RX5005 USB2 + USBD, 1, // RX5006 USB Device Mode controller + Offset(0x51), + EKBC, 1, // RX5100 Internal Keyboard controller + KBCC, 1, // RX5101 Internal KBC Configuration + EPS2, 1, // RX5102 Internal PS2 Mouse + ERTC, 1, // RX5103 Internal RTC + SDIO, 1, // RX5104 enable SDIO controller + , 2, + Offset(0x55), + , 4, + PIRA, 4, // PCI IRQA + PIRB, 4, // PCI IRQB + PIRC, 4, // PCI IRQC + , 4, + PIRD, 4, // PCI IRQD + + Offset(0x58), + , 6, + ESIA, 1, // Enable Source Bridge IO APIC + , 1, + + Offset(0x81), // Enable ACPI I/O + , 7, + ENIO, 1, + Offset(0x88), + , 7, + IOBA, 9, //Power Management I/O Base + + Offset(0x94), + , 5, + PLLD, 1, // RX9405 Internal PLL Reset During Suspend 0:Enable,1:Disable + + Offset(0xB0), + , 4, + EU1E, 1, //Embedded COM1 + EU2E, 1, //Embedded COM2 + , 2, + Offset(0xB2), + UIQ1, 4, // UART1 IRQ + UIQ2, 4, // UART2 IRQ + Offset(0xB4), + U1BA, 7, // UART1 I/O base address. + , 1, + U2BA, 7, // UART2 I/O base address. + , 1, + Offset(0xB7), + , 3, + UDFE, 1, // UART DMA Funtion Enable + Offset(0xB8), + , 2, + DIBA, 14, // UART DMA I/O Base Address + + Offset(0xBC), + SPIB, 24, + Offset(0xD0), + , 4, + SMBA, 12, //SMBus I/O Base (16-byte I/O space) + Offset(0xD2), + ENSM, 1, //Enable SMBus IO + , 7, + Offset(0xF6), + REBD, 8, //Internal Revision ID + } + + Device(APCM) // APIC MMIO + { + Name(_HID, EISAID("PNP0C02")) // Hardware Device ID, Motherboard Resources + Name(_UID, 0x1100) + + Name(CRS, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0xFEE00000, 0x00001000, LAPM) // Local APIC MMIO Space + Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, SIAM) // Sourth Bridge IO APIC MMIO Space + }) + + Method(_CRS, 0) + { + CreateDWordField(CRS, ^SIAM._BAS, BAS1) + CreateDWordField(CRS, ^SIAM._LEN, LEN1) + + + If(LEqual(_SB.PCI0.VT86.ESIA, 1)) + { + Store(0xFEC00000, BAS1) + Store(0x1000, LEN1) + } + + Return(CRS) + } + + } + + +//---------------------------------------------------------------- +// +// Copyright (c) 2005-2012 VIA Technologies, Inc. +// This program contains proprietary and confidential information. +// All rights reserved except as may be permitted by prior written +// consent. +// +//---------------------------------------------------------------- +//Rev Date Name Description +//---------------------------------------------------------------- + + + + + + + +//---------------------------------------------------------------- +// +// Copyright (c) 2005-2012 VIA Technologies, Inc. +// This program contains proprietary and confidential information. +// All rights reserved except as may be permitted by prior written +// consent. +// +//---------------------------------------------------------------- +//Rev Date Name Description +//---------------------------------------------------------------- + + +Device(PS2M) //PS2 Mouse Device +{ + Name(_HID,EISAID("PNP0F13")) // Hardware Device ID + + Method(_STA,0) //Status of the PS2 Mouse device + { + Return(0x0F) + } + + Method(_CRS,0) + { // Current Resource + Name (BUF1, ResourceTemplate () + { + IRQNoFlags () + {12} + }) + Return(BUF1) + } + + Name(_PRW, Package(){0x09, 0x04}) +} + +Device(PS2K) // PS2 Keyboard Device +{ + Name(_HID,EISAID("PNP0303")) // Hardware Device ID + Name(_CID,EISAID("PNP030B")) // PNP030B is Microsoft reserved + + Method(_STA,0) //Status of the PS2 Keyboard device + { + Return(0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0060, // Address Range Minimum + 0x0060, // Address Range Maximum + 0x01, // Address Alignment + 0x01, // Address Length + ) + IO (Decode16, + 0x0064, // Address Range Minimum + 0x0064, // Address Range Maximum + 0x01, // Address Alignment + 0x01, // Address Length + ) + IRQNoFlags () + {1} + }) + Name(_PRW, Package(){0x02, 0x04}) +} + + +Device(DMAC) +{ + Name(_HID, EISAID("PNP0200")) + + Name(_CRS,ResourceTemplate() { + IO(Decode16, 0x0, 0x0, 0, 0x10) // Master DMA Controller + IO(Decode16, 0x81, 0x81, 0, 0x3) // DMA Page Registers + IO(Decode16, 0x87, 0x87, 0, 0x1) + IO(Decode16, 0x89, 0x89, 0, 0x3) + IO(Decode16, 0x8F, 0x8F, 0, 0x1) + IO(Decode16, 0xC0, 0xC0, 0, 0x20) // Slave DMA Controller + DMA(Compatibility,NotBusMaster,Transfer8) {4} // Channel 4 is used to cascade the two DMA controller. + }) +} + +Device(RTC) +{ + Name(_HID,EISAID("PNP0B00")) + + Name(BUF0,ResourceTemplate() + { + IO(Decode16, 0x70, 0x70, 0x00, 0x02) + IO(Decode16, 0x74, 0x74, 0x00, 0x00, AAAA) + IRQNoFlags() {8} // Active High, Edge Sensitive, Non-sharable + }) + + Method(_CRS,0,Serialized) + { + CreateByteField(BUF0, ^AAAA._LEN, LEN1) + If(LEqual(_SB.PCI0.VT86.EP74, 0x01)) + { + Store(0x02, LEN1) + } + Return(BUF0) + } +} + +Device(PIC) +{ + Name(_HID,EISAID("PNP0000")) + + Name(_CRS,ResourceTemplate() { + IO(Decode16,0x20,0x20,0x00,0x02) + IO(Decode16,0xA0,0xA0,0x00,0x02) + }) +} + +Device(FPU) +{ + Name(_HID,EISAID("PNP0C04")) + + Name(_CRS,ResourceTemplate() { + IO(Decode16,0xF0,0xF0,0x00,0x1) + IRQNoFlags(){13} + }) +} + +Device(TMR) +{ + Name(_HID,EISAID("PNP0100")) + + Name(BUF0, ResourceTemplate() + { + IO(Decode16,0x40,0x40,0x00,0x04) + IRQNoFlags() {0} + }) + + Method(_CRS, 0, Serialized) + { + Return(BUF0) + } +} + +Device(SPKR) // System Speaker +{ + Name(_HID,EISAID("PNP0800")) + + Name(_CRS,ResourceTemplate() { + IO(Decode16,0x61,0x61,0x01,0x01) + }) +} + + + + + +//---------------------------------------------------------------- +// +// Copyright (c) 2005-2012 VIA Technologies, Inc. +// This program contains proprietary and confidential information. +// All rights reserved except as may be permitted by prior written +// consent. +// +//---------------------------------------------------------------- +//Rev Date Name Description +//---------------------------------------------------------------- + + + + + + +Name (ICRS, ResourceTemplate () +{ + IRQ (Level, ActiveLow, Shared) // The flags is the value of Byte 3 of IRQ Description Definition + { } // The value decides the value of Byte 1 and byte 2 of IRQ Description Definition +}) + +Name(PRSA, ResourceTemplate() +{ + IRQ(Level, ActiveLow, Shared) + {3, 4, 5, 6, 7, 10, 11, 12, 14, 15} +}) +Alias(PRSA, PRSB) +Alias(PRSA, PRSC) +Alias(PRSA, PRSD) +Alias(PRSA, PRSE) +Alias(PRSA, PRSF) +Alias(PRSA, PRSG) +Alias(PRSA, PRSH) + +Device(LNKA) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 1) + Method(_STA, 0) + { + If(LEqual(_SB.PCI0.VT86.PIRA, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSA) + } + + Method(_DIS) + { + Store(0x0, _SB.PCI0.VT86.PIRA) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, _SB.PCI0.VT86.PIRA, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, _SB.PCI0.VT86.PIRA) + } +} + + +Device(LNKB) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 2) + Method(_STA, 0) + { + If(LEqual(_SB.PCI0.VT86.PIRB, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSB) + } + + Method(_DIS) + { + Store(0x0, _SB.PCI0.VT86.PIRB) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, _SB.PCI0.VT86.PIRB, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, _SB.PCI0.VT86.PIRB) + } +} + + +Device(LNKC) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 3) + Method(_STA, 0) + { + If(LEqual(_SB.PCI0.VT86.PIRC, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSC) + } + + Method(_DIS) + { + Store(0x0, _SB.PCI0.VT86.PIRC) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, _SB.PCI0.VT86.PIRC, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, _SB.PCI0.VT86.PIRC) + } +} + +Device(LNKD) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 4) + Method(_STA, 0) + { + If(LEqual(_SB.PCI0.VT86.PIRD, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSD) + } + + Method(_DIS) + { + Store(0x0, _SB.PCI0.VT86.PIRD) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, _SB.PCI0.VT86.PIRD, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, _SB.PCI0.VT86.PIRD) + } +} +Device(LNKE) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 5) + Method(_STA, 0) + { + If(LEqual(_SB.PCI0.VT86.PIRE, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSE) + } + + Method(_DIS) + { + Store(0x0, _SB.PCI0.VT86.PIRE) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, _SB.PCI0.VT86.PIRE, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, _SB.PCI0.VT86.PIRE) + Store(One,ENR8) + Store(Zero,POLE) + } +} +Device(LNKF) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 6) + Method(_STA, 0) + { + If(LEqual(_SB.PCI0.VT86.PIRF, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSF) + } + + Method(_DIS) + { + Store(0x0, _SB.PCI0.VT86.PIRF) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, _SB.PCI0.VT86.PIRF, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, _SB.PCI0.VT86.PIRF) + Store(One,ENR8) + Store(Zero,POLF) + } +} +Device(LNK0) { + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 7) + Method(_STA, 0) + { + If(LEqual(_SB.PCI0.VT86.PIRG, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSG) + } + + Method(_DIS) + { + Store(0x0, _SB.PCI0.VT86.PIRG) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, _SB.PCI0.VT86.PIRG, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, _SB.PCI0.VT86.PIRG) + Store(One,ENR8) + Store(Zero,POLG) + } +} +Device(LNK1) +{ + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link + Name(_UID, 8) + Method(_STA, 0) + { + If(LEqual(_SB.PCI0.VT86.PIRH, 0x00)) + { + Return(0x09) //disabled + }Else { + Return(0x0B) //enabled, but no UI + } + } + + Method(_PRS) + { + Return(PRSH) + } + + Method(_DIS) + { + Store(0x0, _SB.PCI0.VT86.PIRH) + } + + Method(_CRS) + { + CreateWordField (ICRS, 1, IRA0) + Store (1, Local1) + ShiftLeft (Local1, _SB.PCI0.VT86.PIRH, IRA0) + Return (ICRS) + } + + Method(_SRS, 1) { + CreateWordField (Arg0, 1, IRA) //Byte 1 and Byte 2 in the IRQ Descriptor Definition + FindSetRightBit (IRA, Local0) + Decrement (Local0) + Store (Local0, _SB.PCI0.VT86.PIRH) + Store(One,ENR8) + Store(Zero,POLH) + } +} + +// +// Embedded UART1 +// +Device(EUR1) // Communication Device (Modem Port) +{ + Name(_HID, EISAID("PNP0501")) // PnP Device ID 16550 Type + Name(_UID, 0x1) + + Name(_PRW, Package(){8, 4}) + + Method(_PSW, 1) + { + Store(0x20, PADS) // clear _STS first //PMIO Rx30[5] + And(IRQR,0xFE,IRQR) // don not issue SMI //PMIO Rx2A[0] + + If (Arg0) + { + Store(One, CMAE) + } + Else + { + Store(Zero, CMAE) + } + } + + Method(_STA) // Status of the COM device + { + Store(0x00, Local0) + + If(LNotEqual(_SB.PCI0.VT86.ECOM, Zero)) + { + If(_SB.PCI0.VT86.EU1E) + { + Store(0x0F, Local0) + } + Else + { // if base address is not equal to zero. + If(LNotEqual(_SB.PCI0.VT86.U1BA, Zero)) + { + Store(0x0D, Local0) + } + } + } + Return(Local0) + } + + Method(_DIS,0) + { + Store(Zero, _SB.PCI0.VT86.EU1E) // disable embedded COM A. + } + + Name(RSRC,ResourceTemplate (){ + IO(Decode16,0x0,0x0,0x08,0x08) + IRQNoFlags() {} + }) + + Method(_CRS, 0) + { + And(_STA(), 0x04, Local0) // If the device is disabled, return the blank template. + If(LEqual(Local0,Zero)) // + { // + Return(RSRC) // + } // + + Name(BUF1,ResourceTemplate() { // This is the buffer prepared for OS. + IO(Decode16,0x3F8,0x3F8,0x08,0x08) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQNoFlags(){4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + }) + + CreateByteField(BUF1, 0x02, IOLO) // IO Port MIN Low + CreateByteField(BUF1, 0x03, IOHI) // IO Port MIN High + CreateByteField(BUF1, 0x04, IORL) // IO Port MAX Low + CreateByteField(BUF1, 0x05, IORH) // IO Port MAX High + + if(LNotEqual(_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + CreateByteField(BUF1, 0x0A, DILO) // DMA IO Port MIN Low + CreateByteField(BUF1, 0x0B, DIHI) // DMA IO Port MIN High + CreateByteField(BUF1, 0x0C, DIRL) // DMA IO Port MAX Low + CreateByteField(BUF1, 0x0D, DIRH) // DMA IO Port MAX High + } + + CreateWordField(BUF1, 0x11, IRQV) // IRQ mask + + ShiftLeft(_SB.PCI0.VT86.U1BA, 0x03, local0) // IO low. AD7~AD0 + ShiftRight(_SB.PCI0.VT86.U1BA, 0x05, local1) // IO high. AD9~AD8 + + Store(local0, IOLO) + Store(local1, IOHI) + Store(local0, IORL) + Store(local1, IORH) + + Store(0x00, IRQV) // reset IRQ resource. + If(LNotEqual(_SB.PCI0.VT86.UIQ1, 0x00)) + { // put assigned IRQ to return buffer if there is any. + ShiftLeft(One, _SB.PCI0.VT86.UIQ1, IRQV) + } + + if(LNotEqual(_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + ShiftLeft(_SB.PCI0.VT86.DIBA, 0x02, local0) // IO low. AD7~AD0 + ShiftRight(_SB.PCI0.VT86.DIBA, 0x06, local1) // IO high. AD16~AD8 + + Store(local0, DILO) + Store(local1, DIHI) + Store(local0, DIRL) + Store(local1, DIRH) + } + Return(BUF1) + + } // _CRS + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,0) + { + IO(Decode16,0x3F8,0x3F8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFnNoPri() + { + IO(Decode16,0x2F8,0x2F8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFnNoPri() + { + IO(Decode16,0x3E8,0x3E8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFnNoPri() + { + IO(Decode16,0x2E8,0x2E8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFn(2,2) + { + IO(Decode16,0x3F8,0x3F8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFn(2,2) + { + IO(Decode16,0x2F8,0x2F8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFn(2,2) + { + IO(Decode16,0x3E8,0x3E8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + StartDependentFn(2,2) + { + IO(Decode16,0x2E8,0x2E8,0x1,0x8) + IO(Decode16,0x4080,0x4080,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x00} // DMA 0 + } + EndDependentFn() + })// _PRS + + Method(_SRS, 1) + { + // + // The Arg0 format is the same as _PRS, and _CRS. + // + CreateByteField (Arg0, 0x02, IOLO) // IO Port Low + CreateByteField (Arg0, 0x03, IOHI) // IO Port High + if(LNotEqual(_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + CreateByteField (Arg0, 0x0A, DILO) // DMA IO Port Low + CreateByteField (Arg0, 0x0B, DIHI) // DMA IO Port High + } + CreateWordField (Arg0, 0x11, IRQW) // IRQ + + Store(One, _SB.PCI0.VT86.EU1E) // enable embedded COM A. + + ShiftRight(IOLO, 0x03, local0) // set embedded COM A IO base. + ShiftLeft(IOHI, 0x05, local1) // + Or(local0, local1, _SB.PCI0.VT86.U1BA)// + + if(LNotEqual(_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + ShiftRight(DILO, 0x02, local0) // set embedded COM A DMA IO base. + ShiftLeft(DIHI, 0x06, local1) // + Or(local0, local1, _SB.PCI0.VT86.DIBA) // + } + + FindSetLeftBit(IRQW, Local0) // set embedded COM A IRQ. + If(LNotEqual(Local0, Zero)) // + { // + Subtract(Local0, 0x01, Local0) // IRQ is in a bit-mask fashion. + } // + // + Store(Local0, _SB.PCI0.VT86.UIQ1) + + }// _SRS + +}// embedded UART1. + +// +// Embedded UART2 +// +Device(EUR2) // Communication Device (Modem Port) +{ + Name(_HID, EISAID("PNP0501")) // PnP Device ID 16550 Type + Name(_UID, 0x2) + + Name(_PRW, Package(){8, 4}) + + Method(_PSW, 1) + { + Store(0x40, PADS) // clear _STS first //PMIO Rx30[6] + And(IRQR,0xFE,IRQR) // don not issue SMI //PMIO Rx2A[0]I + + If (Arg0) + { + Store(One, CMBE) + } + Else + { + Store(Zero, CMBE) + } + } + + // + // An empty resource. + // + Name(RSRC,ResourceTemplate (){ + IO(Decode16,0x0,0x0,0x08,0x08) + IRQNoFlags() {} + }) + + Method(_STA) // Status of the COM device + { + Store(0x00, Local0) + + If(LNotEqual(_SB.PCI0.VT86.ECOM, Zero)) + { + If(_SB.PCI0.VT86.EU2E) + { + Store(0x0F, Local0) + } + Else + { // if base address is not equal to zero. + If(LNotEqual(_SB.PCI0.VT86.U2BA, Zero)) + { + Store(0x0D, Local0) + } + } + } + Return(Local0) + } + + Method(_DIS,0) + { + Store(Zero, _SB.PCI0.VT86.EU2E) // disable embedded COM B. + } + + Method(_CRS, 0) + { + And(_STA(), 0x04, Local0) // If the device is disabled, return the blank template. + If(LEqual(Local0,Zero)) // + { // + Return(RSRC) // + } // + + Name(BUF1,ResourceTemplate() { // This is the buffer prepared for OS. + IO(Decode16,0x2F8,0x2F8,0x08,0x08) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQNoFlags(){3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + }) + + CreateByteField(BUF1, 0x02, IOLO) // IO Port MIN Low + CreateByteField(BUF1, 0x03, IOHI) // IO Port MIN High + CreateByteField(BUF1, 0x04, IORL) // IO Port MAX Low + CreateByteField(BUF1, 0x05, IORH) // IO Port MAX High + + if(LNotEqual(_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + CreateByteField(BUF1, 0x0A, DILO) // DMA IO Port MIN Low + CreateByteField(BUF1, 0x0B, DIHI) // DMA IO Port MIN High + CreateByteField(BUF1, 0x0C, DIRL) // DMA IO Port MAX Low + CreateByteField(BUF1, 0x0D, DIRH) // DMA IO Port MAX High + } + CreateWordField(BUF1, 0x11, IRQV) // IRQ mask + + ShiftLeft(_SB.PCI0.VT86.U2BA, 0x03, local0) // IO low. AD7~AD0 + ShiftRight(_SB.PCI0.VT86.U2BA, 0x05, local1) // IO high. AD9~AD8 + + Store(local0, IOLO) + Store(local1, IOHI) + Store(local0, IORL) + Store(local1, IORH) + + Store(0x00, IRQV) // reset IRQ resource. + If(LNotEqual(_SB.PCI0.VT86.UIQ2, 0x00)) + { // put assigned IRQ to return buffer if there is any. + ShiftLeft(One, _SB.PCI0.VT86.UIQ2, IRQV) + } + + if(LNotEqual(_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + ShiftLeft(_SB.PCI0.VT86.DIBA, 0x02, local0) // IO low. AD7~AD0 + ShiftRight(_SB.PCI0.VT86.DIBA, 0x06, local1) // IO high. AD16~AD8 + + Store(local0, DILO) + Store(local1, DIHI) + Store(local0, DIRL) + Store(local1, DIRH) + } + Return(BUF1) + + } // _CRS + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,0) + { + IO(Decode16,0x3F8,0x3F8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFnNoPri() + { + IO(Decode16,0x2F8,0x2F8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFnNoPri() + { + IO(Decode16,0x3E8,0x3E8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFnNoPri() + { + IO(Decode16,0x2E8,0x2E8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFn(2,2) + { + IO(Decode16,0x3F8,0x3F8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFn(2,2) + { + IO(Decode16,0x2F8,0x2F8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFn(2,2) + { + IO(Decode16,0x3E8,0x3E8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x3} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + StartDependentFn(2,2) + { + IO(Decode16,0x2E8,0x2E8,0x1,0x8) + IO(Decode16,0x4082,0x4082,0x02,0x02) + IRQ(Edge,ActiveHigh,Exclusive) {0x4} + DMA(Compatibility, NotBusMaster, Transfer8, ) {0x03} // + } + EndDependentFn() + })// _PRS + + Method(_SRS, 1) + { + // + // The Arg0 format is the same as _PRS, and _CRS. + // + CreateByteField (Arg0, 0x02, IOLO) // IO Port Low + CreateByteField (Arg0, 0x03, IOHI) // IO Port High + if(LNotEqual(_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + CreateByteField (Arg0, 0x0A, DILO) // DMA IO Port Low + CreateByteField (Arg0, 0x0B, DIHI) // DMA IO Port High + } + CreateWordField (Arg0, 0x11, IRQW) // IRQ + + Store(One, _SB.PCI0.VT86.EU2E) // enable embedded COM A. + + ShiftRight(IOLO, 0x03, local0) // set embedded COM A IO base. + ShiftLeft(IOHI, 0x05, local1) // + Or(local0, local1, _SB.PCI0.VT86.U2BA) // + + if(LNotEqual(_SB.PCI0.VT86.UDFE, 0x00)) // if enable DMA + { + ShiftRight(DILO, 0x02, local0) // set embedded COM A DMA IO base. + ShiftLeft(DIHI, 0x06, local1) // + Or(local0, local1, _SB.PCI0.VT86.DIBA) // + } + FindSetLeftBit(IRQW, Local0) // set embedded COM A IRQ. + If(LNotEqual(Local0, Zero)) // + { // + Subtract(Local0, 0x01, Local0) // IRQ is in a bit-mask fashion. + } // + // + Store(Local0, _SB.PCI0.VT86.UIQ2) + + }// _SRS + +}// embedded UART2. + + + + + Device(RMSC) // all "PNP0C02" devices- pieces that don't fit anywhere else + { + Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices + Name (_UID, 0x13) + + Name(CRS,ResourceTemplate(){ + + IO(Decode16,0x10,0x10,0x00,0x10) + IO(Decode16,0x22,0x22,0x00,0x1E) + IO(Decode16,0x44,0x44,0x00,0x1C) + IO(Decode16,0x62,0x62,0x00,0x02) + IO(Decode16,0x65,0x65,0x00,0x0B) + IO(Decode16,0x72,0x72,0x00,0x02) + IO(Decode16,0x76,0x76,0x00,0x09) + IO(Decode16,0x80,0x80,0x00,0x01) + IO(Decode16,0x84,0x84,0x00,0x03) + IO(Decode16,0x88,0x88,0x00,0x01) + IO(Decode16,0x8c,0x8c,0x00,0x03) + IO(Decode16,0x90,0x90,0x00,0x02) + IO(Decode16,0x92,0x92,0x00,0x01) // INIT & Fast A20 port + IO(Decode16,0x93,0x93,0x00,0x0C) + IO(Decode16,0xA2,0xA2,0x00,0x1E) + IO(Decode16,0xE0,0xE0,0x00,0x10) + IO(Decode16,0x3E0,0x3E0,0x00,0x8) + + // Reserve 4D0 and 4D1 for IRQ edge/level control port + IO(Decode16, 0x4D0,0x4D0,0x00,0x2) + // ACPI IO base address allocation + IO(Decode16, 0, 0, 0, 0, IO0) + // SMBus I/O space if applicable + IO(Decode16, 0, 0, 0, 0, IO1) + // SPI Memory Map IO Base + Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, MEM0) + }) + + Method(_CRS, 0){ + If(LEqual(_SB.PCI0.VT86.ENIO, 0x01)) // If we should privide the DSDT, ACPI IO must be enabled. + { + CreateWordField(CRS, ^IO0._MIN, MIN0) + CreateWordField(CRS, ^IO0._MAX, MAX0) + CreateByteField(CRS, ^IO0._LEN, LEN0) + Store(_SB.PCI0.VT86.IOBA, Local0) + ShiftLeft(Local0, 7, Local0) + Store(Local0, MIN0) + Store(Local0, MAX0) + Store(0x80, LEN0) + } + + If(LEqual(_SB.PCI0.VT86.ENSM, 0x01)) + { + CreateWordField(CRS, ^IO1._MIN, MIN1) + CreateWordField(CRS, ^IO1._MAX, MAX1) + CreateByteField(CRS, ^IO1._LEN, LEN1) + Store(_SB.PCI0.VT86.SMBA, Local0) + ShiftLeft(Local0, 4, Local0) + Store(Local0, MIN1) + Store(Local0, MAX1) + Store(0x10, LEN1) // Length: 16 Byte + } + + If(LNotEqual(_SB.PCI0.VT86.SPIB, 0x00)) + { + CreateDWordField(CRS, ^MEM0._BAS, BAS2) + CreateDWordField(CRS, ^MEM0._LEN, LEN2) + Store(_SB.PCI0.VT86.SPIB, Local0) + ShiftLeft(Local0, 8, Local0) + Store(Local0, BAS2) + Store(0x100, LEN2) + } + + Return(CRS) + } + } + + +} // End of VT86 + + + +//---------------------------------------------------------------- +// +// Copyright (c) 2005-2012 VIA Technologies, Inc. +// This program contains proprietary and confidential information. +// All rights reserved except as may be permitted by prior written +// consent. +// +//---------------------------------------------------------------- +//Rev Date Name Description +//---------------------------------------------------------------- + +Name(PICM, Package(){ + + // VIA VGA Device(Integrated Graphics Device) + Package(){0x0001ffff, 0, _SB.PCI0.VT86.LNKA, 0}, // VGA, INTA + + //PCI Slot 1 + Package(){0x0008ffff, 0, _SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTA + Package(){0x0008ffff, 1, _SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTB + Package(){0x0008ffff, 2, _SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTC + Package(){0x0008ffff, 3, _SB.PCI0.VT86.LNKA, 0}, // Slot 1, INTD + + //PCI Slot 2 + Package(){0x0009ffff, 0, _SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTA + Package(){0x0009ffff, 1, _SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTB + Package(){0x0009ffff, 2, _SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTC + Package(){0x0009ffff, 3, _SB.PCI0.VT86.LNKA, 0}, // Slot 2, INTD + + //PCI Slot 3 + Package(){0x000Affff, 0, _SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTA + Package(){0x000Affff, 1, _SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTB + Package(){0x000Affff, 2, _SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTC + Package(){0x000Affff, 3, _SB.PCI0.VT86.LNKA, 0}, // Slot 3, INTD + + // USB Device Controller + Package(){0x000Bffff, 0, _SB.PCI0.VT86.LNKA, 0}, + + // SDIO Controller + Package(){0x000cffff, 0, _SB.PCI0.VT86.LNKA, 0}, + // SD $ MS Controller + Package(){0x000dffff, 0, _SB.PCI0.VT86.LNKB, 0}, + // CE-ATA $ NF Controller(Card Boot) + Package(){0x000effff, 0, _SB.PCI0.VT86.LNKC, 0}, + // VIA VX800 IDE + Package(){0x000fffff, 0, _SB.PCI0.VT86.LNKB, 0}, + + // VIA UHCI USB1 Device + Package(){0x0010ffff, 0, _SB.PCI0.VT86.LNKA, 0}, + // VIA UHCI USB2 Device + Package(){0x0010ffff, 1, _SB.PCI0.VT86.LNKB, 0}, + // VIA UHCI USB3 Device + Package(){0x0010ffff, 2, _SB.PCI0.VT86.LNKC, 0}, + // VIA EHCI USB 2.0 Device + Package(){0x0010ffff, 3, _SB.PCI0.VT86.LNKD, 0}, + + // SB HDAC(Azalia) Audio + Package(){0x0014ffff, 0, _SB.PCI0.VT86.LNKA, 0}, // HD Audio, INTA + + }) + +Name(APIC, Package(){ + + // VIA VGA Device(Integrated Graphics Device) + Package(){0x0001ffff, 0, 0, 0x10}, + + //PCI Slot 1 + Package(){0x0008ffff, 0, 0, 0x10}, + Package(){0x0008ffff, 1, 0, 0x10}, + Package(){0x0008ffff, 2, 0, 0x10}, + Package(){0x0008ffff, 3, 0, 0x10}, + + //PCI Slot 2 + Package(){0x0009ffff, 0, 0, 0x10}, + Package(){0x0009ffff, 1, 0, 0x10}, + Package(){0x0009ffff, 2, 0, 0x10}, + Package(){0x0009ffff, 3, 0, 0x10}, + + //PCI Slot 3 + Package(){0x000Affff, 0, 0, 0x10}, + Package(){0x000Affff, 1, 0, 0x10}, + Package(){0x000Affff, 2, 0, 0x10}, + Package(){0x000Affff, 3, 0, 0x10}, + + // USB Device Controller + Package(){0x000Bffff, 0, 0, 0x13}, // USBD, INTA + + // SDIO Controller + Package(){0x000cffff, 0, 0, 0x16}, // SDIO, INTA + // SD $ MS Controller + Package(){0x000dffff, 0, 0, 0x17}, // Card Reader, INTA + // CE-ATA $ NF Controller(Card Boot) + Package(){0x000effff, 0, 0, 0x14}, // Card Boot(NAND Flash), INTA + // VIA VX800 IDE + Package(){0x000fffff, 0, 0, 0x15}, //IDE, INTA + + // VIA UHCI USB1 Device + Package(){0x0010ffff, 0, 0, 0x14}, + // VIA UHCI USB2 Device + Package(){0x0010ffff, 1, 0, 0x16}, + // VIA UHCI USB3 Device + Package(){0x0010ffff, 2, 0, 0x15}, + // VIA EHCI USB 2.0 Device + Package(){0x0010ffff, 3, 0, 0x17}, + + // SB HDAC(Azalia) Audio + Package(){0x0014ffff, 0, 0, 0x11}, //HD Audio , INTA + +}) // end of APIX + +Method(_PRT, 0, NotSerialized) +{ + If(LNot(PICF)) + { + //PIC + Return(PICM) + }Else{ + //APIC + Return(APIC) + } +} + + Device(P2PB) + { + Name (_ADR, 0x00130000) + + OperationRegion(RP2P,PCI_Config,0x00,0x100) + Field(RP2P,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + Offset(0x19), + BUS1, 8, + } + + Method(_BBN,0) + { + Return(BUS1) + } + + Method(_STA, 0) + { + If(LNotEqual(_SB.PCI0.P2PB.VID, 0x1106)) { + Return(0x00) + }Else { + If(LEqual(_SB.PCI0.P2PB.CMDR, 0x00)) { + Return(0x0D) + }Else{ + Return(0x0F) // present, enabled, functioning + } + } + } + + Name(PIC4, Package(){ + Package(){0x0003ffff, 0,_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0003ffff, 1,_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0003ffff, 2,_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0003ffff, 3,_SB.PCI0.VT86.LNKA , 0}, + + Package(){0x0004ffff, 0,_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0004ffff, 1,_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0004ffff, 2,_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0004ffff, 3,_SB.PCI0.VT86.LNKA , 0}, + + Package(){0x0005ffff, 0,_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0005ffff, 1,_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0005ffff, 2,_SB.PCI0.VT86.LNKA , 0}, + Package(){0x0005ffff, 3,_SB.PCI0.VT86.LNKA , 0}, + + }) + + Name(API4, Package(){ + Package(){0x0003ffff, 0, 0, 0x10}, + Package(){0x0003ffff, 1, 0, 0x10}, + Package(){0x0003ffff, 2, 0, 0x10}, + Package(){0x0003ffff, 3, 0, 0x10}, + + Package(){0x0004ffff, 0, 0, 0x10}, + Package(){0x0004ffff, 1, 0, 0x10}, + Package(){0x0004ffff, 2, 0, 0x10}, + Package(){0x0004ffff, 3, 0, 0x10}, + + Package(){0x0005ffff, 0, 0, 0x10}, + Package(){0x0005ffff, 1, 0, 0x10}, + Package(){0x0005ffff, 2, 0, 0x10}, + Package(){0x0005ffff, 3, 0, 0x10}, + + }) + + Method(_PRT, 0x0, NotSerialized) + { + If(LNot(PICF)) + { + Return(PIC4) + }Else { + Return(API4) + } + } + + Method(_PRW, 0x00, NotSerialized) + { + Return(Package(){0x05,4}) //PME# + } + Device(P4D3) + { + Name(_ADR, 0x00030000) + } + } // Device(P2PB) + + Device(HDAC) + { + Name(_ADR, 0x00140000) + + OperationRegion(RHDA,PCI_Config,0x00,0x100) + Field(RHDA,ByteAcc,NoLock,Preserve){ + Offset(0x00), + VID, 16, + Offset(0x04), + CMDR, 3, + } + + Method(_STA, 0) + { + If(LNotEqual(_SB.PCI0.HDAC.VID, 0x1106)) { + Return(0x00) + }Else { + If(LEqual(_SB.PCI0.HDAC.CMDR, 0x00)) { + Return(0x0D) + }Else{ + Return(0x0F) // present, enabled, functioning + } + } + } + + Method(_PRW) + { + Return (Package(){0xD, 4}) + } + }//Device(HDAC) + + +} // Device(PCI0) + +//----------------------------------------------------------------------- +// System board extension Device node for ACPI BIOS +//----------------------------------------------------------------------- +/* + +Procedure: RMEM + +Description: System board extension Device node for ACPI BIOS +Place the device under _SB scope, As per Msft the MEM +Device is used to reserve Resources that are decoded out of PCI Bus +Important consideration : +Logic to reserve the memory within 0xC0000 - 0xFFFFF Extended BIOS area is based on assumption, that +the BIOS Post has detected all expansion ROMs in the region and made their memory ranges +shadowable ( copied to RAM at the same address, for performance reasons). The rest of the region is left non-Shadowable, +hence no memory is decoded there. Such region is decoded to PCI bus (to be reserved in PCI0._CRS) +Whatever memory is Shadowed, thus, decoded as non "FF"s, is required to be reserved in "SYSM" System board extension Device node, +unless is not already reserved by some of PCI Device drivers. There have been observed the difference of how Win9x & Win2000 +OSes deal with Expansion ROM memory. Win9x Device drivers are tend to claim its expension ROMs regions as used +by the device; Win2000 never use such ROM regions for its devices. Therefore there can be different +approach used for different OSes in reservation unclaimed memory in "SYSM" Device node. +is forwarded to PCI Bus + +Input: Nothing + +Output: _CRS buffer + +**************************************************************************/ + +Device(RMEM) { + Name(_HID, EISAID("PNP0C01")) // Hardware Device ID, System Board + + Name(_UID, 1) + Name(CRS, ResourceTemplate() + { + // Base Address 0 - 0x9FFFF , 640k DOS memory + Memory32Fixed(ReadWrite,0x0000, 0xA0000 ) //Writeable + // Shadow RAM1, C0000 - E0000, 128k Expansion BIOS + Memory32Fixed(ReadOnly, 0x00000, 0x00000, RAM1) //Non-writeable + // Shadow RAM2, E0000 - 1M, 128k System BIOS + Memory32Fixed(ReadOnly, 0xE0000, 0x20000, RAM2) //Non-writeable + // Base Address 1M - Top of system present memory + Memory32Fixed(ReadWrite,0x100000,0x00000, RAM3) //Writeable + + }) + + Method (_CRS, 0) + { + CreateDWordField(CRS, ^RAM1._BAS, BAS1) + CreateDWordField(CRS, ^RAM1._LEN, LEN1) + CreateDWordField(CRS, ^RAM2._BAS, BAS2) + CreateDWordField(CRS, ^RAM2._LEN, LEN2) + CreateDWordField(CRS, ^RAM3._LEN, LEN3) + + //RAM3 + Store(_SB.PCI0.MEMC.LTMA, Local0) + ShiftLeft(Local0, 0x10, Local2) + Store(_SB.PCI0.MEMC.ENIG, Local1) + If(LEqual(Local1, 1)) // Check whether the Internal Graphic is enabled. + { + Add(_SB.PCI0.MEMC.FBSZ, 2, Local3) + ShiftLeft(1, Local3, Local4) + ShiftLeft(Local4, 0x14, Local4) + Subtract(Local2, Local4, Local2) // Subtract the Framebuffer Size + } + Store(_SB.PCI0.MEMC.ENTS, Local1) + If(LEqual(Local1, 1)) // Check Whether the Top SMRAM Segment is Enabled + { + ShiftLeft(1, _SB.PCI0.MEMC.TSMS, Local5) + ShiftLeft(Local5, 0x14, Local5) + Subtract(Local2, Local5, Local2) // Subtract Top SM RAM Size + } + Subtract(Local2, 0x100000, LEN3) + + Return(CRS) + } +} + + }//Scope(_SB) +}
Added: cpu/x86/pc/olpc/via/rtcwake.fth =================================================================== --- cpu/x86/pc/olpc/via/rtcwake.fth (rev 0) +++ cpu/x86/pc/olpc/via/rtcwake.fth 2009-06-25 21:13:27 UTC (rev 1222) @@ -0,0 +1,97 @@ +purpose: Suspend/resume test with RTC wakeup +\ See license at end of file + +h# 7d constant cmos-alarm-day \ Offset of day alarm in CMOS +h# 7e constant cmos-alarm-month \ Offset of month alarm in CMOS +h# 7f constant cmos-century \ Offset of century byte in CMOS + +dev /rtc + +cmos-alarm-day " alarm_day" integer-property +cmos-alarm-month " alarm_month" integer-property +cmos-century " century" integer-property + +\ There are a couple of reasons why you might not want to enable the IRQ: +\ a) It might be shared with the timer IRQ so it is already enabled +\ b) When using the alarm to wakeup from sleep, the IRQ might be unnecessary. + +0 value alarm-irq +false value enable-alarm-irq? + +defer alarm-hook ' noop to alarm-hook + +: disable-alarm ( -- ) + enable-alarm-irq? if alarm-irq disable-interrupt then + h# b cmos@ h# 20 invert and h# b cmos! +; + +: rtc-handler ( -- ) + disable-alarm + h# c cmos@ drop \ Clear RTC interrupt flags + alarm-hook +; + +: enable-alarm ( -- ) + ['] rtc-handler 8 interrupt-handler! + enable-alarm-irq? if alarm-irq disable-interrupt then + h# c cmos@ drop \ Clear RTC interrupt flags + h# b cmos@ h# 20 or h# b cmos! +; + +: set-alarm ( [ handler-xt ] secs -- ) \ No handler-xt if secs is 0 + disable-alarm + ?dup 0= if exit then ( handler-xt secs ) + swap to alarm-hook ( secs ) + now ( secs s m h ) + d# 60 * d# 60 * swap d# 60 * + + + ( s ) + d# 60 /mod d# 60 /mod d# 24 mod ( s m h ) + h# c0 cmos-alarm-month cmos! ( s m h ) \ Any day + h# c0 cmos-alarm-day cmos! ( s m h ) \ Any month + 5 bcd! 3 bcd! 1 bcd! ( ) + enable-alarm +; + +dend + +: show-rtc-wake ." R" ; + +d# 1 constant rtc-alarm-delay +: pm-sleep-rtc ( -- ) + 0 acpi-l@ h# 400.0000 or 0 acpi-l! \ Enable RTC SCI + ['] show-rtc-wake rtc-alarm-delay " set-alarm" clock-node @ $call-method + s + 0 acpi-l@ h# 400.0000 invert and 0 acpi-l! \ Disable RTC SCI +; +: rtc-wackup + 0 + begin pm-sleep-rtc space dup . (cr 1+ key? until + key drop +; + +stand-init: Century + h# 20 cmos-century cmos! \ The century is in BCD, hence h# +; + +\ LICENSE_BEGIN +\ Copyright (c) 2009 FirmWorks +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END
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