Author: wmb Date: Mon Jan 24 23:44:23 2011 New Revision: 2146 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2146
Log: OLPC XO-1.75 - flash-ec is now working on A2.
Modified: cpu/arm/olpc/1.75/devices.fth cpu/arm/olpc/1.75/ecflash.fth cpu/arm/olpc/1.75/edi.fth
Modified: cpu/arm/olpc/1.75/devices.fth ============================================================================== --- cpu/arm/olpc/1.75/devices.fth Fri Jan 21 23:19:08 2011 (r2145) +++ cpu/arm/olpc/1.75/devices.fth Mon Jan 24 23:44:23 2011 (r2146) @@ -143,6 +143,9 @@ : ofw-fw-filename$ " disk:\boot\olpc.rom" ; ' ofw-fw-filename$ to fw-filename$
+fload ${BP}/cpu/arm/olpc/1.75/bbedi.fth +fload ${BP}/cpu/arm/olpc/1.75/edi.fth + fload ${BP}/cpu/arm/olpc/1.75/ecflash.fth
0 0 " d420b000" " /" begin-package @@ -308,9 +311,6 @@ fload ${BP}/cpu/arm/olpc/1.75/accelerometer.fth fload ${BP}/cpu/arm/olpc/1.75/compass.fth
-fload ${BP}/cpu/arm/olpc/1.75/bbedi.fth -fload ${BP}/cpu/arm/olpc/1.75/edi.fth - warning @ warning off : stand-init stand-init
Modified: cpu/arm/olpc/1.75/ecflash.fth ============================================================================== --- cpu/arm/olpc/1.75/ecflash.fth Fri Jan 21 23:19:08 2011 (r2145) +++ cpu/arm/olpc/1.75/ecflash.fth Mon Jan 24 23:44:23 2011 (r2146) @@ -1,14 +1,19 @@ \ See license at end of file purpose: Reflash the EC code
-h# 10000 value /ec-flash
+[ifdef] cl2-a1 +h# 10000 value /ec-flash char 3 value expected-ec-version +[else] +h# 8000 value /ec-flash +char 4 value expected-ec-version +[then]
: check-signature ( adr -- ) - h# ff00 + ( adr' ) + /ec-flash + h# 100 - ( adr' ) dup " XO-EC" comp abort" Bad signature in EC image" ( adr ) - dup ." EC firmware verison: " cscount type cr ( adr ) + dup ." EC firmware version: " cscount type cr ( adr ) dup 6 + c@ expected-ec-version <> abort" Wrong EC version" ( adr ) drop ; @@ -31,20 +36,38 @@ ; : flash-ec ( "filename" -- ) get-ec-file +[ifdef] cl2-a1 " enter-updater" $call-ec ." Erasing ..." cr " erase-flash" $call-ec cr ." Writing ..." cr load-base /ec-flash 0 " write-flash" $call-ec cr ." Verifying ..." cr load-base /ec-flash + /ec-flash 0 " read-flash" $call-ec +[else] + use-edi-spi edi-open + ." Erasing ..." erase-chip cr + ." Writing ..." load-base /ec-flash 0 edi-program-flash cr + ." Verifying ..." + load-base /ec-flash + /ec-flash 0 edi-read-flash +[then] load-base load-base /ec-flash + /ec-flash comp - abort" Miscompare!" + abort" Miscompare!" cr +[ifndef] cl2-a1 + ." Restarting EC and powering off" cr + d# 3000 ms + unreset-8051 +[then] reset-ec ; : read-ec-flash ( -- ) +[ifdef] cl2-a1 " enter-updater" $call-ec flash-buf /ec-flash 0 " read-flash" $call-ec \ " reboot-ec" $call-ec +[else] + use-edi-spi edi-open + flash-buf /ec-flash 0 edi-read-flash +[then] ; : save-ec-flash ( "name" -- ) safe-parse-word $new-file
Modified: cpu/arm/olpc/1.75/edi.fth ============================================================================== --- cpu/arm/olpc/1.75/edi.fth Fri Jan 21 23:19:08 2011 (r2145) +++ cpu/arm/olpc/1.75/edi.fth Mon Jan 24 23:44:23 2011 (r2146) @@ -13,7 +13,7 @@ \ spi-out ( byte -- ) - Send byte \ spi-in ( -- byte ) - Receive byte
-h# 128 constant /flash-page +d# 128 constant /flash-page
: edi-cmd,adr ( offset cmd -- ) \ Send command plus 3 address bytes spi-cs-on ( offset cmd ) @@ -32,6 +32,7 @@ unloop exit then loop + spi-cs-off true abort" EDI byte in timeout" ; [then] @@ -114,7 +115,7 @@
: send-byte ( b offset -- ) set-offset h# feaa edi-b! 2 flash-cmd ;
-: program-page ( adr offset -- ) +: edi-program-page ( adr offset -- ) \ Clear HVPL wait-flash-busy h# 80 flash-cmd ( adr offset )
@@ -130,6 +131,14 @@ h# 70 flash-cmd ( ) wait-flash-busy ( ) ; +: edi-program-flash ( adr len offset -- ) + cr + swap 0 ?do + (cr i . + over i + over i + edi-program-page ( adr offset ) + /flash-page +loop ( adr offset ) + 2drop ( ) +; : edi-read-flash ( adr len offset -- ) over 0= if 3drop exit then ( adr len offset ) edi-b@ ( adr len byte ) @@ -138,44 +147,6 @@ edi-next-b@ i c! ( ) loop ( ) ; -: edi-open ( -- ) - \ slow-edi-clock \ Target speed between 1 and 2 MHz - spi-start - reset-8051 - \ fast-edi-clock \ Target speed up to 16 MHz - \ reset -; -0 [if] -+// IO3731 internal register locations -+#define E51_RST 0xf010 // 8051 Reset Control -+#define CODE_SEL 0xf011 // Code Source selection -+#define CHIP_ID_H 0xf01c // Chip ID High Byte -+#define CHIP_ID_L 0xf01d // Chip ID Low Byte -+#define IOSCCR 0xf02b // Internal OSC Control -+#define LVD_TRIM 0xf035 // Low Voltage Detect Trim -+#define XBIEFCFG 0xfea0 // XBI Embedded Flash Configuration -+#define XBIEFSIG1 0xfea1 // XBI Embedded Flash signals 1 in FW mode -+#define XBIEFSIG2 0xfea2 // XBI Embedded Flash signals 2 in FW mode -+#define XBIPUMP 0xfea3 // XBI Pump IP trimming bits -+#define XBIFM 0xfea4 // XBI Flash IP trimming bits -+#define XBIVR 0xfea5 // XBI VR IP trimming bits -+#define XBIMISC 0xfea6 // XBI MISC Reg -+#define XBIEFCMD 0xfea7 // XBI Embedded Flash Command Port -+#define XBIEFA0 0xfea8 // XBI Embedded Flash Address high -+#define XBIEFA1 0xfea9 // XBI Embedded Flash Address low -+#define XBIEFDO 0xfeaa // XBI Embedded Flash Output Data Port -+#define XBIEFDI 0xfeab // XBI Embedded Flash Input Data Port -+ -+ -+// IO3731 embedded flash command support: -+#define PAGE_LATCH 0x02 // Page latch -+#define READ 0x03 // Read -+#define ERASEPAGE 0x20 // Erase selected page -+#define ERASECHIP 0x60 // Erase whole e-flash -+#define PROGRAMPAGE 0x70 // Program selected page -+#define CLEARPAGELATCH 0x80 // Clear HVPL data -+#define READTRIMDATA 0x90 // Read Trim data from special rows -[then] : trim@ ( offset -- b ) set-offset h# 90 flash-cmd @@ -240,6 +211,16 @@ then \ then ; +: edi-open ( -- ) + \ slow-edi-clock \ Target speed between 1 and 2 MHz + spi-start + \ The first operation often fails so retry it + ['] select-flash catch if select-flash then + reset-8051 + trim-tune + \ fast-edi-clock \ Target speed up to 16 MHz + \ reset +;
\ LICENSE_BEGIN \ Copyright (c) 2011 FirmWorks
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