Author: wmb Date: Thu Oct 14 23:58:27 2010 New Revision: 1983 URL: http://tracker.coreboot.org/trac/openfirmware/changeset/1983
Log: Omnibus checkin of new ARM stuff, including Marvell TIM build support, timer management, ticker interrupts, DRAM init, and clock setting.
Added: cpu/arm/irqdispatch.fth cpu/arm/mmp2/cforth.bth cpu/arm/mmp2/clockset.fth cpu/arm/mmp2/irq.fth cpu/arm/mmp2/sp.bth Modified: cpu/arm/basefw.bth cpu/arm/mmp2/ddr_elpida_512m.fth cpu/arm/mmp2/devices.fth cpu/arm/mmp2/fw.bth cpu/arm/mmp2/mmuon.fth cpu/arm/mmp2/ofw.bth cpu/arm/mmp2/timer.fth cpu/arm/scc.fth
Modified: cpu/arm/basefw.bth ============================================================================== --- cpu/arm/basefw.bth Thu Oct 14 23:56:33 2010 (r1982) +++ cpu/arm/basefw.bth Thu Oct 14 23:58:27 2010 (r1983) @@ -7,7 +7,7 @@
" basefw.tag" r/w create-file drop tag-file !
-' $report-name is include-hook +\ ' $report-name is include-hook
create include-help \ Include help facility
@@ -21,7 +21,7 @@ fload ${BP}/cpu/arm/scc.fth \ System Control Coprocessor registers fload ${BP}/cpu/arm/traps.fth \ Exception handlers fload ${BP}/cpu/arm/psr.fth \ Special registers -fload ${BP}/cpu/arm/getms.fth \ Timer access +\ fload ${BP}/cpu/arm/getms.fth \ Timer access
fload ${BP}/cpu/arm/centry.fth \ Low-level client entry and exit fload ${BP}/cpu/arm/fb8-ops.fth \ 8-bit frame buffer primitives @@ -40,6 +40,7 @@ fload ${BP}/ofw/inet/loadtftp.fth \ Trivial File Transfer Protocol pkg.
fload ${BP}/cpu/arm/forthint.fth \ Alarm handler +fload ${BP}/cpu/arm/irqdispatch.fth \ IRQ dispatcher infrastructure
fload ${BP}/cpu/arm/regacc.fth \ Register access words
Added: cpu/arm/irqdispatch.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/irqdispatch.fth Thu Oct 14 23:58:27 2010 (r1983) @@ -0,0 +1,56 @@ +\ See license at end of file +purpose: Chip-independent part of interrupt dispatch code + +0 value pic-node +: enable-interrupt ( level -- ) " enable-irq" pic-node $call-method ; +: disable-interrupt ( level -- ) " disable-irq" pic-node $call-method ; + +: stray-interrupt ( level -- ) + ." Unexpected interrupt on IRQ" dup .d cr + disable-interrupt \ To prevent recurrence +; + +0 value interrupt-handlers +: interrupt-handler! ( xt int# -- ) + my-self swap interrupt-handlers swap 2* na+ 2! +; +: interrupt-handler@ ( int-level -- xt ) + interrupt-handlers swap 2* na+ 2@ drop +; + +: (dispatch-interrupt) ( -- ) " run-interrupt" pic-node $call-method ; + +: (init-dispatcher) ( -- ) + pic-node 0= if + " /interrupt-controller" open-dev to pic-node + " #levels" pic-node $call-method ( #levels ) + dup 2* /n* alloc-mem to interrupt-handlers ( #levels ) + 0 do ['] stray-interrupt i interrupt-handler! loop ( 0 ) + ['] (dispatch-interrupt) to dispatch-interrupt + then +; +' (init-dispatcher) to init-dispatcher + +\ LICENSE_BEGIN +\ Copyright (c) 2010 FirmWorks +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END
Added: cpu/arm/mmp2/cforth.bth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp2/cforth.bth Thu Oct 14 23:58:27 2010 (r1983) @@ -0,0 +1,52 @@ +purpose: Build Open Firmware for Marvell MMP2 +\ See license at end of file + +command: &builder &this +build-now + +fload ${BP}/cpu/arm/marvell/tim.fth + +\ Marvel Trusted Image Module image creation script for +\ MMP2 platform with 512M of Elpida RAM +\ Running OFW directly, with no intermediate loader + +tim: 00030102 0 Sky! PXA688 +flash: NAN'6 +timh: TIMH 0 d1020000 +\ Skip Marvell's Bad Block Table from 0x1000 to 0x7ffff +in: sp.img +in: fw.img +image: OBMI 80000 d101c000 /home/wmb/OLPC/1.75/dummy.img +image: WTMI 80400 d1000000 /home/wmb/OLPC/1.75/cforth-from-0xc0000.img +reserved: + +\ fload ${BP}/cpu/arm/mmp2/ddr_elpida_512m.fth + term: +end-reserved +end-tim + +save-image: cforth.rom + +\ LICENSE_BEGIN +\ Copyright (c) 2010 FirmWorks +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END
Added: cpu/arm/mmp2/clockset.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp2/clockset.fth Thu Oct 14 23:58:27 2010 (r1983) @@ -0,0 +1,20 @@ +: clk-fast + ffffffff d4050024 l! \ PMUM_CGR_SP \ All clocks ON + 00061808 d4282888 l! \ PMUA_DEBUG \ Reserved bits, but supposed to "allow freq" + + 00000000 d4050008 l! \ Startup operation point + 08fd96d9 d4282800 l! \ PMUA_CC_SP \ speed change voting, ACLK:7, DCLK:5, BACLK1:1, PCLK:0 + 78fd96d9 d4282804 l! \ PMUA_CC_PJ \ + + \ select PLL2 frequency, 520MHz + 08600322 d4050414 l! \ PMUM_PLL2_CTRL1 \ Bandgap+charge pump+VCO loading+regulator defaults, 486.3-528.55 PLL2 (bits 10:6) + 00FFFE00 d4050034 l! \ PMUM_PLL2_CTRL2 \ refclk divisor and feedback divisors at max, software controls activation + 0021da00 d4050034 l! \ PMUM_PLL2_CTRL1 \ refclk divisor=4, feedback divisor=0x76=118, software controls activation + 0021db00 d4050034 l! \ PMUM_PLL2_CTRL2 \ same plus enable + 28600322 d4050414 l! \ PMUM_PLL2_CTRL1 \ same as above plus release PLL loop filter + \ select clock source, PJ4-PLL1, SP-PLL1/2, AXI/DDR-PLL1 + 20800000 d4050008 l! \ PMUM_FCCR PLL1 > PJ4 (bits 31:29), PLL1/2 > SP (bits 28:26), PLL1 > AXI&DDR (bits 25:23) + \ divider setting and frequency change request, core-800, ddr-400, axi-200 + 08fd8248 d4282800 l! \ PMUA_CC_SP \ speed change voting, ACLK:7, DCLK:5, BACLK1:1, PCLK:0 + 78fd8248 d4282804 l! \ PMUA_CC_PJ \ +;
Modified: cpu/arm/mmp2/ddr_elpida_512m.fth ============================================================================== --- cpu/arm/mmp2/ddr_elpida_512m.fth Thu Oct 14 23:56:33 2010 (r1982) +++ cpu/arm/mmp2/ddr_elpida_512m.fth Thu Oct 14 23:58:27 2010 (r1983) @@ -6,12 +6,12 @@ gpio: d0000030 00006420 \ SDRAM_CONFIG_TYPE1-CS1 gpio: d0000b40 00000000 \ SDRAM_CONFIG_TYPE2-CS0 gpio: d0000b50 00000000 \ SDRAM_CONFIG_TYPE2-CS1 - gpio: d0000050 488700c5 \ SDRAM_TIMING1 - gpio: d0000060 323300d2 \ SDRAM_TIMING2 - gpio: d0000190 20000e12 \ SDRAM_TIMING3 + gpio: d0000050 488700c5 \ SDRAM_TIMING1 !4cda00c5 tRTP 2>3, tWTR 2>3, tRC 7>1a (7>26) + gpio: d0000060 323300d2 \ SDRAM_TIMING2 !94860342 tRP 3>9, tRRD 2>4, tRCD 3>8, tWR 3>6, tRFC d>34 + gpio: d0000190 20000e12 \ SDRAM_TIMING3 !2000381b ACS_EXIT_DLY 0>3, ACS_TIMER e>8, OUTEN 0>1, RSVD 0>1 gpio: d00001c0 3023009d \ SDRAM_TIMING4 - gpio: d0000650 00050082 \ SDRAM_TIMING5 - gpio: d0000660 00909064 \ SDRAM_TIMING6 + gpio: d0000650 00050082 \ SDRAM_TIMING5 ! 110142 tRAS 5>11, tFAW 8>14 + gpio: d0000660 00909064 \ SDRAM_TIMING6 ! 2424190 tZQCS 9>24, tZQOPER 24>90, tZQINIT 64>190 gpio: d0000080 00005000 \ SDRAM_CTRL1 gpio: d0000090 00080010 \ SDRAM_CTRL2 gpio: d00000f0 c0000000 \ SDRAM_CTRL3 @@ -31,16 +31,16 @@ gpio: d00005b0 00000000 \ MCB_SLFST_CTRL3 gpio: d0000180 00000000 \ CM_WRITE_PROTECTION gpio: d0000210 00000000 \ PHY_CTRL11 - gpio: d0000240 80000000 \ PHY_CTRL14 - gpio: d0000240 2000ce00 \ PHY_CTRL14 - gpio: d0000240 0000ce00 \ PHY_CTRL14 + gpio: d0000240 80000000 \ PHY_CTRL14 - PHY sync enable + gpio: d0000240 2000ce00 \ PHY_CTRL14 - PHY DLL Reset (20000000) + gpio: d0000240 0000ce00 \ PHY_CTRL14 - release reset gpio: d0000200 0011ce00 \ PHY_CTRL10 gpio: d0000200 0010311c \ PHY_CTRL10 - gpio: d0000140 20004422 \ PHY_CTRL3 + gpio: d0000140 20004422 \ PHY_CTRL3 !20004444 PHY_RFIFO_RPTR_DLY_VAL 2>4, DQ_EXT_DLY 2>4 gpio: d00001d0 13300559 \ PHY_CTRL7 (0x2330_0339 / 0x133C_2559) gpio: d00001e0 03300990 \ PHY_CTRL8 gpio: d00001f0 00000077 \ PHY_CTRL9 - gpio: d0000230 20000088 \ PHY_CTRL13 (0x2000_0108 / 0x2024_0109) + gpio: d0000230 20000088 \ PHY_CTRL13 (0x2000_0108 / 0x2024_0109) gpio: d0000e10 00000080 \ PHY_DLL_CTRL1 gpio: d0000e20 00000080 \ PHY_DLL_CTRL2 gpio: d0000e30 00000080 \ PHY_DLL_CTRL3
Modified: cpu/arm/mmp2/devices.fth ============================================================================== --- cpu/arm/mmp2/devices.fth Thu Oct 14 23:56:33 2010 (r1982) +++ cpu/arm/mmp2/devices.fth Thu Oct 14 23:58:27 2010 (r1983) @@ -1,7 +1,17 @@ fload ${BP}/dev/omap/diaguart.fth \ OMAP UART h# d4018000 to uart-base \ UART# base address on MMP2 d# 26000000 to uart-clock-frequency -defer init-clocks ' noop to init-clocks + +: init-clocks + -1 h# d4051024 l! \ PMUM_CGR_PJ - everything on + h# 07 h# d4015064 l! \ APBC_AIB_CLK_RST - reset, functional and APB clock on + h# 03 h# d4015064 l! \ APBC_AIB_CLK_RST - release reset, functional and APB clock on + h# 13 h# d4015034 l! \ APBC_UART3_CLK_RST - VCTCXO, functional and APB clock on (26 mhz) + h# c1 h# d401e120 l! \ GPIO51 = af1 for UART3 RXD + h# c1 h# d401e124 l! \ GPIO52 = af1 for UART3 TXD + h# 1b h# d4282854 l! \ SD0 clocks +; + : inituarts ( -- ) init-clocks
@@ -33,8 +43,8 @@ \ This devalias lets us say, for example, "dir rom:" devalias rom /dropin-fs
-fload ${BP}/cpu/arm/mmp2/twsi.fth fload ${BP}/cpu/arm/mmp2/timer.fth +fload ${BP}/cpu/arm/mmp2/twsi.fth fload ${BP}/cpu/arm/mmp2/mfpr.fth : init-stuff set-camera-domain-voltage @@ -51,6 +61,7 @@ ;
fload ${BP}/cpu/arm/mmp2/gpio.fth +fload ${BP}/cpu/arm/mmp2/irq.fth
fload ${BP}/cpu/arm/mmp2/watchdog.fth \ reset-all using watchdog timer
@@ -118,11 +129,33 @@
fload ${BP}/ofw/termemu/cp881-16.fth
-d# 3000 to ms-factor - fload ${BP}/cpu/arm/mmp2/sdhcimmp2.fth
devalias ext /sd/disk@1
fload ${BP}/dev/olpc/kb3700/spicmd.fth - + + +\ LICENSE_BEGIN +\ Copyright (c) 2010 FirmWorks +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END
Modified: cpu/arm/mmp2/fw.bth ============================================================================== --- cpu/arm/mmp2/fw.bth Thu Oct 14 23:56:33 2010 (r1982) +++ cpu/arm/mmp2/fw.bth Thu Oct 14 23:58:27 2010 (r1983) @@ -170,9 +170,7 @@ warning off : stand-init-io stand-init-io - ." Going fast" cr go-fast \ From mmuon.fth - ." Gone fast" cr ; warning on [then] @@ -238,11 +236,6 @@
standalone? if disable-interrupts -hex - here . cr - limit . cr - initial-heap . . cr - vector-base . cr [ifdef] notdef d# 1000 i-key-wait if @@ -500,6 +493,10 @@ .( --- Saving fw.dic ...) " fw.dic" $save-forth cr
+fload ${BP}/cpu/arm/mmp2/rawboot.fth + +.( --- Saving fw.img --- ) cr " fw.img" $save-rom + \ LICENSE_BEGIN \ Copyright (c) 2010 FirmWorks \
Added: cpu/arm/mmp2/irq.fth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp2/irq.fth Thu Oct 14 23:58:27 2010 (r1983) @@ -0,0 +1,66 @@ +\ See license at end of file +purpose: Interrupt controller node for Marvell MMP2 (PXA688) + +0 0 " d4282000" " /" begin-package + +" interrupt-controller" device-name +my-address my-space h# 400 reg + +0 value base-adr +d# 64 constant #levels + +: ic@ ( offset -- l ) base-adr + rl@ ; +: ic! ( l offset -- ) base-adr + rl! ; + +: block-irqs ( -- ) 1 h# 110 ic! ; +: unblock-irqs ( -- ) 0 h# 110 ic! ; + +: enable-irq ( level -- ) h# 21 swap /l* ic! ; \ Enable for IRQ1 +: disable-irq ( level -- ) 0 swap /l* ic! ; + +: run-interrupt ( -- ) + h# 104 ic@ dup h# 40 and if ( reg ) + h# 3f and ( level ) + dup disable-irq ( level ) + dup interrupt-handlers over 2* na+ 2@ ( level level xt ih ) + package( execute )package ( level ) + enable-irq ( ) + else ( reg ) + drop ( ) + then ( ) +; + +: open ( -- flag ) + my-space to base-adr + block-irqs + d# 64 0 do i disable-irq loop + unblock-irqs + true +; +: close ( -- ) ; + +end-package + +\ LICENSE_BEGIN +\ Copyright (c) 2010 FirmWorks +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END
Modified: cpu/arm/mmp2/mmuon.fth ============================================================================== --- cpu/arm/mmp2/mmuon.fth Thu Oct 14 23:56:33 2010 (r1982) +++ cpu/arm/mmp2/mmuon.fth Thu Oct 14 23:58:27 2010 (r1983) @@ -26,6 +26,7 @@ h# 0000.0000 h# c0e over fb-pa map-sections \ Cache and write bufferable \ fw-pa h# c0e over /fw-ram map-sections \ Cache and write bufferable fb-pa h# c06 over fb-size map-sections \ Write bufferable + h# d100.0000 h# c0e over fb-pa map-sections \ Cache and write bufferable (SRAM) h# d400.0000 h# c02 over h# 0040.0000 map-sections \ I/O - no caching or buffering ;
@@ -67,6 +68,8 @@ start-mmu dcache-on icache-on - d# 400,000 to ms-factor - d# 400 to us-factor +\ l2cache-on \ Leave off for now, to avoid potential problems with Linux + bpu-on +\ d# 400,000 to ms-factor +\ d# 400 to us-factor ;
Modified: cpu/arm/mmp2/ofw.bth ============================================================================== --- cpu/arm/mmp2/ofw.bth Thu Oct 14 23:56:33 2010 (r1982) +++ cpu/arm/mmp2/ofw.bth Thu Oct 14 23:58:27 2010 (r1983) @@ -1,24 +1,33 @@ purpose: Build Open Firmware for Marvell MMP2 \ See license at end of file
-dictionary: ${BP}/cpu/arm/mmp2/build/fw.dic -command: &armforth &dictionary &this +in: sp.img +in: fw.img +command: &builder &this build-now
-: (init-clocks) - -1 h# d4051024 l! \ PMUM_CGR_PJ - everything on - h# 07 h# d4015064 l! \ APBC_AIB_CLK_RST - reset, functional and APB clock on - h# 03 h# d4015064 l! \ APBC_AIB_CLK_RST - release reset, functional and APB clock on - h# 13 h# d4015034 l! \ APBC_UART3_CLK_RST - VCTCXO, functional and APB clock on (26 mhz) - h# c1 h# d401e120 l! \ GPIO51 = af1 for UART3 RXD - h# c1 h# d401e124 l! \ GPIO52 = af1 for UART3 TXD - h# 1b h# d4282854 l! \ SD0 clocks -; -' (init-clocks) to init-clocks +fload ${BP}/cpu/arm/marvell/tim.fth
-fload ${BP}/cpu/arm/mmp2/rawboot.fth +\ Marvel Trusted Image Module image creation script for +\ MMP2 platform with 512M of Elpida RAM +\ Running OFW directly, with no intermediate loader
-.( --- Saving ofw.rom --- ) cr " ofw.rom" $save-rom +tim: 00030102 0 Sky! PXA688 +flash: NAN'6 +timh: TIMH 0 d1020000 +\ Skip Marvell's Bad Block Table from 0x1000 to 0x7ffff +\ Secure Processor code loaded into SRAM +image: WTMI 80000 d1000000 sp.img +\ Main Processor code loaded into DRAM +image: OBMI 84000 0 fw.img +reserved: + + fload ${BP}/cpu/arm/mmp2/ddr_elpida_512m.fth + term: +end-reserved +end-tim + +save-image: ofw.rom
\ LICENSE_BEGIN \ Copyright (c) 2010 FirmWorks
Added: cpu/arm/mmp2/sp.bth ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ cpu/arm/mmp2/sp.bth Thu Oct 14 23:58:27 2010 (r1983) @@ -0,0 +1,396 @@ +purpose: Load file for ARM Forth kernel +\ See license at end of file + +command: &builder &this +build-now + +[ifndef] arm-assembler \ Make sure we have the ARM assembler +only forth also definitions + +fload ${BP}/forth/lib/bitops.fth +\needs set-relocation-bit defer set-relocation-bit \ keep init-assem happy + +\ only forth also meta also definitions + +fload ${BP}/cpu/arm/assem.fth +fload ${BP}/cpu/arm/code.fth + +[then] +: assembler ( -- ) arm-assembler ; +: setreg \ reg value ( -- ) + safe-parse-word $hnumber abort" Bad number" + safe-parse-word $hnumber abort" Bad number" + swap + " set r1,``" evaluate + " set r0,``" evaluate + " str r0,[r1]" evaluate +; +: getreg \ reg ( -- ) + safe-parse-word $hnumber abort" Bad number" + " set r1,``" evaluate + " ldr r0,[r1]" evaluate +; +: putreg \ reg ( -- ) + " str r0,[r1]" evaluate +; +: bitset \ reg ( -- ) + safe-parse-word $hnumber abort" Bad number" + " orr r0,r0,``" evaluate +; +: bitclr \ reg ( -- ) + safe-parse-word $hnumber abort" Bad number" + " bic r0,r0,``" evaluate +; + +label unreset + \ From jasper.c + setreg d4051024 ffffffff \ PMUM_CGR_PJ - Clocks on + + setreg D42828dc 1FFFF \ PMUA_GLB_CLK_CTRL - Enable CLK66 to APB, PLL2/12/6/3/16/8/4/2/1, PLL1/12/6/3/16/8/4 + + setreg D4015064 07 \ AIB clock + setreg D4015064 03 \ AIB clock + + setreg D4015034 13 \ UART3 clk - 26 MHz + + getreg D401E160 \ G_CLK_REQ + bitset 4000 \ Enable pullup + putreg + + setreg D4015000 83 \ APBC_RTC_CLK_RST - Enable RTC clock and power + + setreg D4015024 05 \ APBC_TIMERS1_CLK_RST - Reset + setreg D4015024 33 \ APBC_TIMERS1_CLK_RST - Enable Timers at 26 MHz + + getreg d4282c08 \ SCU_PJ4_CPU_CONF + bitset 40 \ Bit 6 - bypass clock gate + bitset 200 \ Bit 9 - allow CPU in WFI to be woken up by Multi-ICE as well as by interrupt + bitset 2000 \ Bit 13 - disable MMU translation abort for L2 cache + bitset 4000 \ Bit 14 - bypass clock gate in L2 cache + bitset 80000 \ Bit 19 - L2 Cache burst 8 enable + bitclr 800000 \ Bit 23 - use slow queue for CPU to DDR access + putreg + + \ Now change the frequency + \ from freq_ll.S + + set r4, 0xd0000000 \ DMEM base address + set r5, 0xd4050000 \ PMUM base address + set r6, 0xd4282800 \ PMUA base address + + set r7, 0xffffffff \ All clocks ON + str r7, [r5, #0x0024] \ PMUM_CGR_SP + set r7, 0x00061808 \ Reserved bits, but supposed to "allow freq" + str r7, [r6, #0x88] \ PMUA_DEBUG + + \ change to PLL1/2 first, start-up operation point + set r7, 0x00000000 + str r7, [r5, #0x8] + set r7, 0x08fd96d9 + str r7, [r6, #0x00] + set r7, 0x78fd96d9 + str r7, [r6, #0x04] + + \ select PLL2 frequency, 520MHz + set r7, 0x08600322 \ Bandgap+charge pump+VCO loading+regulator defaults, 486.3-528.55 PLL2 (bits 10:6) + str r7, [r5, #0x0414] \ PMUM_PLL2_CTRL1 + set r7, 0x00FFFE00 \ refclk divisor and feedback divisors at max, software controls activation + str r7, [r5, #0x0034] \ PMUM_PLL2_CTRL2 + set r7, 0x0021da00 \ refclk divisor=4, feedback divisor=0x76=118, software controls activation + str r7, [r5, #0x0034] \ PMUM_PLL2_CTRL1 + set r7, 0x0021db00 \ same plus enable + str r7, [r5, #0x0034] \ PMUM_PLL2_CTRL2 + set r7, 0x28600322 \ same as above plus release PLL loop filter + str r7, [r5, #0x0414] \ PMUM_PLL2_CTRL1 + \ select clock source, PJ4-PLL1, SP-PLL1/2, AXI/DDR-PLL1 + set r7, 0x20800000 \ PLL1 > PJ4 (bits 31:29), PLL1/2 > SP (bits 28:26), PLL1 > AXI&DDR (bits 25:23) + str r7, [r5, #0x0008] \ PMUM_FCCR + \ divider setting and frequency change request, core-800, ddr-400, axi-200 + set r7, 0x08fd8248 \ speed change voting, ACLK:3, DCLK:0, BACLK1:1, PCLK:0 + str r7, [r6, #0x00] \ PMUA_CC_SP + set r7, 0x78fd8248 \ etc - hard to decipher + str r7, [r6, #0x04] \ PMUA_CC_PJ + + \ DDR recalibration after frequency change + \ CONFIG_DECODE_ADDR + set r7, 0xD0004D56 + str r7, [r4, #0x010] + + \ This is for Elpida DDR2 512M + \ MMAP + set r7, 0x000C0001 + str r7, [r4, #0x100] + set r7, 0x100C0001 + str r7, [r4, #0x110] + + \ CONFIG_TYPE + set r7, 0x00006420 + str r7, [r4, #0x020] + set r7, 0x00006420 + str r7, [r4, #0x030] + set r7, 0x00000000 + str r7, [r4, #0xB40] + set r7, 0x00000000 + str r7, [r4, #0xB50] + + \ TIMING + set r7, 0x4CDA00C5 + str r7, [r4, #0x050] + set r7, 0x94860342 + str r7, [r4, #0x060] + set r7, 0x2000381B + str r7, [r4, #0x190] + set r7, 0x3023009D + str r7, [r4, #0x1C0] + set r7, 0x00110142 + str r7, [r4, #0x650] + set r7, 0x02424190 + str r7, [r4, #0x660] + \ End of Elpida-specific stuff + + \ CTRL + set r7, 0x00005000 + str r7, [r4, #0x080] + set r7, 0x00080010 + str r7, [r4, #0x090] + set r7, 0xC0000000 + str r7, [r4, #0x0F0] + set r7, 0x20C08115 + str r7, [r4, #0x1A0] + set r7, 0x01010101 + str r7, [r4, #0x280] + set r7, 0x00000000 + str r7, [r4, #0x760] + set r7, 0x03000000 + str r7, [r4, #0x770] + set r7, 0x00000133 + str r7, [r4, #0x780] + set r7, 0x01010101 + str r7, [r4, #0x7B0] + set r7, 0x0000000F + str r7, [r4, #0x7D0] + set r7, 0x00000000 + str r7, [r4, #0x7E0] + + \ MCB + set r7, 0x00000000 + str r7, [r4, #0x540] + set r7, 0x00000001 + str r7, [r4, #0x570] + set r7, 0x00000000 + str r7, [r4, #0x580] + set r7, 0x00000000 + str r7, [r4, #0x590] + set r7, 0x00000000 + str r7, [r4, #0x5A0] + set r7, 0x00000000 + str r7, [r4, #0x5B0] + + \ WRITE_PROTECTION + set r7, 0x00000000 + str r7, [r4, #0x180] + + \ __PHY Deskew PLL config and PHY initialization + set r7, 0x00000000 + str r7, [r4, #0x210] + set r7, 0x80000000 + str r7, [r4, #0x240] + + \ DLL reset, Need this after any DCLK freq change + set r8, 0x20000000 + ldr r7, [r4, #0x240] + orr r7, r7, r8 + str r7, [r4, #0x240] + set r8, 0xdFFFFFFF + ldr r7, [r4, #0x240] + and r7, r7, r8 + str r7, [r4, #0x240] + + \ Pad drive strength auto calibration + set r8, 0x00110000 + ldr r7, [r4, #0x200] + orr r7, r7, r8 + str r7, [r4, #0x200] + ldr r7, [r4, #0x240] + set r8, 0xFFFeFFFF + ldr r7, [r4, #0x200] + and r7, r7, r8 + str r7, [r4, #0x200] + + \ Elpida DDR2 512M-specific + set r7, 0x20004444 + str r7, [r4, #0x140] + set r7, 0x13300559 + str r7, [r4, #0x1D0] + set r7, 0x03300990 + str r7, [r4, #0x1E0] + set r7, 0x00000077 + str r7, [r4, #0x1F0] + \ End of Elpida-specific + + set r7, 0x20000088 + str r7, [r4, #0x230] + set r7, 0x00000080 + str r7, [r4, #0xE10] + set r7, 0x00000080 + str r7, [r4, #0xE20] + set r7, 0x00000080 + str r7, [r4, #0xE30] + + set r7, 0x00000000 + str r7, [r4, #0xE40] + set r7, 0x00000000 + str r7, [r4, #0xE50] + + \ initialize LPDDR2 + set r7, 0x03000001 + str r7, [r4, #0x120] + ldr r7, [r4, #0x1B0] + set r7, 0x0302003F + str r7, [r4, #0x410] + set r7, 0x01001000 + str r7, [r4, #0x120] + set r7, 0x02001000 + str r7, [r4, #0x120] + set r7, 0x03020001 + str r7, [r4, #0x410] + set r7, 0x03020002 + str r7, [r4, #0x410] + set r7, 0x03020003 + str r7, [r4, #0x410] + +\ End of frequency change + + setreg d4282110 0 \ Release global IRQ0 mask + + setreg d4283894 11000008 \ DFI chip select timing configuration for CS1 + + setreg d428290c 600 \ Power up audio module + setreg d428290c 610 \ and enable peripheral clock + setreg d428290c 710 \ and disable isolation + setreg d428290c 712 \ and release reset + + setreg d4050040 d0080040 \ I2S0 SYSCLK_EN, PLL1/2, denom=0x10, numerator=0x40 + setreg d4050044 d0040040 \ I2S0 SYSCLK_EN, PLL1/2, denom=0x08, numerator=0x40 + + setreg d42a0c3c 10800 \ Undocumented register in SSPA + setreg d42a0c34 211921 \ Undocumented register in SSPA + + setreg d428285c 08 \ Enable AXI clock to USB + setreg d428285c 09 \ and release from reset + + setreg d42828f8 18 \ Enable HSIC1 SPH Controller Clock and AXI Clock + setreg d42828f8 1b \ and release from reset + + setreg d42828fc 18 \ Undocumented, probably another USB HSIC + setreg d42828fc 1b \ Undocumented .. + + setreg d4282900 18 \ Enable FSIC SPH Controller Clock and AXI Clock + setreg d4282900 1b \ and release from reset + + setreg d4282848 08 \ Enable AXI clock to IRE + setreg d4282848 09 \ and release from reset + + setreg D4015004 03 \ Enable TWSI1 clk + \ Delay 99999 + + setreg d4282854 1b \ Enable SDHC0 clk + setreg d42828e8 1b \ Enable SDHC3 clk + + getreg d42828a4 \ Vmeta + bitset 400 \ Module powered up + bitclr 200 \ Inputs isolated + putreg + bitset 008 \ AXI clock enabled + putreg + bitset 001 \ AXI released from reset + putreg + bitset 010 \ Peripheral clock enabled + putreg + bitset 002 \ Peripheral released from reset + putreg + bitset 020 \ PLL2/3 + putreg + bitset 004 \ Reserved + putreg + bitset 100 \ Isolation disabled + putreg + bitclr 240 \ Input isolation disabled, (bit 6 is part of the clock select field) + putreg + \ Whew, that was tedious + + setreg d428284c 08 \ PMUA_DISPLAY1_CLK_RES_CTL - AXI Clk enabled + setreg d428284c 09 \ plus AXI released from reset + setreg d428284c 19 \ plus peripheral clock enabled + setreg d428284c 1b \ plus peripheral released from reset + + setreg d4015038 03 \ Use 32 kHz clock input (bit 1 reserved) + +\ mrc p15,0,r0,c1,c0,2 +\ orr r0,r0,#0xf \ Enable MMX +\ mcr p15,0,r0,c1,c0,2 + +\ Allow access of performance counters (PMU) from user space +\ mov r0, #0x1 +\ mrc p15, 0, r0, c9, c14, 0 +\ orr r0, r0, #0x1 +\ mcr p15, 0, r0, c9, c14, 0 + +\ Ensure branch prediction is enabled - BPU (Default) +\ mrc p15, 0, r0, c1, c0, 0 +\ orr r0, r0, #0x800 +\ mcr p15, 0, r0, c1, c0, 0 + +\ setreg d4015064 03 \ AIB clock, redundant with above + +\ //BU_REG_WRITE( SMC_CSDFICFGX, 0x51890009 ); // SMC_CSDFICFG0 +\ //BU_REG_WRITE( SMC_CSADRMAPX, 0x10000F00 ); // SMC_CSADRMAP0 +\ //BU_REG_WRITE(0xd4283824, 0xC6CFF2C9 ); +\ setreg d4283894 11000008 \ DFI, redundant with above + +\ setreg d4015000 83 \ RTC, redundant with above + setreg d4015074 03 \ MPMU, clocks on + setreg d4282864 09 \ DMA enabled and release from reset + setreg d4282860 b8 \ NAND FLASH PLL1/8 + ECC PLL1/4, AXI clock enabled + setreg d4282860 bf \ plus ECC&controller&AXI released from reset + +\ Finally, release the reset for the main CPU + + set r0,0xd4050020 + ldr r1,[r0] + bic r1,r1,#2 + str r1,[r0] + + begin + mcr p15,0,r0,cr7,cr0,4 \ Wait For Interrupt + again + +end-code + +writing sp.img + unreset here over - ofd @ fputs +ofd @ fclose + +\ LICENSE_BEGIN +\ Copyright (c) 2008 FirmWorks +\ +\ Permission is hereby granted, free of charge, to any person obtaining +\ a copy of this software and associated documentation files (the +\ "Software"), to deal in the Software without restriction, including +\ without limitation the rights to use, copy, modify, merge, publish, +\ distribute, sublicense, and/or sell copies of the Software, and to +\ permit persons to whom the Software is furnished to do so, subject to +\ the following conditions: +\ +\ The above copyright notice and this permission notice shall be +\ included in all copies or substantial portions of the Software. +\ +\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +\ +\ LICENSE_END
Modified: cpu/arm/mmp2/timer.fth ============================================================================== --- cpu/arm/mmp2/timer.fth Thu Oct 14 23:56:33 2010 (r1982) +++ cpu/arm/mmp2/timer.fth Thu Oct 14 23:58:27 2010 (r1983) @@ -22,7 +22,7 @@ ;
-code timer0@ ( -- n ) \ 3.25 MHz +code timer0@ ( -- n ) \ 6.5 MHz psh tos,sp set r1,0xD4014000 mov r0,#1 @@ -48,3 +48,109 @@ mov r0,r0 ldr tos,[r1,#0x30] c; + +: timer0-status@ ( -- n ) h# d4014034 l@ ; +: timer1-status@ ( -- n ) h# d4014038 l@ ; +: timer2-status@ ( -- n ) h# d401403c l@ ; + +: timer0-ier@ ( -- n ) h# d4014040 l@ ; +: timer1-ier@ ( -- n ) h# d4014044 l@ ; +: timer2-ier@ ( -- n ) h# d4014048 l@ ; + +: timer0-icr! ( n -- ) h# d4014074 l! ; +: timer1-icr! ( n -- ) h# d4014078 l! ; +: timer2-icr! ( n -- ) h# d401407c l! ; + +: timer0-ier! ( n -- ) h# d4014040 l! ; +: timer1-ier! ( n -- ) h# d4014044 l! ; +: timer2-ier! ( n -- ) h# d4014048 l! ; + +: timer0-match0! ( n -- ) h# d4014004 l! ; : timer0-match0@ ( -- n ) h# d4014004 l@ ; +: timer0-match1! ( n -- ) h# d4014008 l! ; : timer0-match1@ ( -- n ) h# d4014008 l@ ; +: timer0-match2! ( n -- ) h# d401400c l! ; : timer0-match2@ ( -- n ) h# d401400c l@ ; + +: timer1-match0! ( n -- ) h# d4014010 l! ; : timer1-match0@ ( -- n ) h# d4014010 l@ ; +: timer1-match1! ( n -- ) h# d4014014 l! ; : timer1-match1@ ( -- n ) h# d4014014 l@ ; +: timer1-match2! ( n -- ) h# d4014018 l! ; : timer1-match2@ ( -- n ) h# d4014018 l@ ; + +: timer2-match0! ( n -- ) h# d401401c l! ; : timer2-match0@ ( -- n ) h# d401401c l@ ; +: timer2-match1! ( n -- ) h# d4014020 l! ; : timer2-match1@ ( -- n ) h# d4014020 l@ ; +: timer2-match2! ( n -- ) h# d4014024 l! ; : timer2-match2@ ( -- n ) h# d4014024 l@ ; + +' timer2@ to get-msecs +: (ms) ( delay-ms -- ) + get-msecs + begin ( limit ) + pause ( limit ) + dup get-msecs - ( limit delta ) + 0< until ( limit ) + drop +; +' (ms) to ms + +: us ( delay-us -- ) + d# 13 2 */ timer0@ + ( limit ) + begin ( limit ) + dup timer0@ - ( limit delta ) + 0< until ( limit ) + drop +; + +\ Timing tools +variable timestamp +: t-update ; +: t( ( -- ) timer0@ timestamp ! ; +: ))t ( -- ticks ) timer0@ timestamp @ - ; +: ))t-usecs ( -- usecs ) ))t 2 d# 13 */ ; +: )t ( -- ) + ))t-usecs ( microseconds ) + push-decimal + <# u# u# u# [char] , hold u# u#s u#> type ." us " + pop-base +; +: t-msec( ( -- ) timer2@ timestamp ! ; +: ))t-msec ( -- msecs ) timer2@ timestamp @ - ; +: )t-msec ( -- ) + ))t-msec + push-decimal + <# u# u#s u#> type ." ms " + pop-base +; + +: t-sec( ( -- ) t-msec( ; +: ))t-sec ( -- secs ) ))t-msec d# 1000 / ; +: )t-sec ( -- ) + ))t-sec + push-decimal + <# u# u#s u#> type ." s " + pop-base +; + +: .hms ( seconds -- ) + d# 60 /mod d# 60 /mod ( sec min hrs ) + push-decimal + <# u# u#s u#> type ." :" <# u# u# u#> type ." :" <# u# u# u#> type + pop-base +; +: t-hms( ( -- ) t-sec( ; +: )t-hms + ))t-sec ( seconds ) + .hms +; + +: reschedule-tick ( -- ) + timer2@ ms/tick + timer2-match0! + 1 timer2-icr! +; +: tick-interrupt ( level -- ) + drop + reschedule-tick + check-alarm +; +: (set-tick-limit) ( interval -- ) + to ms/tick + reschedule-tick + timer2-ier@ 1 or timer2-ier! + ['] tick-interrupt d# 15 interrupt-handler! \ d# 15 is the IRQ# for timer0 in the first timer block + d# 15 enable-interrupt +; +' (set-tick-limit) to set-tick-limit
Modified: cpu/arm/scc.fth ============================================================================== --- cpu/arm/scc.fth Thu Oct 14 23:56:33 2010 (r1982) +++ cpu/arm/scc.fth Thu Oct 14 23:58:27 2010 (r1983) @@ -42,10 +42,38 @@ code flush-d$-entry ( va -- ) mcr p15,0,tos,cr7,cr6,1 pop tos,sp c; code flush-d$-entry-way ( sw -- ) mcr p15,0,tos,cr7,cr6,2 pop tos,sp c;
-code flush-i&d$ ( -- ) mcr p15,0,r0,cr7,cr7,0 c; -code flush-u$ ( -- ) mcr p15,0,r0,cr7,cr7,0 c; -code flush-u$-entry ( va -- ) mcr p15,0,tos,cr7,cr7,1 pop tos,sp c; -code flush-u$-way ( sw -- ) mcr p15,0,tos,cr7,cr7,2 pop tos,sp c; +code flush-i&d$ ( -- ) mcr p15,1,r0,cr7,cr7,0 c; +code flush-u$ ( -- ) mcr p15,1,r0,cr7,cr7,0 c; +code flush-u$-entry ( va -- ) mcr p15,1,tos,cr7,cr7,1 pop tos,sp c; +code flush-u$-way ( sw -- ) mcr p15,1,tos,cr7,cr7,2 pop tos,sp c; + +code clean-l2$ ( -- ) mcr p15,1,r0,cr7,cr11,0 c; +code clean-l2$-entry ( va -- ) mcr p15,1,tos,cr7,cr11,1 pop tos,sp c; +code clean-l2$-way ( ws -- ) mcr p15,1,tos,cr7,cr11,2 pop tos,sp c; +code clean-l2$-pa ( pa -- ) mcr p15,1,tos,cr7,cr11,3 pop tos,sp c; + +code flush-l2$ ( -- ) mcr p15,1,r0,cr7,cr7,0 c; +code flush-l2$-entry ( va -- ) mcr p15,1,tos,cr7,cr7,1 pop tos,sp c; +code flush-l2$-way ( ws -- ) mcr p15,1,tos,cr7,cr7,2 pop tos,sp c; +code flush-l2$-pa ( pa -- ) mcr p15,1,tos,cr7,cr7,3 pop tos,sp c; + +code clean&flush-l2$ ( -- ) mcr p15,1,r0,cr7,cr15,0 c; +code clean&flush-l2$-entry ( va -- ) mcr p15,1,tos,cr7,cr15,1 pop tos,sp c; +code clean&flush-l2$-way ( ws -- ) mcr p15,1,tos,cr7,cr15,2 pop tos,sp c; +code clean&flush-l2$-pa ( pa -- ) mcr p15,1,tos,cr7,cr15,3 pop tos,sp c; + +\ Bit 24 is L2 prefetch disable, bit 23 is L2 ECC enable +code l2$-efr ( n -- ) mcr p15,1,tos,cr15,cr1,0 pop tos,sp c; + +code l2$-lockdown-way ( bits -- ) mcr p15,1,tos,cr15,cr10,7 pop tos,sp c; + +code l2$-error@ ( -- n ) psh tos,sp mcr p15,1,tos,cr15,cr9,6 c; +code l2$-error! ( n -- ) mcr p15,1,tos,cr15,cr9,6 pop tos,sp c; + +code l2$-error-threshold@ ( -- n ) psh tos,sp mcr p15,1,tos,cr15,cr9,7 c; +code l2$-error-threshold! ( n -- ) mcr p15,1,tos,cr15,cr9,7 pop tos,sp c; + +code l2$-error-capture@ ( -- n ) psh tos,sp mcr p15,1,tos,cr15,cr11,7 c;
code clean-d$ ( -- ) mcr p15,0,r0,cr7,cr10,0 c; code clean-d$-entry ( va -- ) mcr p15,0,tos,cr7,cr10,1 pop tos,sp c; @@ -65,8 +93,6 @@ code clean&flush-u$-entry ( va -- ) mcr p15,0,tos,cr7,cr15,1 pop tos,sp c; code clean&flush-u$-entry-way ( sw -- ) mcr p15,0,tos,cr7,cr15,2 pop tos,sp c;
- - code drain-write-buffer ( -- ) mcr p15,0,r0,cr7,cr10,4 c; alias data-sync-barrier drain-write-buffer code drain-write-buffer ( -- ) mcr p15,0,r0,cr7,cr10,4 c; @@ -136,6 +162,12 @@ \ operation, so it uses the Open Firmware nomenclature. defer flush-cache ' noop to flush-cache
+: l2cache-on ( -- ) flush-l2$ control@ h# 0400.0000 or control! ; +: l2cache-off ( -- ) clean-l2$ control@ h# 0400.0000 invert and control! ; + +: bpu-on ( -- ) flush-bt$ control@ h# 0800 or control! ; +: bpu-off ( -- ) control@ h# 0800 invert and control! ; + : icache-on ( -- ) flush-i$ control@ h# 1000 or control! ; : icache-off ( -- ) control@ h# 1000 invert and control! ; : dcache-on ( -- ) flush-d$ control@ 4 or control! ;
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