Author: wmb Date: 2009-05-03 10:44:29 +0200 (Sun, 03 May 2009) New Revision: 1166
Modified: cpu/x86/pc/olpc/via/addrs.fth cpu/x86/pc/olpc/via/config.fth cpu/x86/pc/olpc/via/demodram.fth cpu/x86/pc/olpc/via/devices.fth cpu/x86/pc/olpc/via/fw.bth cpu/x86/pc/olpc/via/olpc.bth cpu/x86/pc/olpc/via/probemem.fth cpu/x86/pc/olpc/via/rmstart.fth cpu/x86/pc/olpc/via/romreset.bth cpu/x86/pc/resetend.fth cpu/x86/pc/virtaddr.fth Log: Via demo version - Checkpoint of current state.
Modified: cpu/x86/pc/olpc/via/addrs.fth =================================================================== --- cpu/x86/pc/olpc/via/addrs.fth 2009-04-29 22:52:13 UTC (rev 1165) +++ cpu/x86/pc/olpc/via/addrs.fth 2009-05-03 08:44:29 UTC (rev 1166) @@ -23,7 +23,7 @@ h# 40.0000 constant /fw-area [then]
-h# 80.0000 constant def-load-base \ Convenient for initrd +h# 100.0000 constant def-load-base \ Convenient for initrd
\ The heap starts at RAMtop, which on this system is "fw-pa /fw-ram +"
@@ -53,13 +53,12 @@ h# fec0.0000 constant ioapic-mmio-base h# fed0.0000 constant hpet-mmio-base h# fed3.0000 constant spi-mmio-base -h# fed4.0000 constant wdt-mmio-bast +h# fed4.0000 constant wdt-mmio-base +h# fee0.0000 constant apic-mmio-base
h# 4000 constant acpi-io-base h# 4100 constant smbus-io-base
-h# 9.fc00 constant 'ebda \ Extended BIOS Data Area, which we co-opt for our real-mode workspace - h# e0000 constant rsdp-adr h# e0040 constant rsdt-adr h# e0080 constant fadt-adr
Modified: cpu/x86/pc/olpc/via/config.fth =================================================================== --- cpu/x86/pc/olpc/via/config.fth 2009-04-29 22:52:13 UTC (rev 1165) +++ cpu/x86/pc/olpc/via/config.fth 2009-05-03 08:44:29 UTC (rev 1166) @@ -11,7 +11,7 @@ \ - OBMD format - ROM - direct boot from ROM create rom-loaded
-\ create virtual-mode +create virtual-mode create addresses-assigned \ Define if base addresses are already assigned \ create serial-console \ Define to default to serial port for console create pc
Modified: cpu/x86/pc/olpc/via/demodram.fth =================================================================== --- cpu/x86/pc/olpc/via/demodram.fth 2009-04-29 22:52:13 UTC (rev 1165) +++ cpu/x86/pc/olpc/via/demodram.fth 2009-05-03 08:44:29 UTC (rev 1166) @@ -42,7 +42,7 @@ 66 ff 00 mreg \ Burst DRDR Timing Control for Second cycle in burst 67 ff 00 mreg \ Reserved, probably channel B 54 0a 08 mreg \ Misc ctl 1 - special mode for DRAM cycles - 51 00 80 mreg \ Last step - enable DRDY timing - should the mask be f7 ? + 51 80 80 mreg \ Last step - enable DRDY timing end-table
\ DRAMBurstLength @@ -125,7 +125,7 @@ 57 ff 00 mreg \ default PR4=VR4; PR5=VR5
60 ff 00 mreg \ disable fast turn-around - 65 ff D9 mreg \ AGP timer = D; Host timer = 8; + 65 ff d1 mreg \ AGP timer = D; Host timer = 1; (coreboot uses 9 for host timer) 66 ff 88 mreg \ DRAMC Queue Size = 4; park at the last bus owner,Priority promotion timer = 8 68 ff 0C mreg 69 0F 04 mreg \ set RX69[3:0]=0000b @@ -276,14 +276,6 @@ 96 0f 03 mreg \ Enable self-refresh for ranks 0 and 1 end-table
- 0 4 devfunc \ PM_table - a0 f0 f0 mreg \ Enable dynamic power management - a1 e0 e0 mreg \ Dynamic power management for DRAM - a2 ff fe mreg \ Dynamic clock stop controls - a3 80 80 mreg \ Toggle reduction on - a5 81 81 mreg \ "Reserved" - end-table - 1 [if] ax ax xor h# 12345678 # bx mov
Modified: cpu/x86/pc/olpc/via/devices.fth =================================================================== --- cpu/x86/pc/olpc/via/devices.fth 2009-04-29 22:52:13 UTC (rev 1165) +++ cpu/x86/pc/olpc/via/devices.fth 2009-05-03 08:44:29 UTC (rev 1166) @@ -20,19 +20,22 @@
fload ${BP}/cpu/x86/pc/olpc/via/smbus.fth \ SMBUS driver
-\ Do this early so the interact timing works right -: stand-init-io ( -- ) - stand-init-io - +stand-init: CPU node d# 1,500,000,000 " VIA,C7"
" /cpu" find-device ( cpu-clock-hz model$ ) " model" string-property ( cpu-clock-hz ) " clock-frequency" integer-property ( ) device-end ( ) +;
+\ Do this early so the interact timing works right +warning @ warning off +: stand-init-io ( -- ) + stand-init-io acpi-calibrate-tsc ; +warning !
[ifdef] use-ega 0 0 " " " /" begin-package
Modified: cpu/x86/pc/olpc/via/fw.bth =================================================================== --- cpu/x86/pc/olpc/via/fw.bth 2009-04-29 22:52:13 UTC (rev 1165) +++ cpu/x86/pc/olpc/via/fw.bth 2009-05-03 08:44:29 UTC (rev 1166) @@ -228,7 +228,6 @@ support-package: nfs fload ${BP}/ofw/fs/nfs/loadpkg.fth end-support-package - [then] devalias nfs net//obp-tftp:last//nfs
@@ -267,7 +266,6 @@
standalone? if disable-interrupts -\ interact d# 1000 i-key-wait if [ifdef] Later
Modified: cpu/x86/pc/olpc/via/olpc.bth =================================================================== --- cpu/x86/pc/olpc/via/olpc.bth 2009-04-29 22:52:13 UTC (rev 1165) +++ cpu/x86/pc/olpc/via/olpc.bth 2009-05-03 08:44:29 UTC (rev 1166) @@ -21,8 +21,8 @@ in: ${BP}/clients/emacs/x86/emacs in: ${BP}/cpu/x86/pc/olpc/via/build/verify.img in: ${BP}/dev/pci/build/pcibridg.fc +in: ${BP}/dev/ide/build/leghier.fc \ in: ${BP}/cpu/x86/pc/olpc/via/build/camera.fc -\ VIA-PATA \ in: ${BP}/cpu/x86/pc/olpc/via/build/dsdt.aml \ in: ${BP}/cpu/x86/pc/olpc/via/build/mcastnand.bin \ in: ${BP}/dev/hdaudio/build/hdaudio.fc @@ -66,13 +66,11 @@ " resume.di" $add-file [then]
-[ifndef] Later \ Loads the set of drivers that is common to different output formats
-\ " paging.di" $add-file + " paging.di" $add-file " ${BP}/cpu/x86/build/inflate.bin" " inflate" $add-dropin " fw.img" " firmware" $add-deflated-dropin -[then]
" ${BP}/dev/usb2/hcd/ohci/build/ohci.fc" " class0c0310" $add-deflated-dropin " ${BP}/dev/usb2/hcd/ehci/build/ehci.fc" " class0c0320" $add-deflated-dropin @@ -84,6 +82,7 @@ " ${BP}/dev/usb2/device/storage/build/usbstorage.fc" " usbstorage" $add-deflated-dropin \ " mrv8686.bin" " mrv8686.bin" $add-deflated-dropin
+ " ${BP}/dev/ide/build/leghier.fc" " class01018a" $add-deflated-dropin " ${BP}/dev/mmc/sdhci/build/sdhci.fc" " class080501" $add-deflated-dropin " ${BP}/dev/mmc/sdhci/build/sdmmc.fc" " sdmmc" $add-deflated-dropin " builton.fth" " probe-" $add-dropin
Modified: cpu/x86/pc/olpc/via/probemem.fth =================================================================== --- cpu/x86/pc/olpc/via/probemem.fth 2009-04-29 22:52:13 UTC (rev 1165) +++ cpu/x86/pc/olpc/via/probemem.fth 2009-05-03 08:44:29 UTC (rev 1166) @@ -2,16 +2,20 @@ purpose: Create memory node properties and lists
\ All RAM, including that assigned to the frame buffer +0 value total-ram-cached : total-ram ( -- ramsize ) + total-ram-cached ?dup if exit then \ Search for the last "top of rank" value h# 340 h# 343 do i config-b@ ?dup if ( chunks ) \ Each chunk is 64 MiB d# 26 lshift ( bytes ) + dup to total-ram-cached unloop exit then -1 +loop ." Can't get total RAM size!" cr h# 1000.0000 + dup to total-ram-cached ;
\ Offset of frame buffer/display memory within the memory array
Modified: cpu/x86/pc/olpc/via/rmstart.fth =================================================================== --- cpu/x86/pc/olpc/via/rmstart.fth 2009-04-29 22:52:13 UTC (rev 1165) +++ cpu/x86/pc/olpc/via/rmstart.fth 2009-05-03 08:44:29 UTC (rev 1166) @@ -84,19 +84,14 @@
\ ffff.fc00 GDT
- 0 w, 0 l, 0 w, \ 0 Mandatory null descriptor - 0 w, 0 l, 0 w, \ * Another null descriptor + 1f w, ffff.fc00 l, 0 w, \ 0 Pointer to GDT in first slot + 0 w, 0 l, 0 w, \ * Null descriptor ffff w, 9b.000000 l, 00.c.f w, \ 10 Code, linear=physical, full 4Gbytes ffff w, 93.000000 l, 00.c.f w, \ 18 Data, linear=physical, full 4Gbytes
- \ ffff.fc20 GDT limit + address - - 1f w, ffff.fc00 l, \ # slots (4 * 8 - 1) , starting address - 0 w, \ Padding - \ ------->>>>> Startup code, reached by branch from main entry point below \ - \ ffff.fc28 + \ ffff.fc20
here \ Mark the beginning of this code so its size may be determined \ and so that a jump to it may be assembled later. @@ -127,7 +122,7 @@ \ above is reachable with a 16-bit address and through the "boosted" \ code segment.
- op: cs: 0f c, 01 c, 16 c, fc20 w, \ lgdte cs:[fc20] Setup GDT + op: cs: 0f c, 01 c, 16 c, fc00 w, \ lgdte cs:[fc00] Setup GDT
op: cr0 bx mov \ Get existing CR0 value
@@ -179,8 +174,8 @@
here over - ( adr , size-of-preceding-code )
- \ ffff.fc28 is the location of the code that follows the GDT - ffff.fff0 ffff.fc28 - swap - ( address #bytes-to-pad ) + \ ffff.fc20 is the location of the code that follows the GDT + ffff.fff0 ffff.fc20 - swap - ( address #bytes-to-pad )
\ The code mustn't extend past ffff.ffc0, because that is where PC \ manufacturers put the 0x10-byte BIOS version string. @@ -196,7 +191,7 @@
16-bit cli cld \ Turn off interrupts (does not affect NMI) - #) jmp \ Relative jump back to ffff.fc28 + #) jmp \ Relative jump back to ffff.fc20 0 w, 0 c, \ align "pad" to end of ROM loader-version# l, \ version# loader-format# w, \ "format" (>1 when crc present)
Modified: cpu/x86/pc/olpc/via/romreset.bth =================================================================== --- cpu/x86/pc/olpc/via/romreset.bth 2009-04-29 22:52:13 UTC (rev 1165) +++ cpu/x86/pc/olpc/via/romreset.bth 2009-05-03 08:44:29 UTC (rev 1166) @@ -323,12 +323,12 @@ \ Enable extended config space for PCIe 0 5 devfunc \ NB_APIC 61 ff 0e mreg \ Set Exxxxxxx as PCIe MMIO config range - 60 f4 0b mreg \ Support extended cfg address of PCIe (preserve 28 bits) + 60 f4 13 mreg \ Support extended cfg address of PCIe (preserve 28 bits) (coreboot used vx800 bit resv in vx855) end-table
0 2 devfunc \ HOST CPU CTL 50 1f 08 mreg \ Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 - 51 ff 7c mreg \ CPU I/F Ctrl-1: Disable Fast DRDY and RAW + 51 ff 78 mreg \ CPU I/F Ctrl-1: Disable Fast DRDY and RAW (coreboot uses 7c) 52 cb cb mreg \ CPU I/F Ctrl-2: Enable all for performance 53 ff 44 mreg \ Arbitration: Host/Master Occupancy timer = 4*4 HCLK 54 1e 1c mreg \ Misc Ctrl: Enable 8QW burst Mem Access @@ -345,13 +345,76 @@ 97 ff 00 mreg \ APIC Related Control end-table
+fload ${BP}/cpu/x86/pc/olpc/via/demodram.fth + 0 3 devfunc - 86 d6 29 mreg \ SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg + 86 38 38 mreg \ SMM and APIC Decoding: enable APIC lowest int arb, IOAPIC split decode, MSI (SMM later) end-table
-fload ${BP}/cpu/x86/pc/olpc/via/demodram.fth
+\ Also from FinalSetting.c
+ 0 4 devfunc \ PM_table + a0 80 80 mreg \ Enable dynamic power management (coreboot for vx800 uses f0; 70 bits are reserved on vx855) + a1 e0 e0 mreg \ Dynamic power management for DRAM + a2 d6 d6 mreg \ Dynamic clock stop controls (coreboot for vx8000 uses ff fe; 29 bits are reserved on vx800) + a3 80 80 mreg \ Toggle reduction on + a5 81 81 mreg \ "Reserved" + + \ Additional PM settings not in coreboot + 84 ff db mreg \ Dynamic clocks + 85 ff 05 mreg \ Dynamic clocks + 89 ff f8 mreg \ Dynamic clocks + 8b ff bf mreg \ Dynamic clocks + 8d ff 20 mreg \ Self-refresh in C3 and C4 + 90 ff ff mreg \ Gate clocks + 91 ff ff mreg \ Gate clocks + 92 cc cc mreg \ Dynamic buffer control, power down comparators + a8 20 20 mreg \ Central traffic controller dynamic clock stop + end-table + + \ Additional Power Management Setup not in coreboot + 0 2 devfunc + 76 08 08 mreg \ AGTL Power down buffers in S3 + 92 ff 40 mreg \ ACPI IO Base address + end-table + + 0 3 devfunc + 86 38 38 mreg \ SMM and APIC Decoding: enable APIC lowest int arb, IOAPIC split decode, MSI (SMM later) + end-table + + 0 5 devfunc + 54 8f 80 mreg \ SM request gets high priority, PCCA occupancy timer off + 55 0f 04 mreg \ PCCA P2C Promote Timer value 4 + 59 0f 02 mreg \ IGFX Promote Timer value 2 + 5f 0f 06 mreg \ IPI Promote Timer value 6 + 64 20 00 mreg \ Upstream MSI doesn't flush queued P2C Write Data + 80 0b 08 mreg \ Upstream Request 1T earlier + 83 ff 81 mreg \ P2PW down arb timer timer 8, P2PR down arb timer timer 1 + 84 7f 28 mreg \ Downstream arbitration Timeout timer for C2P + 85 c0 c0 mreg \ Abort P2P cycle to PCI1, CPU to PCI1 cycle blocks next C2P cycle + end-table + + d# 12 0 devfunc \ SDIO tuning + 44 01 01 mreg \ Enable backdoor + 8b 05 05 mreg \ Report both 1.8V and 3.3V + 8c c3 03 mreg \ Falling edge trigger for Slots 1 and 2 data in high speed + 8e ff 7e mreg \ Delay host clock for Slots 1, 2, 3 by 4.8 nS + 8f 09 0a mreg \ Falling edge trigger on slot 3 output clock under high speed + 99 ff f9 mreg \ Two slots not 3 (FIXME for OLPC) + end-table + + d# 15 0 devfunc \ EIDE tuning + 40 02 01 mreg \ Enable primary channel + 4a ff 5e mreg \ Drive1 timing + 4b ff 20 mreg \ Drive0 timing + 4c f0 60 mreg \ Address setup time + 52 df 0e mreg \ Ultra dma wait strobe timing + 53 df c6 mreg \ Ultra DMA mode control + c4 1d 18 mreg \ Config 1 + d4 ac 24 mreg \ Config 3 + end-table + \ UMARamSetting.c \ SetUMARam 0 3 devfunc @@ -361,7 +424,7 @@ a6 ff 76 mreg \ Page register life timer a7 ff 8c mreg \ Internal GFX allocation b3 ff 9a mreg \ Disable read past write - de ff 06 mreg \ Enable CHA and CHB merge mode (but description says this value disable merging!) +\ de ff 06 mreg \ Enable CHA and CHB merge mode (but description says this value disable merging!) 00 for compatibility end-table
0 3 devfunc @@ -379,6 +442,7 @@ cd01 3a0 config-ww \ Set frame buffer size and CPU-relative address and enable
0 0 devfunc + c6 02 02 mreg \ Enable MDA forwarding (not in coreboot) d4 00 03 mreg \ Enable MMIO and S.L. access in Host Control device fe 00 10 mreg \ 16-bit I/O port decoding for VGA (no aliases) end-table @@ -416,11 +480,19 @@
\ cache_as_ram_auto.c : enable_shadow_ram 0 3 devfunc + +\ Initial DOS hole settings, so the firmware can set things up 80 ff ff mreg \ Enable R/W memory access to Cxxxx bank 81 ff ff mreg \ Enable R/W memory access to Dxxxx bank 82 ff ff mreg \ Enable R/W memory access to Exxxx bank 83 30 30 mreg \ Enable R/W memory access to Fxxxx bank (30), no memory hole (0c), SMM switching of Axxxx bank (03) -\ 86 ff 85 mreg \ 4 MiB Top SMM Memory (80), enable top SMM memory (04), enable compatible SMM (01) + +\ Final DOS hole settings, after stuff has been copied in, for reference +\ 80 ff 2a mreg \ CC000-CFFFF off, C0000-C7FFF RO +\ 81 ff 00 mreg \ D0000-DFFFF off +\ 82 ff aa mreg \ E0000-EFFFF RO +\ 83 ff 20 mreg \ Enable R/W memory access to Fxxxx bank (20), no memory hole (0c), SMM switching of Axxxx bank (03) + end-table
\ Low 2 bits of 86: @@ -428,6 +500,17 @@ \ 00 to run - Axxxxx hits VGA in normal mode, hits shadow DRAM in SMM \ 01 to access VGA when in SMM (data cycles only)
+ \ APIC setup + 0 2 devfunc + 59 01 01 mreg \ MSI Flat model support + 5c 10 10 mreg \ Data bit 11 mask for MSI + 97 01 01 mreg \ Redirect lowest priority MSI requests to APIC 00 + end-table + + 0 3 devfunc + 86 38 38 mreg \ SMM and APIC Decoding: enable APIC lowest int arb, IOAPIC split decode, MSI (SMM later) + end-table + h# 1c00.0000 # mem-info-pa 4 + #) mov \ Top of memory
long-offsets on
Modified: cpu/x86/pc/resetend.fth =================================================================== --- cpu/x86/pc/resetend.fth 2009-04-29 22:52:13 UTC (rev 1165) +++ cpu/x86/pc/resetend.fth 2009-05-03 08:44:29 UTC (rev 1166) @@ -7,7 +7,7 @@ \ Beginning of "switch to new GDT" section
\ Move GDT to low memory. We use the first location at gdt-pa as - \ scratch memory for sgdt, and put the actual gdt at gdt-pa + 0x10 + \ the pointer, so you can't use description 0. gdt-pa # ax mov 0 [ax] sgdt \ Read GDT 2 [ax] si mov \ GDT base @@ -15,11 +15,11 @@ ffff # cx and cx inc
- gdt-pa h# 10 + # di mov \ New GDT base + gdt-pa # di mov \ New GDT base rep movsb \ Copy ROM GDT to RAM
\ Move the code and data descriptors to 60,68 - gdt-pa h# 10 + h# 60 + # di mov \ Destination - New descriptor 0x60 + gdt-pa h# 60 + # di mov \ Destination - New descriptor 0x60
cs si mov 2 [ax] si add \ Source - Current code descriptor movs movs \ 2 longwords (1 descriptor) -> 60 @@ -27,8 +27,8 @@ ds si mov 2 [ax] si add \ Source - Current data descriptor movs movs \ 2 longwords (1 descriptor) -> 68
- op: h# ff # 0 [ax] mov \ New GDT size - gdt-pa h# 10 + # 2 [ax] mov \ New GDT base + op: gdt-size 1- # 0 [ax] mov \ New GDT size + gdt-pa # 2 [ax] mov \ New GDT base 0 [ax] lgdt \ Setup RAM GDT
\ Reload code segment descriptor from new table
Modified: cpu/x86/pc/virtaddr.fth =================================================================== --- cpu/x86/pc/virtaddr.fth 2009-04-29 22:52:13 UTC (rev 1165) +++ cpu/x86/pc/virtaddr.fth 2009-05-03 08:44:29 UTC (rev 1166) @@ -1,8 +1,13 @@ \ See license at end of file purpose: Defines Open Firmware virtual address space
+\ Low RAM +h# 580 constant gdt-pa \ Above the BDA, below the MBR area at 600 +h# 80 constant gdt-size + h# 1000 constant mem-info-pa -h# 1040 constant gdt-pa +h# 9.fc00 constant 'ebda \ Extended BIOS Data Area, which we co-opt for our real-mode workspace + [ifdef] virtual-mode h# 2000 constant pdir-pa h# 3000 constant pt-pa
openfirmware@openfirmware.info
-
svn＠openfirmware.info