Author: wmb Date: 2009-10-12 09:51:36 +0200 (Mon, 12 Oct 2009) New Revision: 1418
Modified: cpu/x86/pc/olpc/via/demodram.fth cpu/x86/pc/olpc/via/ioinit.fth cpu/x86/pc/olpc/via/starthostctl.fth Log: Via - folded in a few register settings as recommended by Via, and added commentary relative to a few others.
Modified: cpu/x86/pc/olpc/via/demodram.fth =================================================================== --- cpu/x86/pc/olpc/via/demodram.fth 2009-10-11 09:19:26 UTC (rev 1417) +++ cpu/x86/pc/olpc/via/demodram.fth 2009-10-12 07:51:36 UTC (rev 1418) @@ -228,6 +228,8 @@ 0 3 devfunc 50 ee ee mreg \ DDR default MA7 for DRAM init 51 ee 60 mreg \ DDR default MA3 for CHB init + \ Via says 11, 1F gives slightly better performance in their environment, + \ but that setting doesn't work for us - it crashes with Forth+X+ 52 ff 33 mreg \ DDR use BA0=M17, BA1=M18, 53 ff 3F mreg \ DDR BA2=M19
@@ -240,7 +242,7 @@ 65 ff d1 mreg \ AGP timer = D; Host timer = 1; (coreboot uses 9 for host timer) 66 ff 88 mreg \ DRAMC Queue Size = 4; park at the last bus owner,Priority promotion timer = 8 68 ff 0C mreg - 69 0F 04 mreg \ set RX69[3:0]=0000b + 69 0F 04 mreg \ Disable multiple page and page active for now, enable refresh priority 6A ff 00 mreg \ refresh counter 6E 87 80 mreg \ must set 6E[7],or else DDR2 probe test will fail 85 ff 00 mreg @@ -327,9 +329,9 @@
0 3 devfunc forth #banks 8 = assembler [if] - 69 c3 c3 mreg \ Reinstate page optimizations (03) 8-bank interleave (c0) + 69 c3 c3 mreg \ Enable page optimizations (03) 8-bank interleave (c0) [else] - 69 c3 83 mreg \ Reinstate page optimizations (03) 4-bank interleave (80) + 69 c3 83 mreg \ Enable page optimizations (03) 4-bank interleave (80) [then]
Modified: cpu/x86/pc/olpc/via/ioinit.fth =================================================================== --- cpu/x86/pc/olpc/via/ioinit.fth 2009-10-11 09:19:26 UTC (rev 1417) +++ cpu/x86/pc/olpc/via/ioinit.fth 2009-10-12 07:51:36 UTC (rev 1418) @@ -43,6 +43,11 @@ 89 ff f8 mreg \ Dynamic clocks 8b ff bf mreg \ Dynamic clocks 8d ff 30 mreg \ Self-refresh in C3 and C4 + \ LuckeLin at Via says: If D0F4 Rx8e[5] was set to 0, we could turn-off PLL in S1 state. + \ If your machine does not support S1, it was fine to set it to 1 at all time. + \ (wmb adds - D0F4 Rx8e[5] needs to be set to 1 before entering S3, even if set to 0 for S1) + \ LuckeLin also says: [Phoenix] Set(s) Rx8e[4] to 1 to fix another S3 issue. Chip internal control + \ signal was hard-wired to 1 in new chip. It does not control anything. Please just keep it to be default setting. 8e ff 20 mreg \ Leave PLL on in suspend state - necessary for reliable S3 90 ff ff mreg \ Gate clocks 91 ff ff mreg \ Gate clocks
Modified: cpu/x86/pc/olpc/via/starthostctl.fth =================================================================== --- cpu/x86/pc/olpc/via/starthostctl.fth 2009-10-11 09:19:26 UTC (rev 1417) +++ cpu/x86/pc/olpc/via/starthostctl.fth 2009-10-12 07:51:36 UTC (rev 1418) @@ -25,6 +25,7 @@
55 06 04 mreg \ Miscellaneous Control 2 56 f7 63 mreg \ Write Policy 1 + 57 01 01 mreg \ Enable fast TRDY by detecting HREQa[5]# de-assertion 5d ff a2 mreg \ Write Policy 5e ff 88 mreg \ Bandwidth Timer 5f 46 46 mreg \ CPU Misc Ctrl